Week 2-1-Nabil(2).pdf

Chapter # 2 The Microprocessor and Its Architecture 1 Week # 2, Lecture 1 Dr. Qurban Ali, EE Department, revised by Nabil Bastaki – Fall 2022 Interfacing the CPU with memory / IO System bus: consist of control, address and data Control bus CPU Data bus Address bus Memory / IO A Simple CPU Data lines...

Chapter # 2 The Microprocessor and Its Architecture 1 Week # 2, Lecture 1 Dr. Qurban Ali, EE Department, revised by Nabil Bastaki – Fall 2022 Interfacing the CPU with memory / IO System bus: consist of control, address and data Control bus CPU Data bus Address bus Memory / IO A Simple CPU Data lines Clock D7 D6 D5 D4 D3 D2 D1 D0 A Simple CPU A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address lines RD’ Read WR’ Write 4 Internal architecture of the 8088/8086 ´ 8088 and 8086 have similar architectures. Two units operate in parallel ´ Bus interface unit (BIU) ´ Execution unit (EU) ´ The fetch and execute operations are independent and operate in parallel CPU Execution Unit Instruction pipeline System bus Bus Interface Unit o In a multiple core chip, each core contains the same (programming) model. Dr. Qurban Ali, EE Department The BIU – (1) 5 ´ The BIU is responsible for: Instruction pipeline ´ Instruction fetching Bus Interface Unit ´ Reading and writing data operands from/to memory ´ Inputting and outputting data from/to peripherals (i.e., attached devices) ´ Instruction queuing and address generation ´ BIU transfers information using the system bus which includes ´ 8-bit bidirectional data bus for 8088 (16 for 8086) ´ 20-bit address bus ´ Control signals needed to transfer data over the bus Dr. Qurban Ali, EE Department The BIU – (2) 6 ´ BIU contains: ´ Segment registers ´ Instruction pointer (IP) ´ Address generation adder ´ Bus control logic ´ Instruction queue (4 bytes in 8088 and 6 bytes in 8086) ´ BIU pre-fetches instructions when it’s not being asked to access data from memory ´ The instruction queue is a FIFO. Instructions are automatically shifted closer to the output. Dr. Qurban Ali, EE Department The EU 7 ´ The execution unit is responsible for: ´ Decoding instructions; Executing instructions ´ EU consists of: ´ Arithmetic logic unit, Status and control flags ´ General purpose and temporary-operand registers ´ EU performs the following steps: ´ Reads from FIFO one instruction at a time ´ Decodes the instruction read ´ Read data from GPRs, and generates data addresses if necessary ´passes them to the BIU and requests BIU to perform read or write cycle to memory or I/O ´ Performs the operation specified ´ During execution, EU may test flags and updates them based on the results of the execution ´ If queue is empty, EU waits for next instruction byte to be Dr. Qurban Ali, EE Department fetched and shifted to top of the queue Detailed Internal Architecture (Full view) - 1 8 q q q q q The system has several parallel operating units The EU uses the general registers to store the operands. Instruction queue size: four bytes for 8088; six bytes for 8086. The segment registers store the base addresses of external memory. The instruction pointer stores the offset address of the instruction. The flags are typically used to indicate the status of an operation. Dr. Qurban Ali, EE Department The Software/Programming Model (the simplest) 9 8088/8086 MPU IP CS DS SS ES AH BH CH DH External memory address space Code segment (64 K bytes) AL AX BL BX CL CX DL DX SP BP SI DI SR Data segment (64 K bytes) Stack segment (64 K bytes) 0000016 000016 Input / output address space FFFF16 Extra segment (64 K bytes) FFFFF16 The simplest software architecture of 8088 consists of 13 registers: 4 segment registers (CS, DS, SS, ES); 4 data registers (AX, BX, CX, DX); 2 index registers (SI, DI); 2 pointer register (SP, BP); and an instruction pointer (IP). Each register is 16-bit long. Dr. Qurban Ali, EE Department Figure 2–1 The programming model of the 8086 through Core2 microprocessor including the 64-bit extensions program-visible registers used during programming and are specified by the instructions o 80286 and above contain program-invisible registers n to control and operate protected memory and other features of the microprocessor n not addressable directly during applications programming Multipurpose Registers ´ RAX - a 64-bit register (RAX), a 32-bit register (accumulator) (EAX), a 16-bit register (AX), or as either of two 8-bit registers (AH and AL). ´The accumulator is used for instructions such as multiplication, division, and some of the adjustment instructions. ´Intel plans to expand the address bus to 52 bits to address 4P (peta) bytes of memory. ´ RBX, addressable as RBX, EBX, BX, BH, BL. ´BX register (base index) sometimes holds offset address of a location in the memory system in all versions of the microprocessor Multipurpose Registers – cont. ´ RCX, as RCX, ECX, CX, CH, or CL. ´a (count) general-purpose register that also holds the count for various instructions ´ RDX, as RDX, EDX, DX, DH, or DL. ´a (data) general-purpose register ´holds a part of the result from a multiplication or part of dividend before a division ´ RBP, as RBP, EBP, or BP. ´points to a memory (base pointer) location for memory data transfers ´ RDI addressable as RDI, EDI, or DI. ´often addresses (destination index) string destination data for the string instructions Registers – cont. ´ RSI used as RSI, ESI, or SI. ´the (source index) register addresses source string data for the string instructions ´like RDI, RSI also functions as a generalpurpose register ´ R8 - R15 found in the Pentium 4 and Core2 if 64-bit extensions are enabled. ´data are addressed as 64-, 32-, 16-, or 8-bit sizes and are of general purpose ´Most applications do not use these registers until 64-bit processors are common. ´the 8-bit portion is the rightmost 8-bit only ´bits 8-15 aren’t directly addressable as a byte Segment Registers o Segment registers include CS, DS, ES, SS, FS, and GS ´ Generate memory addresses when combined with other registers in the microprocessor. ´ Four or six segment registers in various versions of the microprocessor. ´ A segment register functions differently in real mode than in the protected mode. ´ Following is a list of each segment and its register, along with its function in the system. Memory Segment & Registers ´ CS (code) segment holds code (programs and procedures) used by the microprocessor à CS register ´ DS (data) contains most data used by a program à DS register ´Data are accessed by an offset address or contents of other registers that hold the offset address ´ ES (extra) an additional data segment used by some instructions to hold destination data à ES register ´ SS (stack) defines the area of memory used for the stack à SS register ´stack entry point is determined by the stack segment and stack pointer registers ´the BP register also addresses data within the stack segment ´ FS and GS segments are supplemental segment registers available in 80386–Core2 microprocessors à FS and GS registers ´allow two additional memory segments for access by programs ´Windows uses these segments for internal operations, but no definition of their usage is available. Special-Purpose Registers ´ RIP addresses the next instruction in a section of memory. ´defined as (instruction pointer) in a code segment ´ RSP addresses an area of memory called the stack. ´the stack stores data through this pointer ´ RFLAGS indicate the condition of the microprocessor and control its operation. ´ Figure 2–2 shows the flag registers of all versions of the microprocessor. ´ Flags are upward-compatible from the 8086/8088 through Core2. ´ The rightmost five and the overflow flag are changed by most arithmetic and logic operations. ´although data transfers do not affect them Figure 2–2 The EFLAG and FLAG register counts for the entire 8086 and Pentium microprocessor family. Flag bits, with a brief description of function ´ C (carry) holds the carry after addition or borrow after subtraction. ´ also indicates error conditions ´ P (parity) is the count of ones in a number expressed as even or odd. Logic 0 for odd parity; logic 1 for even parity. ´ if a number contains three binary one bits, it has odd parity ´ if a number contains no one bits, it has even parity ´ A (auxiliary carry) holds the carry (half-carry) after addition or the borrow after subtraction between bit positions 3 and 4 of the result. ´ Z (zero) shows that the result of an arithmetic or logic operation is zero. If Z=0, the result is not zero. ´ S (sign) flag holds the arithmetic sign of the result after an arithmetic or logic instruction executes. ´ T (trap) The trap flag enables trapping through an on-chip debugging feature. If TF=1, the 8086 gets interrupted after each instruction. ´ I (interrupt) controls operation of the INTR (interrupt request) input pin. ´ D (direction) selects increment or decrement mode for the DI and/or SI registers. If D=1, the registers are decremented. ´ O (overflow) occurs when signed numbers are added or subtracted. ´ an overflow indicates the result has exceeded the capacity of the machine register. ´ IOPL used in protected mode operation to select the privilege level for I/O devices. ´ NT (nested task) flag indicates the current task is nested within another task in protected mode operation. ´ RF (resume) used with debugging to control resumption of execution after the next instruction. ´ VM (virtual mode) flag bit selects virtual mode operation in a protected mode system. ´ AC (alignment check) flag bit activates if a word or doubleword is addressed on a non-word or non-doubleword boundary. ´ VIF is a copy of the interrupt flag bit available to the Pentium 4– (virtual interrupt) ´ VIP (virtual) provides information about a virtual mode interrupt for (interrupt pending) Pentium. ´ used in multitasking environments to provide virtual interrupt flags ´ ID (identification) flag indicates that the Pentium microprocessors support the CPUID instruction. ´ CPUID instruction provides the system with information about the Pentium microprocessor Example 23 ´ Update the flags, when E952 is subtracted from B765? 1011 1110 B765 E952 --------C E 1 3 1100 1110 0001 0011 TF DF IF OF SF ZF AF PF CF x x x 1 Dr. Qurban Ali, EE Department 1 0 0 0 1