Interfacing the CPU with Memory and IO System Bus

System Bus Components

• The three components of the system bus are: data bus, address bus, and control bus

8088 CPU Architecture

• The 8088 CPU has 20 address lines
• The data bus of the 8088 CPU is 8 bits wide
• The address bus of the 8088 CPU has 20 bits

Bus Interface Unit (BIU)

• The BIU retrieves instructions from memory, decodes them, and generates control signals
• An essential responsibility of the BIU is to manage data transfer between the CPU and memory

Fetch and Execute Units

• The fetch unit retrieves instructions from memory and decodes them
• The execute unit executes the instructions
• The fetch and execute units operate in parallel

Registers

• The RIP register holds the address of the next instruction to be executed
• The RSP register holds the address of the top of the stack
• The RFLAGS register contains flags that reflect the result of arithmetic and logical operations

Flags

• The Carry flag (CF) holds the carry after an addition or the borrow after a subtraction
• The Sign flag (S) holds the sign of the result (negative or positive)
• The Zero flag (Z) indicates whether the result of an arithmetic or logical operation is zero
• The Parity flag (P) indicates whether the result has even or odd parity
• The Auxiliary Carry flag (A) holds the carry from the lower nibble to the upper nibble
• The Direction flag (D) controls the direction of string operations
• The Interrupt flag (I) enables or disables interrupts
• The Trap flag (TF) enables single-step mode for debugging
• The Nested Task flag (NT) indicates whether the current task is nested
• The I/O Privilege Level (IOPL) flag determines the I/O privilege level
• The Virtual Mode flag (VM) enables virtual mode operation
• The Resume flag (RF) resumes execution after an exception