UNIT 2.pdf

UNIT 2 The Central Processing Unit  What is Microprocessor A microprocessor, sometimes called a logic chip, is a computer processor on a microchip. It is also called as “Heart of Computer.” The microprocessor contains all, or most of, the central processing unit (CPU)...

UNIT 2 The Central Processing Unit  What is Microprocessor A microprocessor, sometimes called a logic chip, is a computer processor on a microchip. It is also called as “Heart of Computer.” The microprocessor contains all, or most of, the central processing unit (CPU) functions. A microprocessor is designed to perform arithmetic and logic operations that make use of small number-holding areas called Registers. Prof. R. V. Bidwe, SIT, Pune. 2  Typical microprocessor operations include adding, subtracting, comparing two numbers, and fetching numbers from one area to another. These operations are the result of a set of instructions that are part of the microprocessor design. Prof. R. V. Bidwe, SIT, Pune. 3  About 8086 It is 16 bit processor. So that it has 16 bit ALU, 16 bit registers and internal data bus and 16 bit external data bus. 8086 has 20 bit address lines to access memory. Hence it can access. 2^20 = 1 MB memory location Prof. R. V. Bidwe, SIT, Pune. 4  Pipelining:-8086 uses two stage of pipelining. First is Fetch Stage and the second is Execute Stage. – Fetch stage that prefetch upto 6 bytes of instructions stores them in the queue. – Execute stage that executes these instructions. Pipelining improves the performance of the processor so that operation is faster. Segmentation divides memory into 4 parts. Prof. R. V. Bidwe, SIT, Pune. 5  Operates in two modes:-8086 operates in two modes: – Minimum Mode: A system with only one microprocessor. – Maximum Mode: A system with multiprocessor. 8086 uses memory banks:-The 8086 uses a memory banking system. It means entire data is not stored sequentially in a single memory of 1 MB but memory is divided into two banks of 512KB. Interrupts:-8086 has 256 vectored interrupts. Prof. R. V. Bidwe, SIT, Pune. 6  Multiplication And Division:-8086 has a powerful instruction set. So that it supports Multiply and Divide operation. Prof. R. V. Bidwe, SIT, Pune. 7 Architecture of 8086 Prof. R. V. Bidwe, SIT, Pune. 8  Architecture of 8086 The architecture of 8086 includes – Arithmetic Logic Unit (ALU) – Flag Register – General Registers – Instruction Stream Byte Queue – Segment Registers Prof. R. V. Bidwe, SIT, Pune. 9  EU & BIU The 8086 CPU logic has been partitioned into two functional units namely Bus Interface Unit (BIU) and Execution Unit (EU). The major reason for this separation is to increase the processing speed of the processor. The BIU has to interact with memory and input and output devices in fetching the instructions and data required by the EU. EU is responsible for executing the instructions of the programs and to carry out the required processing. Prof. R. V. Bidwe, SIT, Pune. 10 BUS INTERFACE UNIT (BU) The BIU performs all bus operations for EU. – Fetching instructions – Responsible for executing all external bus cycles. – Read operands and write result. EXECUTION UNIT (EU) Execution unit contains the complete infrastructure required to execute an instruction. Prof. R. V. Bidwe, SIT, Pune. 11  Bus Interface Unit The BIU has – Instruction Byte Queue – Segment Registers – Instruction Pointer Prof. R. V. Bidwe, SIT, Pune. 12  BIU – Instruction Byte Queue 8086 instructions vary from 1 to 6 bytes. Therefore fetch and execution are taking place concurrently in order to improve the performance of the microprocessor. The BIU feeds the instruction stream to the execution unit through a 6 byte prefetch queue. Prof. R. V. Bidwe, SIT, Pune. 13  BIU – Instruction Byte Queue Execution and decoding of certain instructions do not require the use of buses. While such instructions are executed, the BIU fetches up to six instruction bytes for the following instructions (subsequent instructions). The BIU store these prefetched bytes in a first-in- first out register by name instruction byte queue. When the EU is ready for its next instruction, it simply reads the instruction byte(s) for the instruction from the queue in BIU. Prof. R. V. Bidwe, SIT, Pune. 14  Segment Registers Prof. R. V. Bidwe, SIT, Pune. 15  Different Areas in Memory Program memory – The executable programs from the memory. Data memory – The processor can access the secondary data in any one out of four available segments. Stack memory – A stack is a section of the memory set aside to store addresses and data while a subprogram executes. Extra segment – This segment is also similar to data memory where additional secondary data may be stored and maintained. Prof. R. V. Bidwe, SIT, Pune. 16  Segment Registers Code Segment (CS) register is a 16-bit register containing address of 64 KB segment with Processor Instructions. The processor uses CS segment for all accesses to instructions referenced by Instruction Pointer (IP) register. Stack Segment (SS) register is a 16-bit register containing address of 64KB segment with Program Stack. By default, the processor assumes that all data referenced by the Stack Pointer (SP) and Base Pointer (BP) registers is located in the stack segment. Prof. R. V. Bidwe, SIT, Pune. 17  Data Segment (DS) register is a 16-bit register containing address of 64KB segment with Program Data. By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and Index Register (SI, DI) is located in the data segment. Extra Segment (ES) register is a 16-bit register containing address of 64KB segment, usually with Program Data. By default, the processor assumes that the DI register references the ES segment in string manipulation instructions. Prof. R. V. Bidwe, SIT, Pune. 18  Execution Unit The Execution Unit (EU) has – Control Unit – Arithmetic And Logical Unit (ALU) – General Registers – Flag Register – Pointers – Index Registers Prof. R. V. Bidwe, SIT, Pune. 19  Execution Unit Control unit is responsible for the co- ordination of all other units of the processor. ALU performs various arithmetic and logical operations over the data. The Control Unit translates the instructions fetched from the memory into a series of actions that are carried out by the EU. Prof. R. V. Bidwe, SIT, Pune. 20  Programmer’s Model of 8086 General Purpose Register Prof. R. V. Bidwe, SIT, Pune. 21 Prof. R. V. Bidwe, SIT, Pune. 22  Flag Register Prof. R. V. Bidwe, SIT, Pune. 23 Pin Diagram 8086 Prof. R. V. Bidwe, SIT, Pune. 24 Prof. R. V. Bidwe, SIT, Pune. 25 8086 can be work in two modes Minimum Mode: For single processor systems. Maximum Mode: For system with two or more processors. Depending upon modes signals can be divided into Signals having common functions in both modes Signals for Minimum Mode Signals for Maximum Mode Prof. R. V. Bidwe, SIT, Pune. 26  Signals having common functions in both modes AD15 – AD0: Address /Data Bus (BI) T1 state: Address Bus T2,T3,Tw and T4: Data Bus A19/S6 - A16/S3: Address/Status (OP) T1 state : used to address upper 4 bits of address. T2, T3, Tw and T4 : Used to output status. S3 and S4 indicates segment registers being used S5: Status of Interrupt enable flag updated every clock cycle. S6: When 8086 Shared system bus, then goes low or goes high. Prof. R. V. Bidwe, SIT, Pune. 27  BHE(#)/S7: BHE (Bus High Enable) (OP) Low: If transfer is using higher order bytes (AD15-AD8) High: If transfer is using lower order bytes (AD7-AD0) S7 is used with HOLD Pin. BHE A0 Characteristics 0 0 Whole word 0 1 Upper byte from/to odd address 1 0 Lower byte from/to even address 1 1 None Prof. R. V. Bidwe, SIT, Pune. 28  NMI (NON-MASKABLE INTERRUPT) (IP) Interrupts can not be avoided. RESET: (IP) Causes the processor to immediately terminate its present activity. CLK: (IP) Provides the basic timing for the processor and bus controller. Power supply given to the system is converted to CLK signals by the Clock Generator. READY: (IP) It is the acknowledgement from the addressed memory or I/O device that it is ready for the data transfer. Otherwise 8086 will move to wait state. Prof. R. V. Bidwe, SIT, Pune. 29  TEST (#): (IP) This signal is used by WAIT instruction. Execution will continue, until TEST is low else it will be in idle state. TEST is synchronized internally during each clock cycle. RD (#): (OP) This signal remains low when 8086 is reading data from memory or I/O devices. MN/MX (#): (IP) Indicates what mode the processor is to operate in. GND: Ground (OP) To prevent 8086 from thermal heating ,two ground signals are used. VCC: (IP) +5V power supply pin. Prof. R. V. Bidwe, SIT, Pune. 30  Signals functions in Maximum modes QS1,QS0 : (OP) Reflects status of Instruction Queue. QS1 QS0 Status 0 0 No Operation 0 1 First Byte of Op Code from Queue 1 0 Queue is empty 1 1 Subsequent Byte from Queue S2,S1,S0 (#): (OP) Indicates type of transfer takes place during current bus cycle. S2 S1 S0 Machine Cycle S2 S1 S0 Machine Cycle 0 0 0 Interrupt ACK 1 0 0 Instruction Fetch 0 0 1 I/O Read 1 0 1 Memory Read 0 1 0 I/O Write 1 1 0 Memory Write 0 1 1 Halt 1 Pune. 1 1 Inactive-Passive (In T3) Prof. R. V. Bidwe, SIT, 31  LOCK: (OP) Bus is not used by another processor, current system have locked the rights. Used for notifying to another processors. RQ(#)/GT1(#)&RQ(#)/GT0(#): (Bus request/Bus Grant) (BI) Using bus request signal another master can request a system bus and processor sends a grant signal as a acceptance. RQ/GT0 is having greater priority than RQ/GT1. Prof. R. V. Bidwe, SIT, Pune. 32  Signals functions in Minimum modes INTA (Interrupt Ack): (OP) It indicates recognition of an interrupt request. It then sends two negative going pulse in next to clk cycles, first informs interface that its interrupt request in accepted, in next pulse interface replies with interrupt type. ALE (Address Latch Enable): (OP) It is provided to demultiplex AD0-AD15 to A0-A15 and D0- D15. DEN (#) (Data Enable): (OP) This signal informs transceivers that 8086 is ready to send or receive data. Prof. R. V. Bidwe, SIT, Pune. 33  DT/R (#) (Data Transmit/Receive): (OP) It is used to control the direction of data flow through the transceiver. High: 8086 is transmitting data Low: 8086 is receiving data M/IO (#) : (OP) It is used to distinguish a memory access from an I/O access. High: Memory Access Low: I/O Access WR (#) (WRITE): (OP) Indicates that the processor is performing a writing data to memory or I/O. Prof. R. V. Bidwe, SIT, Pune. 34  HOLD (IP) / HLDA (OP) : HOLD: indicates that DMA master is requesting a local bus, on request processor replies High HLDA signal as a Ack. Prof. R. V. Bidwe, SIT, Pune. 35  Minimum-Mode and Maximum- Mode System (cont.) Signals common to both minimumProf. andR. maximum mode V. Bidwe, SIT, Pune. 36 Minimum-Mode and Maximum- Mode System (cont.) Unique minimum-mode signals Prof. R. V. Bidwe, SIT, Pune. 37 Minimum-Mode and Maximum- Mode System (cont.) Unique maximum-mode signals Prof. R. V. Bidwe, SIT, Pune. 38  Segmentation in 8086 The process of dividing memory is called Segmentation. Intel 8086 has 20 lines address bus. With 20 address lines, the memory that can be addressed is 2^20 bytes 2^20 = 1,048,576 bytes (1 MB). 8086 can access memory with address ranging from 00000 H to FFFFF H. Prof. R. V. Bidwe, SIT, Pune. 39 Prof. R. V. Bidwe, SIT, Pune. 40  In 8086, memory has four different types of segments. These are: – Code Segment – Data Segment – Stack Segment – Extra Segment These registers are 16-bit in size. Each register stores the base address (starting address) of the corresponding segment. Because the segment registers cannot store 20 bits, they only store the upper 16 bits. Prof. R. V. Bidwe, SIT, Pune. 41  Logical to physical address Translation in 8086 The 20-bit address of a byte is called its Physical Address. High level languages have a Logical Address. Logical address is in the form of: Base Address : Offset Offset is the displacement of the memory location from the starting location of the segment. Prof. R. V. Bidwe, SIT, Pune. 42  Example The value of Data Segment Register (DS) is 2222 H. To convert this 16-bit address into 20-bit, the BIU appends 0H to the LSBs of the address. After appending, the starting address of the Data Segment becomes 22220H. If the data at any location has a logical address specified as: 2222 H : 0016 H Then, the number 0016 H is the offset. 2222 H is the value of DS. Prof. R. V. Bidwe, SIT, Pune. 43  To calculate the effective address of the memory, BIU uses the following formula: Effective Address = Starting Address of Segment + Offset To find the starting address of the segment, BIU appends the contents of Segment Register with 0H. Then, it adds offset to it. Therefore: EA = 22220 H + 0016 H ------------ 22236 H Prof. R. V. Bidwe, SIT, Pune. 44 Prof. R. V. Bidwe, SIT, Pune. 45  Question 1 The contents of the following registers are: CS = 1111 H DS = 3333 H SS = 2526 H IP = 1232 H SP = 1100 H DI = 0020 H Calculate the corresponding physical addresses for the address bytes in CS, DS and SS. Prof. R. V. Bidwe, SIT, Pune. 46 1. CS = 1111 H The base address of the code segment is 11110 H. Effective address of memory is given by 11110H + 1232H = 12342H. 2. DS = 3333 H The base address of the data segment is 33330 H. Effective address of memory is given by 33330H + 0020H = 33350H. 3. SS = 2526 H The base address of the stack segment is 25260 H. Effective address of memory is given by 25260H + 1100H = 26360H. Prof. R. V. Bidwe, SIT, Pune. 47  Question 2 The contents of the following registers are: CS = 1234 H ES = 0014 H SS = 9526 H IP = 0042 H SP = 1800 H DI = 2020 H Calculate the corresponding physical addresses for the address bytes in CS, ES and SS. Prof. R. V. Bidwe, SIT, Pune. 48 1. CS = 1234 H The base address of the code segment is 12340 H. Effective address of memory is given by 12340H + 0042H = 12382H. 2. ES = 0014 H The base address of the data segment is 00140 H. Effective address of memory is given by 00140H + 2020H = 02160H. 3. SS = 9526 H The base address of the stack segment is 95260 H. Effective address of memory is given by 95260H + 1800H = 96A60H. Prof. R. V. Bidwe, SIT, Pune. 49 Assemblers, Linkers & Loaders Prof. R. V. Bidwe, SIT, Pune. 50 Prof. R. V. Bidwe, SIT, Pune. 51 Prof. R. V. Bidwe, SIT, Pune. 52 Prof. R. V. Bidwe, SIT, Pune. 53 Prof. R. V. Bidwe, SIT, Pune. 54 Prof. R. V. Bidwe, SIT, Pune. 55 Prof. R. V. Bidwe, SIT, Pune. 56 Prof. R. V. Bidwe, SIT, Pune. 57 Procedures Prof. R. V. Bidwe, SIT, Pune. 58 Why Procedures? Prof. R. V. Bidwe, SIT, Pune. 59 Nested Procedures Prof. R. V. Bidwe, SIT, Pune. 60 Macros Prof. R. V. Bidwe, SIT, Pune. 61 Macros as Inline codes Prof. R. V. Bidwe, SIT, Pune. 62 Difference between Macro and Procedure Prof. R. V. Bidwe, SIT, Pune. 63  How to define macro section.data Section.text Global main msg: db “hello”,10 Main: len: equ $-msg - print msg,len Section.bss - - count: resb 2 print msg,len - %macro print 2 - Mov rax,1 - Mov rdi,1 ; code of addition and result stored in COUNT variable Mov rsi, %1 print count,2 Mov rdx, %2 - Syscall - %endmacro Mov rax,60 Mov rdi,0 syscall Prof. R. V. Bidwe, SIT, Pune. 64  Stack Prof. R. V. Bidwe, SIT, Pune. 65  Directives There are some instructions in the assembly language program which are not a part of Processor Instruction Set. These instructions are instructions to the Assembler, Linker and Loader. These are referred to as pseudo-operations or as assembler directives. Prof. R. V. Bidwe, SIT, Pune. 66  DB – Define Byte DD – Define Doubleword DQ – Define Quadword DT – Define Ten Bytes DW – Define Word ENDS This directive is used with name of the segment to indicate the end of that logic segment. CODE SEGMENT ; this statement starts the segment CODE ENDS ; this statement ends the segment EQU Prof. R. V. Bidwe, SIT, Pune. 67 Prof. R. V. Bidwe, SIT, Pune. 68 Prof. R. V. Bidwe, SIT, Pune. 69 Prof. R. V. Bidwe, SIT, Pune. 70  Flag Manipulation instructions The Flag manipulation instructions directly modify some of the Flags of 8086. i. CLC – Clear Carry Flag. ii. CMC – Complement Carry Flag. iii. STC – Set Carry Flag. iv. CLD – Clear Direction Flag. v. STD – Set Direction Flag. vi. CLI – Clear Interrupt Flag. vii. STI – Set Interrupt Flag. Machine Control instructions The Machine control instructions control the bus usage and execution i. WAIT – Wait for Test input pin to go low. ii. HLT – Halt the process. iii. NOP – No operation. iv. ESC – Escape to external device like NDP v. LOCK – Bus lock instruction prefix. Prof. R. V. Bidwe, SIT, Pune. 71 Shift Instruction Prof. R. V. Bidwe, SIT, Pune. 72 How it works? Prof. R. V. Bidwe, SIT, Pune. 73 Rotate Instructions Prof. R. V. Bidwe, SIT, Pune. 74 String Instructions Prof. R. V. Bidwe, SIT, Pune. 75 Prof. R. V. Bidwe, SIT, Pune. 76 If sting instructions are not used.. Prof. R. V. Bidwe, SIT, Pune. 77 Prof. R. V. Bidwe, SIT, Pune. 78  REP Instruction These instructions are used along with string instructions only. Prof. R. V. Bidwe, SIT, Pune. 79  Addressing Modes What is Addressing Mode? – The way operand is specified within an instruction, i.e., either as an immediate operand or indirect operand or direct operand. – The way to access Variables, Arrays, Records, Pointer and other complex data types. Prof. R. V. Bidwe, SIT, Pune. 80  Types of addressing modes o Register Addressing Modes o Immediate Operand Addressing o Memory Operand Addressing Each operand can use a different addressing Mode. Prof. R. V. Bidwe, SIT, Pune. 81  Register Addressing Mode The effect of executing the {MOV BX,CX} instruction at the point just before the BX register changes. Note that only the rightmost 16 bits of register EBX change. Prof. R. V. Bidwe, SIT, Pune. 82  Immediate Addressing Mode The operation of the {MOV EAX,13456H} instruction. This instruction copies the immediate data (13456H) into EAX. Prof. R. V. Bidwe, SIT, Pune. 83  Memory Addressing Modes The 8086 processor generalized the memory addressing modes. In 8086 you are allowed to use BX or BP as Base Registers apart from Segment Registers and SI or DI as Index Registers. Prof. R. V. Bidwe, SIT, Pune. 84  1. Direct Data Addressing The operation of the {MOV AL, byte[1234H]} instruction when DS=1000H. Prof. R. V. Bidwe, SIT, Pune. 85 Prof. R. V. Bidwe, SIT, Pune. 86  2. Register Indirect Addressing 8086 Allows data to be addressed at any memory location through an offset address held in any of the following registers: BP, BX, DI, and SI. Base Address is given by Segment Registers. Prof. R. V. Bidwe, SIT, Pune. 87  The operation of the {MOV AX, word[BX]} instruction when BX = 1000H and DS = 0100H. Note that this instruction is shown after the contents of memory are transferred to AX. Prof. R. V. Bidwe, SIT, Pune. 88 Prof. R. V. Bidwe, SIT, Pune. 89  3. Base+ Index Addressing An example showing how the base-plus-index addressing mode functions for the {MOV DX, word[BX + DI]} instruction. Note: DS=0100H, BX=1000H and DI=0010H. Prof. R. V. Bidwe, SIT, Pune. 90 Prof. R. V. Bidwe, SIT, Pune. 91 4. Base+ Index+ Displacement Addressing Similar to base-plus-index addressing and displacement addressing. – Data in a segment of memory are addressed by adding the displacement to the contents of a base or an index register (BP, BX, DI, or SI) Figure shows the operation of the {MOV AX, word[BX+1000H]} instruction. when BX=0100H and DS=0200H Prof. R. V. Bidwe, SIT, Pune. 92  The operation of the {MOV AX, word[BX+1000H]} instruction. Prof. R. V. Bidwe, SIT, Pune. 93  Implied/ Implicit Addressing Mode Instructions with no oprand belongs to this addressing mode. Prof. R. V. Bidwe, SIT, Pune. 94