unit 1_Notes.pdf

Microprocessor And Assembly Language Unit-1  Unit 1 Introduction to 8086 Microprocessor Introduction Brief History Of Intel Microprocessors Overview of Microprocessor and Microcomputer Features of 8086 Microprocessor The 8086 Architecture Segmentation...

Microprocessor And Assembly Language Unit-1  Unit 1 Introduction to 8086 Microprocessor Introduction Brief History Of Intel Microprocessors Overview of Microprocessor and Microcomputer Features of 8086 Microprocessor The 8086 Architecture Segmentation in 8086 Microprocessor The 8086 Pin Functions The 8086 Memory System  Introduction A microprocessor is a computer processor that incorporates the functions of a central processing unit on a single integrated circuit (IC),or at most a few integrated circuits. The microprocessor is a multipurpose, clock driven, register based, digital integrated circuit that accepts binary data as input, processes it according to instructions stored in its memory, and provides results as output. Microprocessors contain both combinational logic and sequential digital logic. Microprocessors operate on numbers and symbols represented in the binary number system. A microprocessor executes a collection of machine instructions that tell the processor what to do  Introduction Microprocessor is multipurpose, programmable logic device that reads the binary instruction from storage device like memory, accepts the binary data as input and processes data according to those instructions, and provides the results as output. Microprocessors have been developed by various companies like Intel, AMD, Motorola, IBM, Sun etc. Initially Microprocessors were of 8 bit then we had 16 bit, 32 bit, and the latest is 64 bit microprocessors.  Introduction Example of 8 bit microprocessors: Intel 8085, Motorola 6809, Zilog Z80 etc. Example of 16 bit microprocessors: Intel 8086, Intel 80286, Motorola 68000, Zilog 8000 etc. Example of 32 bit microprocessors: Intel 486, Pentium, Pentiuam pro, Celeron, Pentium II, Pentiam III etc. Example of 64 bit microprocessors: Intel Pentium 4EE, Itanium, SUN Ultrasparc, DEC Alpha 21264 etc.  Introduction Classification of Microprocessors: 1. Semiconductor technology: TTL( transistor transistor logic), CMOS( Complementary metal oxide semiconductor), ECL (emitter coupled logic) 2. Word length 3. Instruction set: RISC and CISC 4. Bandwidth: the number of bits processed by processor in a single instruction. 5. Clock speed: it determines how many instructions a processor can process. Overview of Microprocessor and Microcomputer Microprocessor: Microprocessor is a simple central processing unit (CPU) on a single chip (remember the word ‘Single Chip’). It includes Arithmetic logic unit (ALU), control unit (CU), registers, instruction decoders, bus control circuit etc. but everything should be on a single chip. Microcomputer: it is a digital system consisting of microprocessor, memory and I/O devices connected using system bus. The system bus includes data, address and control buses. Overview of Microprocessor and Microcomputer  Features of 8086 Microprocessor 8086 Microprocessor is an enhanced version of 8085Microprocessor that was designed by Intel in 1976. It is a 16-bit Microprocessor having 20 address lines and16 data lines that provides up to 1MB storage. It consists of powerful instruction set, which provides operations like multiplication and division easily. It supports two modes of operation, i.e. Maximum mode and Minimum mode. Maximum mode is suitable for system having multiple processors and Minimum mode is suitable for system having a single processor.  Features of 8086 Microprocessor 40 pin DIP( Dual Inline Package). 16 bit ALU. 16 bit data bus. 20 bit address bus, total addressable memory 1 MB. Two internal hardware units: BIU ( Bus interface unit) EU (Execution Unit)  Features of 8086 Microprocessor 6 byte pre fetch queue. Four 16 bit general purpose registers (AX, BX, CX, DX) also accessible as eight 8 bit registers (AH, AL, BH, BL, CH, CL, DH and DL). Two 16 bit index registers ( SI and DI) Two 16 bit stack pointers (SP and BP) Four 16 bit segment registers ( CS, DS, ES, SS) 16 bit instruction Pointer register (IP)  Features of 8086 Microprocessor 16 bit flag registers : six conditional flags ( OF, SF, ZF, PF, AF, CF) and three control flags (DF, IF and TF). Two hardware modes: Maximum and Minimum mode Memory divided into odd and even banks and accessible simultaneously to read 16 bit word in one cycle.  Features of 8086 Microprocessor Instruction set supporting:  Variety of flexible addressing modes  Multiplication and division instructions.  Special set of string instructions.  Special iteration control instructions.  Signed and unsigned processing.  Binaly, BCD and ASCII processing.  The 8086 Architecture 8086 has two blocks BIU and EU. The BIU performs all bus operations such as instruction fetching, reading and writing operands from memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue. EU executes instructions from the instruction queue. Both units operate independently to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance.  The 8086 Architecture BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder. EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register. The 8086 Architecture  BUS INTERFACE UNIT (BIU) It provides a full 16 bit bidirectional data bus and 20 bit address bus. The bus interface unit is responsible for performing all external bus operations. Specifically it has the following functions: Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus control. The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture. Functional Components of BIU: Prefetch Queue, Segment Registers and Instruction Pointer  Prefetch Queue (instruction Queue) Prefetch Queue (instruction Queue): To increase the execution speed, BIU fetches as many as six instruction bytes ahead to time from memory. The pre fetched instruction bytes are held for the EU in a first in first out group of registers called a instruction queue. When the EU is ready for its next instruction, it simply reads the instruction from this instruction queue. This is much faster than sending out an address to the system memory and to send back the next instruction byte. Fetching the next instruction while the current instruction executes is called pipelining.  Segment Registers Segment Registers: BIU contains four 16-bit segment registers. – extra segment (ES) register – code segment (CS) register – data segment (DS) register – stack segment (SS) registers. These segment registers are used to hold the upper 16 bits of the starting address for each of the segments. These registers are used to access 1MB of memory. The part of a segment starting address stored in a segment register is often called the base address or segment base.  Segment Registers Code Segment (CS): The CS register is used for addressing a memory location in the Code Segment of the memory, where the executable program is stored. It contains the base address of code segment. Data Segment (DS): The DS contains most data used by program. Data are accessed in the Data Segment by an offset address or the content of other register that holds the offset address. DS register contains the base address of Data Segment.  Segment Registers Stack Segment (SS): SS defined a section of memory to store addresses and data while a subprogram executes. SS Register holds the starting address of Stack Segment Extra Segment (ES): ES is additional data segment that is used to hold the extra destination data. ES register holds the starting address of ES. 8086 allows only one segment to be active at a time.  Instruction Pointer BIU contains 16 bit register – Instruction Pointer (IP). the instruction pointer is register that holds the address of the next instruction to be fetched from memory. It contains the offset of the next word instruction code instead of its actual address.  EXECUTION UNIT (EU) Execution unit gives instructions to BIU stating from where to fetch the data and then decode and execute those instructions. Its function is to control operations on data using the instruction decoder & ALU. EU has no direct connection with system buses, it performs operations over data through BIU. It contains 16 bit ALU, general purpose registers, pointer registers, index registers, flag registers and temporary operand registers. It gets instruction from Prefetch queue, decodes it and requests the BIU for data read or write operation if necessary and performs the steps to complete the execution of the instruction.  General Purpose Registers EU has eight general purpose registers labeled AH, AL, BH, BL, CH, CL, DH, and DL. These registers can be used individually for temporary storage of 8-bit data. The AL register is also called the accumulator. AX Register: For 16-bit operations, AX is called the accumulator register that stores operands for arithmetic operations. The lower 8 bits of AX are designated to use as AL and higher 8 bits as AH. AL can be used as an 8 bit accumulator for 8 bit operation. this accumulator used in arithmetic, logic and data transfer operations.  General Purpose Registers BX Register: This register is mainly used as a base register. It holds the starting base location of a memory region within a data segment. CX Register: It is defined as a counter. It is primarily used in loop instruction to store loop counter. Counter register can also be used as a counter in string manipulation and shift/rotate instruction. DX Register: DX register is used to contain I/O port address for I/O instruction. It can also be used as an implicit operand to store data.  Pointer Registers Stack Pointer: The stack pointer (SP) register contains the 16-bit offset from the start of the segment to the memory location where a word was most recently stored on the stack. The memory location where a word was most recently stored is called the top of stack. Base Pointer: the Base Pointer (BP) is a 16 bit register pointing to data in stack segment. It can also be used to access other memory segments.  Index Registers The Source Index (SI) and Destination Index (DI) are two 16 bit index registers used to keep track of index of the elements in array and strings. Source Index (SI): SI is a 16 bit register. Used to store the offset of source data in data segment. SI used for indexed, based indexed and register indirect addressing as well as a source data address in string manipulation instructions.  Index Registers Destination Index (DI): DI is a 16 bit register it is used to access memory locations in data or extra segment DI used for indexed, based indexed and register indirect addressing as well as a Destination data address in string manipulation instructions.. Flag Registers  Conditional Flag It represents the result of the last arithmetic or logical instruction executed. Following is the list of conditional flags Parity flag − This flag is used to indicate the parity of the result, i.e. when the lower order 8-bits of the result contains even number of 1’ s, then the Parity Flag is set. For odd number of 1 ’ s, the Parity Flag is reset. 1 for even parity 0 for odd parity  Conditional Flag Carry flag − this flag is set when there is a carry out of MSB in case of addition or borrow in case of subtraction. 0 for NO carry/Borrow 1 for Carry /Borrow Auxiliary flag − When an operation is performed at ALU, it results in a carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), then this flag is set, i.e. carry given by D3 bit to D4 is AF flag. The processor uses this flag to perform binary to BCD conversion.  Conditional Flag Zero flag − This flag is set to 1 when the result of arithmetic or logical operation is zero else it is set to 0. Sign flag − This flag holds the sign of the result, i.e. when the result of the operation is negative, then the sign flag is set to 1 else set to 0. Overflow flag − This flag represents the result when the system capacity is exceeded. This flag is set when an overflow occurs i.e. if the result of a signed operation is large enough to accommodate in a destination register.  Control Flags Control flags are intentionally set or reset to control certain operations of the processor with specific instructions put in the program from the user. Control flags are as follows: Trap Flag (TF): It is used for single step control. It allows user to execute one instruction of a program at a time for debugging. When trap flag is set, program can be run in single step mode. When in single step mode it executes an instruction then jumps to a special service routine that may determine the effect of executing the instruction. This type of operation is very useful for debugging programs.  Control Flags Interrupt Flag (IF): It is an interrupt enable/disable flag, i.e. used to allow/prohibit the interruption of a program. If it is set, the maskable interrupt is enabled and if it is reset, the interrupt is disabled. Direction Flag (DF): It is used in string operation. If it is set (1), string bytes are accessed from higher memory address to lower memory address. i.e. auto decrement mode When it is reset (0), the string bytes are accessed from lower memory address to higher memory address. i.e. auto increment mode  8086 Pin Functions The 8086 is Intel's first 16 bit microprocessor manufactured as 40 pin DIP (Dual Inline package). 8086 operates in two modes: minimum mode and maximum mode. The pin MN/MX’ is used to decide the operating mode. If MN/MX’ pin is tied to the Vcc (Logic 1) then the processor operates in the minimum mode. If MN/MX’ pin is tied to the ground (Logic 0) then the processor operates in the maximum mode. The functions of pin numbers 24 to 31 are different in minimum and maximum mode. the minimum mode pin functions for pin numbers 24 to 31 are listed in fig in brackets. 8086 Pin Functions  8086 Pin Functions The 8086 uses 20-line address bus. It has a 16-line data bus. The 20 lines of the address bus operate in multiplexed mode. 0The 16-low order address bus (A0-A15) lines have been multiplexed with data( D0 –D15) known as (AD0- AD15) 4 high-order address bus lines (A16- A19) have been multiplexed with status signals (S3 – S6) known as ( A16/S3 – A19/S6) The output signal ALE (address latch Enable) is used to demultiplex the multiplexed address/data and multiplexed address/status bus.  8086 Pin Functions ALE: When ALE is high (1) : the multiplex bus contains the address bits. When ALE is low (0) : the multiplex bus contains data and status bits. AD0-AD15 : Address/Data bus. These are low order address bus. They are multiplexed with data. When AD lines are used to transmit memory address the symbol A is used instead of AD, for example A0-A15. When data are transmitted over AD lines the symbol D is used in place of AD, for example D0-D7, D8-D15 or D0-D15.  8086 Pin Functions S3 – S6: output signals used to show the internal status of the 8086 The status line S3 S4 together give which segment register is used to generate the physical address during current cycle. S4 S3 Segment Register Used 0 0 ES 0 1 SS 1 0 CS 1 1 Ds S6: it is always 0 S5: show the status of the interrupt flag  8086 Pin Functions INTR: Interrupt Request Maskable interrupt. It can be disabled. NMI: Non Maskable interrupt. Non Maskable interrupt. It can not be disabled. INTA’ : interrupt Acknowledge It is an output signal used to acknowledge the acceptance of interrupt on INTR or NMI pin sent by the external device.  8086 Pin Functions MN/MX’: Minimum/Maximum This pin signal indicates what mode the processor will operate in. TEST’: input signal Used to synchronize the 8089 with external hardware when the 8086 executes the WAIT instruction. RESET : RESET causes the system reset for the 8086 microprocessor. READY: Used to synchronize the slower devices with the microprocessor. 0 -- wait state , 1 -- device ready to transfer  8086 Pin Functions Vcc: Power Supply( +5V D.C.) CLK: Clock Input The clock input provides the basic timing for processing operation and bus control activity. BHE’/S7: Bus High Enable/ status signal S7 BHE’ is used to enable the odd memory bank in the 8086 memory banks. BHE’ is multiplexed with status signal S7  8086 Pin Functions HOLD and HOLDA: (minimum mode) Used to interface 8086 with the DMA (direct Memory Access) Controller. HOLD is an input signal used by external DMA controller chip to send the request to the 8086 microprocessor to grant the control of the system bus. HOLDA is an output signal used by 8086 microprocessor to inform DMA controller to grant the request. M/IO’: Memory / IO operation 1– indicates memory operation 0– indicates IO operation  8086 Pin Functions DT/R’: Data transmit / Receive 1– indicates data is transmitted from the microprocessor 0– indicates data is received by microprocessor DEN’: Data Enable Enable external device to provide the data. RQ’/GT1′ and RQ’/GT0′ : Request and Grant DMA operation LOCK’: Lock the peripherals  8086 Pin Functions QS1, QS0: Queue Status These signals indicate the status of the internal 8086 instruction queue QS1 QS0 STATUS 0 0 No operation 0 1 First byte of op code from queue 1 0 Empty the queue 1 1 Subsequent byte from queue Prepared By: Ankita Pimputkar  8086 Pin Functions S0’ , S1’, S2’: Status pins These signals indicate the status of the internal 8086 instruction queue S2 S1 S0 CHARACTERISTICS 0 0 0 Interrupt acknowledge 0 0 1 Read I/O port 0 1 0 Write I/O port 0 1 1 Halt 1 0 0 Code access 1 0 1 Read memory 1 1 0 Write memory 1 1 1 Passive state  Segmentation in 8086 Microprocessor Addressing in 8086 segmentation: The 20-bit address of a byte is called its Physical Address. But, it is specified as a Logical Address. Logical address is in the form of: Base Address : Offset Offset is the displacement of the memory location from the starting location of the segment. Effective Address (EA) = Starting Address of Segment + Offset  Segmentation in 8086 Microprocessor Addressing in 8086 segmentation: Prepared By: Ankita Pimputkar  Segmentation in 8086 Microprocessor Addressing in 8086 segmentation: Example: If the data at any location has a logical address specified as: 2222 H : 0016 H Then, the number 0016 H is the offset. 2222 H is the value of DS. EA = 22220 H + 0016 H ------------ 22236 H Prepared By: Ankita Pimputkar  8086 Memory System 8086 can address total 1 MB memory using 20 bits address bus. The 8086 memory is organized in to two banks in order to utilize 16 bit data bus to transfer 16 bit data at a time. (when a word starts from even address) The even bank contains the memory locations with even addresses. And the odd bank contains the memory locations with odd address. The low order data bus D0-D7 is connected to even bank and the higher order data bus D8 – D15 is connected to odd bank. The address line A0 is used to enable even bank. (0 = Enable , 1= Disable) BHE (Bus High Enable) is used to odd bank. (0 = Enable , 1= Disable) Prepared By: Ankita Pimputkar 8086 Memory System Prepared By: Ankita Pimputkar  8086 Memory System 8086 supports both the 8 bit (byte) and 16 bit (word) data transfer in both directions. There are four cases possible to read/write data to/from memory: Prepared By: Ankita Pimputkar