Chapter 4 The Processor PDF

COMPUTER ORGANIZATION AND DESIGN 6th Edition The Hardware/Software Interface Chapter 4 The Processor  §4.6 An Overview of Pipelining Pipelining Analogy ◼ Pipelined laundry: o...

COMPUTER ORGANIZATION AND DESIGN 6th Edition The Hardware/Software Interface Chapter 4 The Processor  §4.6 An Overview of Pipelining Pipelining Analogy ◼ Pipelined laundry: overlapping execution ◼ Parallelism improves performance ◼ Four loads: ◼ Speedup = 8/3.5 = 2.3 ◼ Non-stop: ◼ Speedup = 2n/0.5n + 1.5 ≈ 4 = number of stages Chapter 4 — The Processor — 2 MIPS Pipeline ◼ Five stages, one step per stage 1. IF: Instruction fetch from memory 2. ID: Instruction decode & register read 3. EX: Execute operation or calculate address 4. MEM: Access memory operand 5. WB: Write result back to register Chapter 4 — The Processor — 3  Pipeline Performance ◼ Assume time for stages is ◼ 100ps for register read or write ◼ 200ps for other stages ◼ Compare pipelined datapath with single-cycle datapath Instr Instr fetch Register ALU op Memory Register Total time read access write lw 200ps 100 ps 200ps 200ps 100 ps 800ps sw 200ps 100 ps 200ps 200ps 700ps R-format 200ps 100 ps 200ps 100 ps 600ps beq 200ps 100 ps 200ps 500ps Chapter 4 — The Processor — 4 Pipeline Performance Single-cycle (Tc= 800ps) Pipelined (Tc= 200ps) Chapter 4 — The Processor — 5 Pipeline Speedup ◼ If all stages are balanced ◼ i.e., all take the same time ◼ Time between instructionspipelined = Time between instructionsnonpipelined Number of stages ◼ If not balanced, speedup is less ◼ Speedup due to increased throughput ◼ Latency (time for each instruction) does not decrease Chapter 4 — The Processor — 6 Pipelining and ISA Design ◼ MIPS ISA designed for pipelining ◼ All instructions are 32-bits ◼ Easier to fetch and decode in one cycle ◼ c.f. x86: 1- to 17-byte instructions ◼ Few and regular instruction formats ◼ Can decode and read registers in one step ◼ Load/store addressing ◼ Can calculate address in 3rd stage, access memory in 4th stage ◼ Alignment of memory operands ◼ Memory access takes only one cycle Chapter 4 — The Processor — 7 Hazards ◼ Situations that prevent starting the next instruction in the next cycle ◼ Structure hazards ◼ A required resource is busy ◼ Data hazard ◼ Need to wait for previous instruction to complete its data read/write ◼ Control hazard ◼ Deciding on control action depends on previous instruction Chapter 4 — The Processor — 8 Structural Hazards ◼ Conflict for use of a resource ◼ In MIPS pipeline with a single memory ◼ Load/store requires data access ◼ Instruction fetch would have to stall for that cycle ◼ Would cause a pipeline “bubble” ◼ Hence, pipelined datapaths require separate instruction/data memories ◼ Or separate instruction/data caches Chapter 4 — The Processor — 9 Data Hazards ◼ An instruction depends on completion of data access by a previous instruction ◼ add $s0, $t0, $t1 sub $t2, $s0, $t3 Chapter 4 — The Processor — 10 Forwarding (aka Bypassing) ◼ Use result when it is computed ◼ Don’t wait for it to be stored in a register ◼ Requires extra connections in the datapath Chapter 4 — The Processor — 11 Load-Use Data Hazard ◼ Can’t always avoid stalls by forwarding ◼ If value not computed when needed ◼ Can’t forward backward in time! Chapter 4 — The Processor — 12 Code Scheduling to Avoid Stalls ◼ Reorder code to avoid use of load result in the next instruction ◼ C code for A = B + E; C = B + F; lw $t1, 0($t0) lw $t1, 0($t0) lw $t2, 4($t0) lw $t2, 4($t0) stall add $t3, $t1, $t2 lw $t4, 8($t0) sw $t3, 12($t0) add $t3, $t1, $t2 lw $t4, 8($t0) sw $t3, 12($t0) stall add $t5, $t1, $t4 add $t5, $t1, $t4 sw $t5, 16($t0) sw $t5, 16($t0) 13 cycles 11 cycles Chapter 4 — The Processor — 13 Control Hazards ◼ Branch determines flow of control ◼ Fetching next instruction depends on branch outcome ◼ Pipeline can’t always fetch correct instruction ◼ Still working on ID stage of branch ◼ In MIPS pipeline ◼ Need to compare registers and compute target early in the pipeline ◼ Add hardware to do it in ID stage Chapter 4 — The Processor — 14 Stall on Branch ◼ Wait until branch outcome determined before fetching next instruction Chapter 4 — The Processor — 15 Branch Prediction ◼ Longer pipelines can’t readily determine branch outcome early ◼ Stall penalty becomes unacceptable ◼ Predict outcome of branch ◼ Only stall if prediction is wrong ◼ In MIPS pipeline ◼ Can predict branches not taken ◼ Fetch instruction after branch, with no delay Chapter 4 — The Processor — 16 MIPS with Predict Not Taken Prediction correct Prediction incorrect Chapter 4 — The Processor — 17 More-Realistic Branch Prediction ◼ Static branch prediction ◼ Based on typical branch behavior ◼ Example: loop and if-statement branches ◼ Predict backward branches taken ◼ Predict forward branches not taken ◼ Dynamic branch prediction ◼ Hardware measures actual branch behavior ◼ e.g., record recent history of each branch ◼ Assume future behavior will continue the trend ◼ When wrong, stall while re-fetching, and update history Chapter 4 — The Processor — 18 Pipeline Summary The BIG Picture ◼ Pipelining improves performance by increasing instruction throughput ◼ Executes multiple instructions in parallel ◼ Each instruction has the same latency ◼ Subject to hazards ◼ Structure, data, control ◼ Instruction set design affects complexity of pipeline implementation Chapter 4 — The Processor — 19  §4.7 Pipelined Datapath and Control MIPS Pipelined Datapath MEM Right-to-left WB flow leads to hazards Chapter 4 — The Processor — 20 Pipeline registers ◼ Need registers between stages ◼ To hold information produced in previous cycle Chapter 4 — The Processor — 21 Pipeline Operation ◼ Cycle-by-cycle flow of instructions through the pipelined datapath ◼ “Single-clock-cycle” pipeline diagram ◼ Shows pipeline usage in a single cycle ◼ Highlight resources used ◼ c.f. “multi-clock-cycle” diagram ◼ Graph of operation over time ◼ We’ll look at “single-clock-cycle” diagrams for load & store Chapter 4 — The Processor — 22 IF for Load, Store, … Chapter 4 — The Processor — 23 ID for Load, Store, … Chapter 4 — The Processor — 24 EX for Load Chapter 4 — The Processor — 25 MEM for Load Chapter 4 — The Processor — 26 WB for Load Wrong register number Chapter 4 — The Processor — 27 Corrected Datapath for Load Chapter 4 — The Processor — 28 EX for Store Chapter 4 — The Processor — 29 MEM for Store Chapter 4 — The Processor — 30 WB for Store Chapter 4 — The Processor — 31 Multi-Cycle Pipeline Diagram ◼ Form showing resource usage Chapter 4 — The Processor — 32 Multi-Cycle Pipeline Diagram ◼ Traditional form Chapter 4 — The Processor — 33 Single-Cycle Pipeline Diagram ◼ State of pipeline in a given cycle Chapter 4 — The Processor — 34 Pipelined Control (Simplified) Chapter 4 — The Processor — 35 Pipelined Control ◼ Control signals derived from instruction ◼ As in single-cycle implementation Chapter 4 — The Processor — 36 Pipelined Control Chapter 4 — The Processor — 37  §4.8 Data Hazards: Forwarding vs. Stalling Data Hazards in ALU Instructions ◼ Consider this sequence: sub $2, $1,$3 and $12,$2,$5 or $13,$6,$2 add $14,$2,$2 sw $15,100($2) ◼ We can resolve hazards with forwarding ◼ How do we detect when to forward? Chapter 4 — The Processor — 38 Dependencies & Forwarding Chapter 4 — The Processor — 39 Detecting the Need to Forward ◼ Pass register numbers along pipeline ◼ e.g., ID/EX.RegisterRs = register number for Rs sitting in ID/EX pipeline register ◼ ALU operand register numbers in EX stage are given by ◼ ID/EX.RegisterRs, ID/EX.RegisterRt ◼ Data hazards when Fwd from 1a. EX/MEM.RegisterRd = ID/EX.RegisterRs EX/MEM pipeline reg 1b. EX/MEM.RegisterRd = ID/EX.RegisterRt 2a. MEM/WB.RegisterRd = ID/EX.RegisterRs Fwd from MEM/WB 2b. MEM/WB.RegisterRd = ID/EX.RegisterRt pipeline reg Chapter 4 — The Processor — 40 Detecting the Need to Forward ◼ But only if forwarding instruction will write to a register! ◼ EX/MEM.RegWrite, MEM/WB.RegWrite ◼ And only if Rd for that instruction is not $zero ◼ EX/MEM.RegisterRd ≠ 0, MEM/WB.RegisterRd ≠ 0 Chapter 4 — The Processor — 41 Forwarding Paths Chapter 4 — The Processor — 42  Forwarding Conditions Mux control Source Explanation ForwardA = 00 ID/EX The first ALU operand comes from the register file. ForwardA = 10 EX/MEM The first ALU operand is forwarded from the prior ALU result. ForwardA = 01 MEM/WB The first ALU operand is forwarded from data memory or an earlier ALU result. ForwardB = 00 ID/EX The second ALU operand comes from the register file. ForwardB = 10 EX/MEM The second ALU operand is forwarded from the prior ALU result. ForwardB = 01 MEM/WB The second ALU operand is forwarded from data memory or an earlier ALU result. Chapter 4 — The Processor — 43 Double Data Hazard ◼ Consider the sequence: add $1,$1,$2 add $1,$1,$3 add $1,$1,$4 ◼ Both hazards occur ◼ Want to use the most recent ◼ Revise MEM hazard condition ◼ Only fwd if EX hazard condition isn’t true Chapter 4 — The Processor — 44 Revised Forwarding Condition ◼ MEM hazard ◼ if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0) and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01 ◼ if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0) and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01 Chapter 4 — The Processor — 45 Datapath with Forwarding Chapter 4 — The Processor — 46 Load-Use Data Hazard Need to stall for one cycle Chapter 4 — The Processor — 47 Load-Use Hazard Detection ◼ Check when using instruction is decoded in ID stage ◼ ALU operand register numbers in ID stage are given by ◼ IF/ID.RegisterRs, IF/ID.RegisterRt ◼ Load-use hazard when ◼ ID/EX.MemRead and ((ID/EX.RegisterRt = IF/ID.RegisterRs) or (ID/EX.RegisterRt = IF/ID.RegisterRt)) ◼ If detected, stall and insert bubble Chapter 4 — The Processor — 48 How to Stall the Pipeline ◼ Force control values in ID/EX register to 0 ◼ EX, MEM and WB do nop (no-operation) ◼ Prevent update of PC and IF/ID register ◼ Using instruction is decoded again ◼ Following instruction is fetched again ◼ 1-cycle stall allows MEM to read data for lw ◼ Can subsequently forward to EX stage Chapter 4 — The Processor — 49 Load-Use Data Hazard Stall inserted here Chapter 4 — The Processor — 50 Load-Use Data Hazard Or, more accurately… Chapter 4 — The Processor — 51 Datapath with Hazard Detection Chapter 4 — The Processor — 52 Stalls and Performance The BIG Picture ◼ Stalls reduce performance ◼ But are required to get correct results ◼ Compiler can arrange code to avoid hazards and stalls ◼ Requires knowledge of the pipeline structure Chapter 4 — The Processor — 53  §4.9 Control Hazards Branch Hazards ◼ If branch outcome determined in MEM Flush these instructions (Set control values to 0) PC Chapter 4 — The Processor — 54 Reducing Branch Delay ◼ Move hardware to determine outcome to ID stage ◼ Target address adder ◼ Register comparator ◼ Example: branch taken 36: sub $10, $4, $8 40: beq $1, $3, 7 44: and $12, $2, $5 48: or $13, $2, $6 52: add $14, $4, $2 56: slt $15, $6, $7... 72: lw $4, 50($7) Chapter 4 — The Processor — 55 Example: Branch Taken Chapter 4 — The Processor — 56 Example: Branch Taken Chapter 4 — The Processor — 57 Data Hazards for Branches ◼ If a comparison register is a destination of 2nd or 3rd preceding ALU instruction add $1, $2, $3 IF ID EX MEM WB add $4, $5, $6 IF ID EX MEM WB … IF ID EX MEM WB beq $1, $4, target IF ID EX MEM WB ◼ Can resolve using forwarding Chapter 4 — The Processor — 58 Data Hazards for Branches ◼ If a comparison register is a destination of preceding ALU instruction or 2nd preceding load instruction ◼ Need 1 stall cycle lw $1, addr IF ID EX MEM WB add $4, $5, $6 IF ID EX MEM WB beq stalled IF ID beq $1, $4, target ID EX MEM WB Chapter 4 — The Processor — 59 Data Hazards for Branches ◼ If a comparison register is a destination of immediately preceding load instruction ◼ Need 2 stall cycles lw $1, addr IF ID EX MEM WB beq stalled IF ID beq stalled ID beq $1, $0, target ID EX MEM WB Chapter 4 — The Processor — 60 Dynamic Branch Prediction ◼ In deeper and superscalar pipelines, branch penalty is more significant ◼ Use dynamic prediction ◼ Branch prediction buffer (aka branch history table) ◼ Indexed by recent branch instruction addresses ◼ Stores outcome (taken/not taken) ◼ To execute a branch ◼ Check table, expect the same outcome ◼ Start fetching from fall-through or target ◼ If wrong, flush pipeline and flip prediction Chapter 4 — The Processor — 61 1-Bit Predictor: Shortcoming ◼ Inner loop branches mispredicted twice! outer: … … inner: … … beq …, …, inner … beq …, …, outer ◼ Mispredict as taken on last iteration of inner loop ◼ Then mispredict as not taken on first iteration of inner loop next time around Chapter 4 — The Processor — 62 2-Bit Predictor ◼ Only change prediction on two successive mispredictions Chapter 4 — The Processor — 63 Calculating the Branch Target ◼ Even with predictor, still need to calculate the target address ◼ 1-cycle penalty for a taken branch ◼ Branch target buffer ◼ Cache of target addresses ◼ Indexed by PC when instruction fetched ◼ If hit and instruction is branch predicted taken, can fetch target immediately Chapter 4 — The Processor — 64  §4.10 Exceptions Exceptions and Interrupts ◼ “Unexpected” events requiring change in flow of control ◼ Different ISAs use the terms differently ◼ Exception ◼ Arises within the CPU ◼ e.g., undefined opcode, overflow, syscall, … ◼ Interrupt ◼ From an external I/O controller ◼ Dealing with them without sacrificing performance is hard Chapter 4 — The Processor — 65 Handling Exceptions ◼ In MIPS, exceptions managed by a System Control Coprocessor (CP0) ◼ Save PC of offending (or interrupted) instruction ◼ In MIPS: Exception Program Counter (EPC) ◼ Save indication of the problem ◼ In MIPS: Cause register ◼ We’ll assume 1-bit ◼ 0 for undefined opcode, 1 for overflow ◼ Jump to handler at 8000 00180 Chapter 4 — The Processor — 66 An Alternate Mechanism ◼ Vectored Interrupts ◼ Handler address determined by the cause ◼ Example: ◼ Undefined opcode: C000 0000 ◼ Overflow: C000 0020 ◼ …: C000 0040 ◼ Instructions either ◼ Deal with the interrupt, or ◼ Jump to real handler Chapter 4 — The Processor — 67 Handler Actions ◼ Read cause, and transfer to relevant handler ◼ Determine action required ◼ If restartable ◼ Take corrective action ◼ use EPC to return to program ◼ Otherwise ◼ Terminate program ◼ Report error using EPC, cause, … Chapter 4 — The Processor — 68 Exceptions in a Pipeline ◼ Another form of control hazard ◼ Consider overflow on add in EX stage add $1, $2, $1 ◼ Prevent $1 from being clobbered ◼ Complete previous instructions ◼ Flush add and subsequent instructions ◼ Set Cause and EPC register values ◼ Transfer control to handler ◼ Similar to mispredicted branch ◼ Use much of the same hardware Chapter 4 — The Processor — 69 Pipeline with Exceptions Chapter 4 — The Processor — 70 Exception Properties ◼ Restartable exceptions ◼ Pipeline can flush the instruction ◼ Handler executes, then returns to the instruction ◼ Refetched and executed from scratch ◼ PC saved in EPC register ◼ Identifies causing instruction ◼ Actually PC + 4 is saved ◼ Handler must adjust Chapter 4 — The Processor — 71 Exception Example ◼ Exception on add in 40 sub $11, $2, $4 44 and $12, $2, $5 48 or $13, $2, $6 4C add $1, $2, $1 50 slt $15, $6, $7 54 lw $16, 50($7) … ◼ Handler 80000180 sw $25, 1000($0) 80000184 sw $26, 1004($0) … Chapter 4 — The Processor — 72 Exception Example Chapter 4 — The Processor — 73 Exception Example Chapter 4 — The Processor — 74 Multiple Exceptions ◼ Pipelining overlaps multiple instructions ◼ Could have multiple exceptions at once ◼ Simple approach: deal with exception from earliest instruction ◼ Flush subsequent instructions ◼ “Precise” exceptions ◼ In complex pipelines ◼ Multiple instructions issued per cycle ◼ Out-of-order completion ◼ Maintaining precise exceptions is difficult! Chapter 4 — The Processor — 75 Imprecise Exceptions ◼ Just stop pipeline and save state ◼ Including exception cause(s) ◼ Let the handler work out ◼ Which instruction(s) had exceptions ◼ Which to complete or flush ◼ May require “manual” completion ◼ Simplifies hardware, but more complex handler software ◼ Not feasible for complex multiple-issue out-of-order pipelines Chapter 4 — The Processor — 76  §4.11 Parallelism via Instructions Instruction-Level Parallelism (ILP) ◼ Pipelining: executing multiple instructions in parallel ◼ To increase ILP ◼ Deeper pipeline ◼ Less work per stage  shorter clock cycle ◼ Multiple issue ◼ Replicate pipeline stages  multiple pipelines ◼ Start multiple instructions per clock cycle ◼ CPI < 1, so use Instructions Per Cycle (IPC) ◼ E.g., 4GHz 4-way multiple-issue ◼ 16 BIPS, peak CPI = 0.25, peak IPC = 4 ◼ But dependencies reduce this in practice Chapter 4 — The Processor — 77 Multiple Issue ◼ Static multiple issue ◼ Compiler groups instructions to be issued together ◼ Packages them into “issue slots” ◼ Compiler detects and avoids hazards ◼ Dynamic multiple issue ◼ CPU examines instruction stream and chooses instructions to issue each cycle ◼ Compiler can help by reordering instructions ◼ CPU resolves hazards using advanced techniques at runtime Chapter 4 — The Processor — 78 Speculation ◼ “Guess” what to do with an instruction ◼ Start operation as soon as possible ◼ Check whether guess was right ◼ If so, complete the operation ◼ If not, roll-back and do the right thing ◼ Common to static and dynamic multiple issue ◼ Examples ◼ Speculate on branch outcome ◼ Roll back if path taken is different ◼ Speculate on load ◼ Roll back if location is updated Chapter 4 — The Processor — 79 Compiler/Hardware Speculation ◼ Compiler can reorder instructions ◼ e.g., move load before branch ◼ Can include “fix-up” instructions to recover from incorrect guess ◼ Hardware can look ahead for instructions to execute ◼ Buffer results until it determines they are actually needed ◼ Flush buffers on incorrect speculation Chapter 4 — The Processor — 80 Speculation and Exceptions ◼ What if exception occurs on a speculatively executed instruction? ◼ e.g., speculative load before null-pointer check ◼ Static speculation ◼ Can add ISA support for deferring exceptions ◼ Dynamic speculation ◼ Can buffer exceptions until instruction completion (which may not occur) Chapter 4 — The Processor — 81 Static Multiple Issue ◼ Compiler groups instructions into “issue packets” ◼ Group of instructions that can be issued on a single cycle ◼ Determined by pipeline resources required ◼ Think of an issue packet as a very long instruction ◼ Specifies multiple concurrent operations ◼  Very Long Instruction Word (VLIW) Chapter 4 — The Processor — 82 Scheduling Static Multiple Issue ◼ Compiler must remove some/all hazards ◼ Reorder instructions into issue packets ◼ No dependencies with a packet ◼ Possibly some dependencies between packets ◼ Varies between ISAs; compiler must know! ◼ Pad with nop if necessary Chapter 4 — The Processor — 83 MIPS with Static Dual Issue ◼ Two-issue packets ◼ One ALU/branch instruction ◼ One load/store instruction ◼ 64-bit aligned ◼ ALU/branch, then load/store ◼ Pad an unused instruction with nop Address Instruction type Pipeline Stages n ALU/branch IF ID EX MEM WB n+4 Load/store IF ID EX MEM WB n+8 ALU/branch IF ID EX MEM WB n + 12 Load/store IF ID EX MEM WB n + 16 ALU/branch IF ID EX MEM WB n + 20 Load/store IF ID EX MEM WB Chapter 4 — The Processor — 84 MIPS with Static Dual Issue Chapter 4 — The Processor — 85 Hazards in the Dual-Issue MIPS ◼ More instructions executing in parallel ◼ EX data hazard ◼ Forwarding avoided stalls with single-issue ◼ Now can’t use ALU result in load/store in same packet ◼ add $t0, $s0, $s1 load $s2, 0($t0) ◼ Split into two packets, effectively a stall ◼ Load-use hazard ◼ Still one cycle use latency, but now two instructions ◼ More aggressive scheduling required Chapter 4 — The Processor — 86 Scheduling Example ◼ Schedule this for dual-issue MIPS Loop: lw $t0, 0($s1) # $t0=array element addu $t0, $t0, $s2 # add scalar in $s2 sw $t0, 0($s1) # store result addi $s1, $s1,–4 # decrement pointer bne $s1, $zero, Loop # branch $s1!=0 ALU/branch Load/store cycle Loop: nop lw $t0, 0($s1) 1 addi $s1, $s1,–4 nop 2 addu $t0, $t0, $s2 nop 3 bne $s1, $zero, Loop sw $t0, 4($s1) 4 ◼ IPC = 5/4 = 1.25 (c.f. peak IPC = 2) Chapter 4 — The Processor — 87 Loop Unrolling ◼ Replicate loop body to expose more parallelism ◼ Reduces loop-control overhead ◼ Use different registers per replication ◼ Called “register renaming” ◼ Avoid loop-carried “anti-dependencies” ◼ Store followed by a load of the same register ◼ Aka “name dependence” ◼ Reuse of a register name Chapter 4 — The Processor — 88 Loop Unrolling Example ALU/branch Load/store cycle Loop: addi $s1, $s1,–16 lw $t0, 0($s1) 1 nop lw $t1, 12($s1) 2 addu $t0, $t0, $s2 lw $t2, 8($s1) 3 addu $t1, $t1, $s2 lw $t3, 4($s1) 4 addu $t2, $t2, $s2 sw $t0, 16($s1) 5 addu $t3, $t4, $s2 sw $t1, 12($s1) 6 nop sw $t2, 8($s1) 7 bne $s1, $zero, Loop sw $t3, 4($s1) 8 ◼ IPC = 14/8 = 1.75 ◼ Closer to 2, but at cost of registers and code size Chapter 4 — The Processor — 89 Dynamic Multiple Issue ◼ “Superscalar” processors ◼ CPU decides whether to issue 0, 1, 2, … each cycle ◼ Avoiding structural and data hazards ◼ Avoids the need for compiler scheduling ◼ Though it may still help ◼ Code semantics ensured by the CPU Chapter 4 — The Processor — 90 Dynamic Pipeline Scheduling ◼ Allow the CPU to execute instructions out of order to avoid stalls ◼ But commit result to registers in order ◼ Example lw $t0, 20($s2) addu $t1, $t0, $t2 sub $s4, $s4, $t3 slti $t5, $s4, 20 ◼ Can start sub while addu is waiting for lw Chapter 4 — The Processor — 91  Dynamically Scheduled CPU Preserves dependencies Hold pending operands Results also sent to any waiting reservation stations Reorders buffer for register writes Can supply operands for issued instructions Chapter 4 — The Processor — 92 Register Renaming ◼ Reservation stations and reorder buffer effectively provide register renaming ◼ On instruction issue to reservation station ◼ If operand is available in register file or reorder buffer ◼ Copied to reservation station ◼ No longer required in the register; can be overwritten ◼ If operand is not yet available ◼ It will be provided to the reservation station by a function unit ◼ Register update may not be required Chapter 4 — The Processor — 93 Speculation ◼ Predict branch and continue issuing ◼ Don’t commit until branch outcome determined ◼ Load speculation ◼ Avoid load and cache miss delay ◼ Predict the effective address ◼ Predict loaded value ◼ Load before completing outstanding stores ◼ Bypass stored values to load unit ◼ Don’t commit load until speculation cleared Chapter 4 — The Processor — 94 Why Do Dynamic Scheduling? ◼ Why not just let the compiler schedule code? ◼ Not all stalls are predicable ◼ e.g., cache misses ◼ Can’t always schedule around branches ◼ Branch outcome is dynamically determined ◼ Different implementations of an ISA have different latencies and hazards Chapter 4 — The Processor — 95 Does Multiple Issue Work? The BIG Picture ◼ Yes, but not as much as we’d like ◼ Programs have real dependencies that limit ILP ◼ Some dependencies are hard to eliminate ◼ e.g., pointer aliasing ◼ Some parallelism is hard to expose ◼ Limited window size during instruction issue ◼ Memory delays and limited bandwidth ◼ Hard to keep pipelines full ◼ Speculation can help if done well Chapter 4 — The Processor — 96