Unit-1 (Basic VLSI System Design) PDF

Subject: Digital System Design Subject code: EC20005 Module 1: Basic VLSI System Design  Introduction to Digital System System- A set of related components work as a whole to achieve a goal A system contains Input...

Subject: Digital System Design Subject code: EC20005 Module 1: Basic VLSI System Design  Introduction to Digital System System- A set of related components work as a whole to achieve a goal A system contains Input Behavior Output Inputs Behavior Outputs Behavior is a function that translates inputs to outputs  Contents Introduction to digital systems and VLSI design, Moore’s Law VLSI Design flow, Design hierarchy Introduction to Verilog HDL and operators Modelling techniques (Gate-level, Data-flow, and Behavioral) Example: Half-adder implementation  Introduction (conti..) Components are electronic blocks: Digital, Analog or mixed signal – Digital System is a system in which signals have a finite number of discrete values – Analog system has values from a continuous set – Mixed signal system has both digital and analog parts  Analog and Digital Signals Analog signals are After digitization, the continuous in time and continuous analog signal voltage or current. becomes a set of discrete values, typically separated by fixed time intervals.  Advantages of Digital Sytems Digital representation is very well suited for both numerical and non-numerical information processing Easy to design, particularly the automated design and fabrication Low cost Easy to duplicate similar circuits High noise immunity Easily controllable by computer-The finite number of values in a digital system can be represented by a vector of signals with just two values(Binary signals) eg. 5 is 0101 and 9 is 1001 So the device which process this signal is very simple say a switch- open/closed Adjustable precision Complex digital ICs are manufactured with the advent of Microelectronics Technology  Some of the disadvantages of Digital systems (conti..) Lower speed The physical world is analog so, needs to convert digital to analog and vice versa to communicate with real world. This makes the digital system expensive and less precision Digital abstraction allows analog signals to be ignored and allow some discrete values to be used Example is Binary system;only two values are allowed- 1 and 0  1 means high value or logic “TRUE”  0 means low value or logic “FALSE”  Digital System Example Digital Computer Digital calculator Digital Watch Introduction to digital systems  Analog and Digital Signals (conti..) Summary: Analog signals suffer from noise, but don’t need such complex equipment. Digital signals need fast, clever electronics, but we can get rid of any noise. Introduction to VLSI design: Integration Density  MOORE'S LAW: The number of transistors in a chip doubles in every two years Moore's law is nothing but a prediction made by the Gordon Moore in year 1965 that the no. of transistors in IC would double every two years which would increase speed and capability of computer every two years and their prices would drop, their growth would be exponential.  Let’s take the case of Intel Moore’s law. In 1971, Intel introduced the Intel 4004 with a transistor count of 2250. And in 1974, the Intel 8080 processor came with the ability of 6,000 transistors. Two years later, Intel introduced the Intel 8085 processor with 6,500 transistors in 1976. In 1978, the Intel 8086 came with a transistor count of 29,000. Then, the Intel 8051 came in 1980 with 50,000 transistors, followed by the Intel 80186 with 55,000 transistors in 1982. Finally, in 1985, the Intel 80386 had a 275,000 transistor count. This came to be known as the Intel Moore’s Law. From the above data, it is evident that there have been increments in the transistor counts over the years with a period of two years. Moore’s Law  Specification of Digital Systems Specification of system is the description of its function and other characteristics required for it  Speed  Area Performance (Speed)  Power Power Area (Energy (Complexity) dissipation)  Specification(conti..) Design can be improved at the expense of worsening one or both of the others These trade-offs exist at entry level in the system design every sub-piece and component A designer must make the trade-offs necessary to achieve the function within the constraints Specifications should have following properties:  simple but complete  Interpretation is unambiguous  SYSTEM VLSI Design Flow SPECIFICATION ARCHITECTURE DESIGN BEHAVIOURAL FUNCTIONAL VERIFICATION REPRESENTATION (Flow Graph, Pseudo Code) LOGIC DESIGN LOGIC(GATE-LEVEL) LOGIC VERIFICATION REPRESENTATION (Gate Wirelist, Netlist) CIRCUIT DESIGN CIRCUIT CIRCUIT VERIFICATION REPRESENTATION PHYSICAL DESIGN LAYOUT REPRESENTATION LAYOUT VERIFICATION (Transistor list, layout) FABRICATION AND TESTING (Chip or Board)  The Figure provides a simplified view of the VLSI design flow, taking into account the various representations, or abstractions of design - behavioral, logic, circuit and mask layout. Note that the verification of design plays a very important role in every step during this process. The failure to properly verify a design in its early phases typically causes significant and expensive re-design at a later stage, which ultimately increases the time-to-market. Although the design process has been described in linear fashion for simplicity, in reality there are many iterations back and forth, especially between any two neighboring steps, and occasionally even remotely separated pairs. Although top-down design flow provides an excellent design process control, in reality, there is no truly unidirectional top-down design flow. Both top-down and bottom-up approaches have to be combined. For instance, if a chip designer defined an architecture without close estimation of the corresponding chip area, then it is very likely that the resulting chip layout exceeds the area limit of the available technology. Some of the classical techniques for reducing the complexity of IC design are: hierarchy, regularity, modularity and locality.  Steps of the VLSI Design Flow 1. Specification and Architecture This is the initial stage where the requirements for the IC or SoC are defined, including the functionality, performance, power consumption, and area constraints. 2. Design Entry This involves creating a high-level design representation of the IC or SoC using a hardware description language (HDL) such as Verilog or VHDL. 3. Functional Verification This step involves verifying that the high-level design meets the specifications by simulating it using a hardware simulator.  Steps of the VLSI Design Flow(Conti..) 4. Synthesis In this step, the high-level design is translated into a gate- level netlist, which is a collection of logic gates and flip-flops that implement the design. 5. Design Optimization The gate-level netlist is optimized for various design constraints such as power consumption, timing, and area. 6. Physical Design This step involves placing the gates and routing the interconnections to meet the timing and area constraints.  Steps of the VLSI Design Flow(Conti..) 7.Design Rule Check (DRC) The physical design is checked against a set of design rules to ensure it is manufacturable. 8. Layout Verification The physical design is verified using simulations to ensure that it meets the specifications. 9. Tape-out Once the physical design is verified, the final design is sent to the fabrication facility for manufacturing. 10. Testing After the IC or SoC is fabricated, it is tested to ensure that it meets the specifications.  Design Hierarchy The use of hierarchy, or “divide and conquer” technique involves dividing a module into sub- modules and then repeating this operation on the sub-modules until the complexity of the smaller parts becomes manageable. This approach is very similar to the software case where large programs are split into smaller and smaller sections until simple subroutines, with well-defined functions and interfaces, can be written.  Implementation of Digital System Implementation means how the system is constructed from smaller and simpler components called modules The modules can vary from simple gates to complex processors Digital system follows some hierarchical implementation  Hierarchical Implementation Modular design Divide and conquer Modules are designed and buit separately and then assembled to form the system Simplifies implementation and debugging One of the major factors for cost effectiveness of digital systems Hierarchical Implementation(conti..) Top-Down Design Starts at the top(root) and works down by successive refinement decomposes the system into subsystem and the subsystem into simpler and smaller subsystems and so on stops when subsystem can be realized by directly available module  Hierarchical Implementation(conti..) Bottom-up Design Starts at the leaves and puts pieces together to buid up the design subsystems are assembled to form a bigger subsystem stops when required functional specification is achieved  Hierarchical Implementation(conti..) Disadvantages of Top-down or Bottom-up design No systematic procedure exists for decomposition (in case of Top-down) or composition (in case of Bottom-up) Depends on the expertise of the designer  Hierarchical Implementation(conti..) Which is better? In practice both Top-down and Bottom-up design approaches are needed and used Need top-down divide and conquer to handle the complexity Need bottom-up because in a well designed system the structure is influenced by what primitives are available  Design Hierarchy Structural decomposition of a four- bit adder circuit, showing the hierarchy down to gate level Fig. shows the structural decomposition of a CMOS four-bit adder into its components. The adder can be decomposed progressively into one- bit adders, separate carry and sum circuits, and finally, into individual logic gates. At this lower level of the hierarchy, the design of a simple circuit realizing a well-defined Boolean function is much more easier to handle than at the higher levels of the hierarchy.  Hardware Description Languages 1. VHDL (VHSIC-very high speed integrated circuit) 2. Verilog HDL Verilog HDL is one of the two most common Hardware Description Languages (HDL) used by integrated circuit(IC) designers. Designs described in HDL are technology-independent, easy to design and debug, and are usually more readable than schematics, particularly for large circuits.  Advantages of Verilog C-like syntax (easy to learn and write) More compact code (simpler and intuitive syntax) Block commenting No heavy component instantiation as in VHDL Switch Level modelling is only possible in Verilog  Modelling techniques A module is a basic building block in Verilog and can There are four levels of design abstractions Switch-level (lowest level modelling) Gate-level Data-flow Behavioral (Algorithmic Level)-highest level modelling f any complexity.  Gate Level Modeling This is the basic level of modeling in terms of logic gates and the connections between these gates. Most digital designs are now done at the gate level or higher levels of abstractions. At gate level, the circuit is described in terms of gates say AND, OR etc. Hardware design at this level is intuitive for a user who is familiar with the basic knowledge of Digital logic Design. This allows the user to see a direct correspondence between the Verilog Description and the Circuit Diagram.  Data Flow Modeling The design at this level specifies how the data flows between the hardware registers and how the data is processed. For small circuits the gate level modeling works well as the number of gates is limited. However, in complex designs the designers may have to concentrate on implementing the function than bother about the gates. Verilog allows a circuit to be designed in terms of the data flow between registers and how a design processes data rather than instantiation of gates using expressions (=), operators like (&,|,?) etc.. and continuous assignments(the assign statement).  Behavioral Modeling This is the highest level of abstraction provided by Verilog. The design at this level is similar to an algorithm. This design is very similar to C programming. A module can be implemented in terms of the desired design algorithm without looking into the hardware details using structured procedures (like always and initial), conditional statements (like if and else) and multi way branching (like case, case x and case z).  Behavioural Representation Behavioural representation describes how a particular design should respond to a given set of inputs. Behaviour may be specified by Boolean Equations Tables of input and output values algorithms written in standard high level computer language or in special hardware description language  Operators Arithmetic Operators These perform arithmetic operations. The + and - can be used as either unary (-z) or binary (x-y) operators. Operators  + (addition)  - (subtraction)  * (multiplication) Example:  / (division) parameter n = 4;  % (modulus) reg[3:0] a, c, f, g, count;  ** (exponentiation) f = a + c; g = c - n; count = (count +1)%16; //Can count 0 thru 15.  Operators Relational Operators Relational operators compare two operands and return a single bit 1or 0. These operators synthesize into comparators. Wire and reg variables are positive Thus (-3’b001) = = 3’b111 and (- 3d001)>3d110. However for integers -1< 6. Operators Example:  < (less than) if (x = = y) e = 1;  (greater than) else e = 0;  >= (greater than or equal to) // Compare in 2’s compliment; a>b  == (equal to) reg [3:0] a,b;  != (not equal to) if (a= = b) a[2:0] > b[2:0]; else b;  Operators Bit-wise Operators Bit-wise operators do a bit-by-bit comparison between two operands. Operators  ~ (bitwise NOT)  & (bitwise AND)  | (bitwise OR)  ^ (bitwise XOR) Example:  ~^ or ^~(bitwise XNOR) module and2 (a, b, c); input [1:0] a, b; output [1:0] c; assign c = a & b; endmodule  Operators Logical Operators Logical operators return a single bit 1 or 0. They are the same as bit-wise operators only for single bit operands. They can work on expressions, integers or groups of bits, and treat all values that are nonzero as “1”. Logical operators are typically used in conditional (if... else) statements since they work with expressions. Operators Example:  ! (logical NOT) wire[7:0] x, y, z; // x, y and z are multibit variables.  && (logical AND) reg a;  || (logical OR)... if ((x == y) && (z)) a = 1; // a = 1 if x equals y, and z is nonzero. else a = !x; // a =0 if x is anything but zero.  Operators Reduction Operators Reduction operators operate on all the bits of an operand vector and return a single-bit value. These are the unary (one argument) form of the bit-wise operators above. Example: Operators module chk_zero (a, z);  & (reduction AND) input [2:0] a;  | (reduction OR) output z;  ~& (reduction NAND) assign z = ~| a; // Reduction NOR  ~| (reduction NOR) endmodule  ^ (reduction XOR)  ~^ or ^~(reduction XNOR)  Operators Shift Operators Shift operators shift the first operand by the number of bits specified by the second operand. Vacated positions are filled with zeros for both left and right shifts (There is no sign extension). Operators Example: assign c = a (shift right)  Operators Concatenation Operator The concatenation operator combines two or more operands to form a larger vector. Operators  { }(concatenation) Example: wire [1:0] a, b; wire [2:0] x; wire [3;0] y, Z; assign x = {1’b0, a}; // x=0, x=a, x=a assign y = {a, b}; assign {cout, y} = x + Z; // Concatenation of a result  Operators Replication Operator The replication operator makes multiple copies of an item. Operators  {n{item}} (n fold replication of an item) Example: wire [1:0] a, b; wire [4:0] x; assign x = {2{1’b0}, a}; // Equivalent to x = {0,0,a } assign y = {2{a}, 3{b}}; //Equivalent to y ={a,a,b,b,b}  Operators Conditional Operator: “?” Conditional operator is like those in C/C++. They evaluate one of the two expressions based on a condition. It will synthesize to a multiplexer (MUX). Operators  (cond) ? (result if cond true): (result if cond false) Example: assign a = (g) ? x : y; assign a = (inc = = 2) ? a+1 : a-1; ways end ifnone or rpmos tranif1 Reserved Keywords and endcase initial output rtran tri assign endmodule inout parameter rtranif0 tri0 begin endfunction input pmos rtranif1 tri1 Verilog endprimitiv buf integer posedge scalared triand Reserved Key e bufif0 endspecify join primitive small trior bufif1 Words endtable large pull0 specify trireg case endtask macromodule pull1 specparam vectored casex event medium pullup strong0 wait casez for module pulldown strong1 wand cmos force nand rcmos supply0 weak0 deassign forever negedge real supply1 weak1 default for nmos realtime table while defparam function nor reg task wire disable highz0 not release time wor edge highz1 notif0 repeat tran xnor else if notif1 rnmos tranif0 xor  Logic gates Keywords for Logic Gates: buf , not, and, nand, or, nor, xor, xnor. Example: Half-adder implementation a b Sum Carry 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1  Half Adder Verilog Code: Gate level Modelling module half_adder(sum, carry, a, b); “module” is the basic building block in Verilog. In Verilog, a module is declared by the keyword input a, b; “module”. A corresponding keyword “endmodule” must appear output sum, carry; at the end of the module definition. Each module must have a module_name, which is xor sum1(sum, a, b); the identifier for the module, and a port list, which describes the input and output terminals of the module and carry1(carry, a, b); The module name, formally called an identifier should best endmodule describe what the system is doing. Each identifier in Verilog, including module names must follow these rules: It can be composed of letters, digits, dollar sign ($), and underscore characters (_) only. It must start with a letter or underscore. No spaces are allowed inside an identifier. Upper and lower case characters are distinguished (Verilog is case sensitive) Reserved keywords cannot be used as identifiers.  Testbench for half-adder module half_adder_testbench; a = 1'b1; reg a,b; b = 1'b0; wire sum,cout; #20; Verilog data-type reg can be used to half_adder h1(sum, carry, a, b); model hardware registers since it can hold values between assignments. a = 1'b1; A wire represents a physical wire in a initial begin b = 1'b1; circuit and is used to connect gates or a = 1'b0; #20; modules. The value of a wire can be b = 1'b0; read, but not assigned to, in a function or block. #20; $finish; end a = 1'b0; endmodule b = 1'b1; #20; NOTE: Testbench is same for all types of modelling  Half Adder Verilog Code: Dataflow Modelling module half_adder(sum, carry, a, b); input a,b; output sum,carry; // sum and carry assign sum = a^b; assign is used for driving wire/net type declarations. assign carry = a&b ; Since wires change values according to the value driving them, whenever the operands on the RHS endmodule changes,the value is evaluated and assigned to LHS( thereby simulating a wire).  Half Adder Verilog Code:Behavioral Modelling module half_adder(sum, carry, a, b); input a,b; always is a procedural block is used for output reg sum,carry; // sum and carry modelling registers and combinational logic. always @(*) begin always block contains sensitivity list, that is, case ({a,b}) the event list, upon which the logic inside the 2'b00: begin sum = 0;carry=0;end block must be evaluated. 2'b01: begin sum = 1;carry=0;end 2'b10: begin sum = 1;carry=0; end always(@ posedge clk) triggers the the logic 2'b11: begin sum = 0;carry=1; end inside the block at every positive edge. default : begin sum = 0;carry=0; end endcase end endmodule