VLSI Design Flow: RTL To GDS Lecture 29 - Power Analysis PDF

VLSI DESIGN FLOW: RTL TO GDS Lecture 29 Power Analysis Sneh Saurabh Electronics and Communications Engineering IIIT Delhi Lecture...

VLSI DESIGN FLOW: RTL TO GDS Lecture 29 Power Analysis Sneh Saurabh Electronics and Communications Engineering IIIT Delhi Lecture Plan Power Analysis: ▪ Components of Power Dissipation ▪ Power Models in Library ▪ Estimating Power Dissipation VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Components of Power Dissipation Power dissipation is broadly of two types: 1. Dynamic Power Dissipation: Occurs when a circuit performs computation actively 2. Static Power Dissipation: When the circuit is powered on (supply voltages are applied), but it does not perform active computation VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Dynamic Power Dissipation: Switching Power Switching power dissipated in a synchronous circuit: 2 𝑃𝑠𝑤 = 𝐶𝐿 𝑉𝐷𝐷 𝛼𝑓𝑐𝑙𝑘 where, ▪ 𝑓𝑐𝑙𝑘 =frequency of the clock in the circuit ▪ 𝛼 =activity of the signal define 𝛼 = 1 when the output completes one cycle of transition (1→0→1) in one ▪ Energy dissipated in one cycle of 0→1→0 clock period transition: 2 𝐸𝑠𝑤 = 𝐶𝐿 𝑉𝐷𝐷 VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Dynamic Power Dissipation: Short circuit Power ▪ Short circuit power dissipation: 𝑃𝑠𝑐 = 𝑉𝐷𝐷 𝐼𝑆𝐶 ▪ Power dissipated when short circuit condition occur: 𝑃𝑑𝑦𝑛 = 𝑃𝑠𝑤 + 𝑃𝑠𝑐 VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Static Power Dissipation ▪ Static power dissipation occurs because of: Subthreshold current Gate Leakage Junction Leakage ▪ 𝑃𝑠𝑡𝑎𝑡 = 𝑉𝐷𝐷 𝐼𝑙𝑒𝑎𝑘 Total power dissipation in a circuit: 𝑃𝑡𝑜𝑡 = 𝑃𝑑𝑦𝑛 + 𝑃𝑠𝑡𝑎𝑡 VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Technology Library Models: Dynamic Power Energy dissipated in one cycle of 0→1→0 transition: 2 𝐸𝑑𝑦𝑛 = 𝐶𝐿 𝑉𝐷𝐷 + 𝑉𝐷𝐷 𝐼𝑆𝐶 𝜏𝑆𝐶 2 𝐸𝑑𝑦𝑛 = (𝐶𝑑 +𝐶𝑤 + 𝐶𝐼 )𝑉𝐷𝐷 + 𝑉𝐷𝐷 𝐼𝑆𝐶 𝜏𝑆𝐶 We can write: 2 2 𝐸𝑑𝑦𝑛 = 𝐶𝑑 𝑉𝐷𝐷 + 𝑉𝐷𝐷 𝐼𝑆𝐶 𝜏𝑆𝐶 + (𝐶𝑤 +𝐶𝐼 )𝑉𝐷𝐷 = 𝐸𝑖𝑛𝑡 +𝐸𝑒𝑥𝑡 ▪ Energy dissipated inside a cell 𝐸𝑖𝑛𝑡 is the property of the cell and modelled in the library ▪ Energy dissipated outside a cell 𝐸𝑒𝑥𝑡 depends on the environment (external load) Tools can compute it after (𝐶𝑤 +𝐶𝐼 ) is known ▪ Power can be estimated using energy per transition by multiplying with activity and clock frequency VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Non-linear Power Model (NLPM) ▪ Internal power dissipation depends on the output-load and input slew u_table_template(index_1) { ▪ Modelled as two-dimensional table named variable_1 : input_net_transition ; internal_power variable_2 : total_output_net_capacitance ; index_1( "10, 20, 30" ) ; Referred to as Non-linear Power index_2( "1.2, 5.0,15.0, 37.5) ; Model (NLPM) } …. pin(Z) { internal_power() { related_pin : “A" ; rise_power(index_1) { values( "4, 5, 7, 12, …3x4 table); } ▪ Rise and fall power can be represented as … } different arcs } ▪ Values represent energy dissipated per S. Saurabh, “Introduction to VLSI Design Flow”.Cambridge University Press, 2023. transition VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Technology Library Models: Static Power ▪ Static power dissipated inside a CMOS logic gate depends on the value (0 or 1) cell (NAND2) {... at its input pin cell_leakage_power : 125; leakage_power () { ▪ Modeled using when condition in the when : “!A & !B”; value : 20; } library leakage_power () { when : “A & !B”; value : 150; } leakage_power () { when : “!A & B”; value : 200; } leakage_power () { when : “A & B”; value : 300; }... S. Saurabh, “Introduction to VLSI Design Flow”.Cambridge University Press, 2023. VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Estimating Power Dissipation 2 𝑃𝑡𝑜𝑡 = 𝐶𝐿 𝑉𝐷𝐷 𝛼𝑓𝑐𝑙𝑘 + 𝑉𝐷𝐷 𝐼𝑆𝐶 + 𝑉𝐷𝐷 𝐼𝑙𝑒𝑎𝑘 ▪ Computing power dissipation is a where, challenging problem. ▪ 𝑉𝐷𝐷 = supply voltage Capacitance estimation ▪ 𝐶𝐿 = load capacitance Accounting for the activity of signals ▪ 𝑓𝑐𝑙𝑘 = frequency of the clock in the circuit ▪ 𝛼 = activity of the signal Activity of a signal depends on: ▪ Application being run on an IC ▪ Logical structure and the circuit topology VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Estimation of Activity Simulation-based Techniques (Vector-based Technique): ▪ Perform simulation using test bench. ▪ Simulator generates the output response for all the nets [value change dump (VCD) files] Convert a VCD file into a format from which the activity measures can be easily extracted [switching activity interchange format (SAIF)] Provide the SAIF file to the power analysis tool Tools can also assume default activity [such as 0.2] Probabilistic Techniques (Vector-less Technique): ▪ Propagate the activity measures through the circuit by considering the logic function of the gates encountered in the path ▪ Example: Assume that static probabilities of signals A and B are 𝑃1𝐴 = 0.5 and 𝑃1𝐵 = 0.3 If they propagate through an AND gate: 𝑃1𝐴.𝐵 = 𝑃1𝐴. 𝑃1𝐵 = 0.5 × 0.3 = 0.15 If they propagate through an OR gate: 𝑃1𝐴+𝐵 = 1 − (1 − 𝑃1𝐴 ) 1 − 𝑃1𝐵 = 1 − 0.5 × 0.7 = 0.65 VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh  References ▪ N. H. Weste and D. Harris. “CMOS VLSI Design: A Circuits and Systems Perspective”. Pearson Education India, 2015. ▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press, 2023. soprotection.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh VLSI DESIGN FLOW: RTL TO GDS Lecture 30 Power Optimizations Sneh Saurabh Electronics and Communications Engineering IIIT Delhi Lecture Plan Overview of power-driven optimizations VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Strategies for Reducing Power Dissipation 2 𝑃𝑡𝑜𝑡 = 𝐶𝐿 𝑉𝐷𝐷 𝛼𝑓𝑐𝑙𝑘 + 𝑉𝐷𝐷 𝐼𝑆𝐶 + 𝑉𝐷𝐷 𝐼𝑙𝑒𝑎𝑘 Power saving strategies: where, ▪ Reduce supply voltage ▪ 𝑉𝐷𝐷 = supply voltage ▪ Reduce clock frequency ▪ 𝐶𝐿 = load capacitance ▪ Reduce activity of the signal ▪ 𝑓𝑐𝑙𝑘 = frequency of the clock in the circuit ▪ Reduce load capacitance ▪ 𝛼 = activity of the signal VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Dynamic Voltage Frequency Scaling (DVFS) ▪ Utilizes the strategy of reducing supply voltage and clock frequency ▪ Popular technique employed in processors: Exploit variations in workload to save energy Full speed of a processor is utilized by only a few tasks or for a small time duration. For the remaining period, the deadlines can be met at low speed and consuming significantly less energy Illustration: ▪ Consider a processor that can perform a task in 10 ms at 1.2 GHz and 1.2 V. ▪ Let us reduce the clock frequency and the supply voltage to half (600 MHz, 0.6 V), Task will now complete in double the original time, i.e., 20 ms. Will reduce the switching power dissipation by 1/8 (𝑃𝑡𝑜𝑡 ∝ 𝑉𝐷𝐷2 𝑓𝑐𝑙𝑘 ) Will reduce the energy consumption by 1/4 VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Power Gating ▪ Utilizes the strategy of eliminating supply voltage Power Gating: ▪ Switch off the power supply for a block ▪ Effective technique to tackle both static and dynamic components of power dissipation. ▪ Requires a careful circuit design and inserting specially designed circuit elements. VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Power Gating: Circuit Elements Circuit Elements ▪ Switch Cell ▪ Retention Cell ▪ Isolation Cell VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Clock Gating ▪ Utilizes the strategy of reducing activity Assume that there is a set of 𝑁 flip-flops that captures new data conditionally ▪ Shut off the clock when that condition is false ▪ Save power in charging/discharging capacitors in the clock network, including flip-flops ▪ Find enabling condition of clocking ▪ Simple AND of EN and CLK will lead to glitch VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Clock Gating: Integrated Clock Gater Integrated Clock Gater (ICG) ▪ Logic gate with an enable signal so that clock is propagated when the 𝐸𝑁 = 1 ▪ Latch (negative sensitive) allows EN to propagate only when CLK is low ▪ When CLK is high, Latch (LT) output is stable and glitch cannot propagate VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Resizing ▪ Resize cells to reduce power dissipation For example, we can use smaller cells in the noncritical path of a circuit Reduce the power dissipation due to the reduced load capacitances VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh  References ▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press, 2023. soprotection.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh VLSI DESIGN FLOW: RTL TO GDS Lecture 31 DFT: Basic Concepts Sneh Saurabh Electronics and Communications Engineering IIIT Delhi Lecture Plan ▪ Basic Concepts related to DFT VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Structural Testing Consider a circuit that implements a Boolean function with 𝑁 inputs. How to test the fabricated circuit? Functional Testing: ▪ Apply all possible 2𝑁 input combinations and check output ▪ Becomes infeasible for large 𝑁 (say 50 or 100) Structural Testing: ▪ Test the components that implements a logic function rather than testing the input–output functionality ▪ The paradigm of structural testing is widely employed It reduces the number of test patterns required for good test quality VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Functional Testing vs. Structural Testing Functional Testing ▪ Will require 216 = 65536 input combinations Structural Testing ▪ Test individual components of the circuit ( G1, G2, G3, G4, and G5) ▪ Each gate will require 24 = 16 input combinations (total 80) Assumptions ▪ Can observe the output pins for all the components ▪ Can write any value at the input pins of all the components ▪ There could be a problem in the integration of components (need to tackle that also). DFT techniques tries to make structural testing more effective by ensuring the above assumptions. VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Fault Models Fault Model ▪ Represents a defect using a logical or electrical model Why do we use a Fault Model? ▪ Allows us to analyze the impact of a defect using logic or circuit analysis techniques ▪ Allows deriving test patterns algorithmically for detecting a given fault Quantitative assessment of testing effectiveness using fault coverage ▪ Transforms the problem of defect detection to the problem of fault detection VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Stuck-at Fault Models Stuck-at Fault Model ▪ Assumes that defects cause the signal to be permanently stuck at a constant logic ▪ Transforms defects to a logical fault model ▪ Two types: Stuck at logic “0”: stuck-at-0 or SA0 fault Stuck at logic “1”: stuck-at-1 or SA1 fault Single Stuck-at Fault Model ▪ Assumes that there is only one fault active at a time ▪ Reduces the complexity of test pattern generation significantly VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Stuck-at Faults: Fault-site Fault-site: ▪ The point where a fault exists or we assume it to exist ▪ Emulate a stuck-at fault by first disconnecting the corresponding signal source. ▪ Tie it to the constant logic (either 0 or 1 depending on the fault type) Multi-fanout net (N>1): ▪ (N+1) fault sites Fanout-free net: ▪ 1 fault site VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Possible Stuck-at Faults: Illustration ▪ Consider the circuit alongside ▪ How many single stuck-at (0/1) faults are possible in this circuit? Answer: 18 VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Detecting a Fault: Test Vectors Test Vectors ▪ Any input pattern, or sequence of input patterns, that produces a different output response for a faulty circuit and a fault-free circuit Exhaustive Testing for functionality ▪ Exponential number of test vectors required (2𝑁 ) to test the functionality Single stuck-at fault model makes the number of fault linear in the number of circuit elements VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Design for Testability: Test Vectors Stuck-at 0 Stuck-at 1 A B C D Z A/0 B/0 C/0 D/0 Z/0 A/1 B/1 C/1 D/1 Z/ 1 0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 0 0 1 0 1 1 1 1 1 0 1 1 1 1 1 Test Vectors 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 0 1 0 0 1 1 1 1 1 0 1 1 1 1 1 ▪ 1111 (A/0, B/0, C/0, D/0, Z/1) 0 1 0 1 1 1 1 1 1 0 1 1 1 1 1 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 ▪ 0111 (A/1, Z/0) 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 ▪ 1011 (B/1, Z/0) 1 0 0 0 1 1 1 1 1 0 1 1 1 1 1 ▪ 1101 (C/1, Z/0) 1 0 0 1 1 1 1 1 1 0 1 1 1 1 1 ▪ 1110 (D/1, Z/0) 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑡𝑒𝑠𝑡 𝑣𝑒𝑐𝑡𝑜𝑟𝑠 = 𝑛 + 1 1 1 0 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 0 1 1VLSI Design 1 1Flow: 1RTL to0GDS 1 1NPTEL 2023 1 1 S. Saurabh 0 0 0 0 0 1 Combinational Circuit: Controllability and Observability ▪ If the NAND gate was lying too deep in a circuit, it is difficult to apply the required test vectors at the inputs Controllability: ability to set any desired value (0 or 1) on the internal signals of a circuit by applying an appropriate test-vector to the primary inputs. ▪ Similarly the output of NAND gate will be difficult to observe at any primary output if the NAND gate is lying too deep in circuit Observability: ability to examine any internal signal by propagating its value to a primary output by applying appropriate test vector to the primary inputs. VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Sequential Circuit: Controllability and Observability Problem of controllability ▪ Setting a particular value at any pin in a sequential circuit is more difficult Several cycles may be required to write a particular value State traversal required Finding such a test sequence is time consuming by sequential ATPG tool Problem of observability ▪ Similar difficulty in examining the value at a particular pin in the sequential circuit (requires state traversal) VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh  References ▪ M. Bushnell and V. Agrawal, “Essentials of electronic testing for digital, memory and mixed- signal VLSI circuits”, Springer Science & Business Media, 2004. ▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press, 2023. soprotection.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh VLSI DESIGN FLOW: RTL TO GDS Lecture 32 Scan Design Flow Sneh Saurabh Electronics and Communications Engineering IIIT Delhi Lecture Plan Scan Design Flow ▪ Design Modifications ▪ Mechanism of Testing ▪ Tasks VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Scan Design Flow: Design Modifications ▪ Extra primary ports added TM (Test Mode) SE (Scan Enable) SI (Scan In) SO (Scan Out) ▪ D flip-flops replaced with another memory elements (scan cells) ▪ Scan cells are reconnected to form shift register (scan chain) Effect ▪ Dramatically improve controllability and observability of memory elements (flip-flop) in a sequential circuit VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Scan Design Flow: Different Modes Design works in three modes: 1. Normal Mode: functional mode in which chip works 2. Shift Mode: Memory elements (i.e. scan cells) work as shift registers Test vectors are shifted-in and responses are shifted-out 3. Capture Mode: response of the fabricated circuit is captured during testing Mode TM SE Normal 0 0 Shift 1 1 Capture 1 0 VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Scan Cells ▪ Different kinds of scan cell can be ▪ The multiplexer selects data between D and SI used using the value at SE pin ▪ Most popular is MUXED-D Scan Cell ▪ In the normal/capture mode: SE=0 Value at D is latched ▪ In the shift mode, SE=1 Value at SI is latched Output pin produces the content of D flip-flop Next State could be of D-pin or SI-pin ▪ D, CLK, Q similar to D flip-flop ▪ SI ≡ scan input ▪ SE ≡ scan enable ▪ Q also works as SO≡ scan out VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Scan Design Flow: Forming Scan Chain (Example) ▪ The SI pin of the first scan cell is connected to the SI port ▪ Q/SO pin of one cell is connected to SI pin of the next cell to form a chain ▪ Q/SO pin of the last scan cell is connected to the SO port ▪ All SE pins of scan cells are connected to the SE port ▪ Form a scan chain consisting of 𝑁 scan cells ▪ Any test vector can be shifted-in from SI port in 𝑁 clock cycles ▪ Any test response can be shifted-out to SO port in 𝑁 clock cycles ▪ No changes made to the previous ▪ Without scan chain, it could take connections of D, Q and CLK pins exponential number of cycles VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Scan Design: Sequential to Combinational Circuit Testing ▪ Pins of a flip-flop becomes controllable/observable from primary input/output Q-pin can be treated as pseudo-primary input (PPI) D-pin can be treated as pseudo-primary output (PPO) Scan design eases of testing: ▪ Effectively transforms the problem of sequential circuit testing to combinational circuit testing ▪ Automatic test pattern generation (ATPG) problem effectively changes from sequential to combinational VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Scan Design Flow: Mechanism Shift Mode: set SE=1. ▪ Shift in the desired test vector using port SI to the scan cells F1, F2, F3. ▪ Apply the required test vector at input port also. Capture Mode: set SE=0 for 1 clock cycle. ▪ If there was a fault for which test vector was applied, scan cells will capture the result of fault and receive “fault” output Shift Mode: switch back to shift mode (SE=1) ▪ Shift out the captured result to the port SO. ▪ The result is compared with the expected response ▪ Simultaneously, apply next test vector at port SI and allow it to scan-in through the scan chain. VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Scan Design Flow: Tasks Design Preparation: Design becomes testable ▪ Guidelines that must be followed during designing such that scan design flow can be used effectively Scan Synthesis: Design becomes Scan Design ▪ Scan Configuration (During Synthesis) Decide number of scan chains, scan cells to be used, exclude certain elements from being converted to scan cells ▪ Scan Replacement (During Synthesis) Replace Flip-Flops with Scan Cells ▪ Scan Reordering and Stitching (During Physical Design) Reorder scan cells based on physical location so that routing becomes easier ▪ Test Vector Generation ▪ Scan Verification Scan Shift/Capture Operation using logic simulator Verify Timing (STA): Hold Violations VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Scan Design Flow: Cost ▪ Area Overhead: Scan Cell, Routing resource ▪ IO Pin Cost ▪ Performance degradation: added delay of multiplexor ▪ Design Effort Cost VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh  References ▪ M. Bushnell and V. Agrawal, “Essentials of electronic testing for digital, memory and mixed- signal VLSI circuits”, Springer Science & Business Media, 2004. ▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press, 2023. soprotection.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh  VLSI Design Flow: RTL To GDS (NPTEL Course) Tutorial 9 Objective: To gain a hands-on experience on Power Analysis using OpenSTA Requirements: OpenSTA: The installation and how to run OpenSTA is described in Tutorial 7. Please refer to it if you do not have OpenSTA installed on your machine. Files: o Design file: test.v o OpenSTA script file: test.tcl o SDC file: test.sdc o Technology library: toy.lib All the above files are available on the NPTEL website as study material for Week 9 Concepts: From Lecture 29 (Power Analysis): 2 𝑃𝑡𝑜𝑡 = 𝐶𝐿 𝑉𝐷𝐷 𝛼𝑓𝑐𝑙𝑘 + 𝑉𝐷𝐷 𝐼𝑆𝐶 + 𝑉𝐷𝐷 𝐼𝑙𝑒𝑎𝑘 where 𝑉𝐷𝐷 = supply voltage, 𝐶𝐿 = load capacitance,𝑓𝑐𝑙𝑘 = frequency of the clock in the circuit, 𝛼 = activity of the signal Energy dissipated in one cycle of 0→1→0 transition: 2 2 𝐸𝑑𝑦𝑛 = 𝐶𝑑 𝑉𝐷𝐷 + 𝑉𝐷𝐷 𝐼𝑆𝐶 𝜏𝑆𝐶 + (𝐶𝑤 + 𝐶𝐼 )𝑉𝐷𝐷 = 𝐸𝑖𝑛𝑡 + 𝐸𝑒𝑥𝑡 Non-linear Power Model (NLPM) Experiment: Run OpenSTA and examine how Power Analysis is done by the tool. Internal Power Computation: From toy.lib: Fall Transition: Rise Transition: From small.v and small.sdc: 1+2 Average energy consumed per transition= 2 = 1.5 𝑓𝐽 = 1.5 × 10−15 𝐽 Clock Period = 1000 ps 1 No. of clock cycles per second = = 109 1000×10−12 Activity = number of transitions per clock cycle=0.1 No. of transitions per second =0.1 × 109 Internal power =𝐸𝑛𝑒𝑟𝑔𝑦 𝑝𝑒𝑟 𝑡𝑟𝑎𝑛𝑠𝑖𝑡𝑖𝑜𝑛 × 𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑡𝑟𝑎𝑛𝑠𝑖𝑡𝑖𝑜𝑛 𝑝𝑒𝑟 𝑠𝑒𝑐𝑜𝑛𝑑 −15 = 1.5 × 10 × 0.1 × 109 = 1.5 × 10−7 𝑊 Switching Power Computation: Load = 𝐶 = 0.1𝑓𝑓 Voltage = 1 V 1 Energy dissipated in one transition = 𝐶𝑉 2 = 0.5 × 0.1 × 10−15 × 12 = 5 × 10−17 J 2 No. of transitions per second =0.1 × 109 Switching power= 𝐸𝑛𝑒𝑟𝑔𝑦 𝑝𝑒𝑟 𝑡𝑟𝑎𝑛𝑠𝑖𝑡𝑖𝑜𝑛 × 𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑡𝑟𝑎𝑛𝑠𝑖𝑡𝑖𝑜𝑛 𝑝𝑒𝑟 𝑠𝑒𝑐𝑜𝑛𝑑 = 5 × 10−17 × 0.1 × 109 = 5 × 10−9 𝑊 Leakage Power: From toy.lib 150 × 10−12 = 1.5 × 10−10 𝑊