VLSI Design Flow: RTL To GDS Lecture 25 Constraints I PDF

VLSI DESIGN FLOW: RTL TO GDS Lecture 25 Constraints I Sneh Saurabh Electronics and Communications Engineering IIIT Delhi Lecture...

VLSI DESIGN FLOW: RTL TO GDS Lecture 25 Constraints I Sneh Saurabh Electronics and Communications Engineering IIIT Delhi Lecture Plan ▪ Basics of constraints ▪ Clock constraints ▪ Input/Output constraints ▪ Timing exceptions VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Constraints: Basics Constraints are: create_clock -period 10 -waveform {5 10} ▪ Requirements of a design that needs to be [get_ports CLK] honoured or attempted to be honoured by the set_clock_transition -rise 0.1 [get_clocks CLK] CAD tools set_clock_uncertainty 0.2 [get_clocks CLK] ▪ Information about a design that could potentially be exploited by the CAD tools to set_input_delay -clock CLK 3.0 [get_ports improve the PPA of the design INPA] set_output_delay -clock CLK 3.0 [get_ports ▪ Constraints are normally specified in Synopsys INPA] Design Constraints (SDC) set_false_path –from [get_ports TE] ▪ ASCII format written in Tool Command Language (TCL) set_multicycle_path –from [get_ports mult_out] VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Constraints: Application ▪ Most of the constraints are related to timing of a design (also called timing constraints) Employed by implementation tool to gather information about the expected timing behavior Employed by STA tool to verify timing VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Constraints: What is the origin? Constraints are normally manually written ▪ Designer have the knowledge of design goals and environmental constraints ▪ There are certain tools for automatic constraints generation Some user intervention is always required It is important to write correct constraints ▪ Otherwise design implementation tools can produce unexpected results ▪ There should be consistency between different constraints ▪ Constraints should be consistent with design attributes VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Constraints: Types Clock signal ▪ Attributes of a clock signal such as frequency, duty cycle, skew, uncertainty and delay Environment under which the design operates ▪ Attributes of external incoming signal and expected behavior of the signals produced by a design Functionality of the design (informative) ▪ Timing exceptions (paths that are false and paths that are allowed to behave differently than traditional synchronous behavior), modes of design Design rules and optimization constraints ▪ Maximum slew at the port, maximum capacitance at a pin, and soft constraints VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh  Constraints Clock Signal VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Clock Constraints: Sources Two types of clock sources ▪ Primary clock sources: waveform independent of other clock sources in that design ▪ Derived clock sources: waveform depends on other clock sources ▪ Master clock: clock from which we derive another clock is known as the master clock of the derived clock CS1 is the master clock source of CS2 VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Primary Clock Source Definition create_clock: defines the primary clock source in a design current_design MyComp create_clock -name EXT_CLK -period 10 -waveform {0 4} [get_ports clk_in] create_clock -name INT_CLK -period 10 [get_pins CS1/clk_g] -waveform: time when the clock edges occur, starting from rise-edge VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Derived Clock Source Definition create_generated_clock: define derived clock sources create_clock -name CLK -period 10 [get_pins CS1/CLK] create_generated_clock -name GCLK -divide_by 2 –source [get_pins CS1/CLK] [get_pins CS2/GCLK] VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Attributes of Clock Signal: Latency set_clock_latency: specify clock latency create_clock -name CLK -period 200 [get_ports clk_port] set_clock_latency 5 -source [get_clocks CLK] set_clock_latency 10 [get_clocks CLK] VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Attributes of Clock Signal: Uncertainty set_clock_uncertainty: unpredictable deviation of the clock edges from the ideal value Clock uncertainty can be used to model: ▪ Jitter: temporal variation ▪ Skew: spatial variation ▪ Safety margins create_clock -name CLK -period 200 [get_ports clk_port] set_clock_uncertainty 15 -hold [get_clocks CLK] set_clock_uncertainty 20 -setup [get_clocks CLK] VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Attributes of Clock Signal: Transition set_clock_transition: specify an estimated clock transition time create_clock -name CLK -period 2000 [get_ports clk_port] set_clock_transition 10 [get_clocks CLK] VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh  References ▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press, 2023. ▪ Bhasker, Jayaram, and Rakesh Chadha. Static timing analysis for nanometer designs: A practical approach. Springer Science & Business Media, 2009. inprotected.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh VLSI DESIGN FLOW: RTL TO GDS Lecture 26 Constraints II Sneh Saurabh Electronics and Communications Engineering IIIT Delhi  Constraints Environment VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Static Timing Analysis: Environment of design Environment of design puts additional constraints on the signal entering/leaving a design ▪ Signal entering the design at the input port encounters delay ▪ Signal leaving the design at the output port will encounter delay and get captured externally Should meet setup/hold requirements at FOUT Check for setup/hold must also be performed at the output port VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Input Port Constraints: set_input_delay ▪ Signal gets delayed before entering the design Lesser part of clock-period is available for the signal to reach flip-flop within the design ▪ Delay external to design at the input ports is modelled using set_input_delay ▪ Value of input delay = Delay of 𝐶𝐸1 + CP → Q delay of 𝐹𝐼𝑁 + Delay of 𝐷𝐼𝑁 create_clock –name CLK –period 2000 [get_ports CLK_PORT] set_input_delay –clock [get_clocks CLK] 100 [get_ports IN] VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Transition at Input Port ▪ set_input_transition: model slew of ▪ set_driving_cell : driver of inputs incoming signal set_driving_cell -lib_cell BUF1X -library tech14nm set_input_transition 10 -max -rise [get_ports IN] [get_ports IN] VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Output Port Constraints: set_output_delay Output Delay: signal leaving a design must meet the setup/hold constraints of the flip-flop that captures that signal ▪ Constraints of the external flip-flop is modelled using set_output_delay ▪ The delay of OD needs to be chosen such that the setup/hold requirements in the actual circuit and equivalent circuit match ▪ Delay of OD is specified in set_output_delay command VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Illustration: set_output_delay 𝑇𝑖𝑛𝑡 + 400 < 𝑇𝑐𝑙𝑘 + 20 − 30 𝑇𝑖𝑛𝑡 + 𝑇𝑂𝐷 < 𝑇𝑐𝑙𝑘 𝑇𝑂𝐷 = 400 − 20 + 30 = 410 create_clock -name SYS_CLOCK -period 2000 [get_ports CLK] set_output_delay 410 -max -clock [get_clocks SYS_CLK] [get_ports OUT] VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Load at Output Port ▪ set_load: load that will be driven by the output port set_load 0.039 [get_ports OUT] VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh  Constraints Functionality VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Timing Exceptions ▪ set_false_path: To make exceptions from analysing certain paths that may not be exercised ▪ set_multicycle_path: To inform the STA tool that certain path may take more than one cycle set_multicycle_path 4 -setup -from [get_pins FF1/CP] -to [get_pins FF2/D] set_multicycle_path 4 -setup -from [get_pins FF1/CP] -to [get_pins FF2/D] set_multicycle_path 3 -hold -from [get_pins FF1/CP] -to [get_pins FF2/D] VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Constant Value to Port/Pin ▪ set_case_analysis: assign constant value to some port/pin set_case_analysis 1 [get_ports SCAN_ENABLE] set_case_analysis 1 [get_ports SLEEP_MODE] VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh  References ▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press, 2023. ▪ Bhasker, Jayaram, and Rakesh Chadha. Static timing analysis for nanometer designs: A practical approach. Springer Science & Business Media, 2009. soprotection.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh VLSI DESIGN FLOW: RTL TO GDS Lecture 27 Technology Mapping Sneh Saurabh Electronics and Communications Engineering IIIT Delhi Lecture Plan ▪ Technology Mapping VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Technology Mapping: Framework Technology Libraries ▪ Cells with different logic functions ▪ Cells with same function, but of different sizes Unmapped Netlist: ▪ Netlist of generic logic gates Constraints: Mapped Netlist: ▪ Synopsys Design Constraint (SDC) file ▪ Netlist consisting of library cells ▪ Objectives: ▪ Functionally equivalent to unmapped Minimize area under a given delay netlist constraint Minimize delay under a given area constraint VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Illustration of Mapping: Given Problem Logic Function: ′ ▪ 𝑌 = 𝐴. 𝐵 + 𝐶 VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Illustration of Mapping: Solution 1 Given: 𝑌 = 𝐴. 𝐵 + 𝐶 ′ Logic Function: ′ 𝑌 = ( 𝐴. 𝐵 ′. 𝐶′)′ = 𝐴. 𝐵 ′. 𝐶 ′ = 𝐴. 𝐵 + 𝐶 ′ VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Illustration of Mapping: Solution 2 Given: 𝑌 = 𝐴. 𝐵 + 𝐶 ′ Logic Function: 𝑌 = 𝐴. 𝐵 ′. 𝐶′ = 𝐴. 𝐵 + 𝐶 ′ VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Illustration of Mapping: Solution 3 Given: 𝑌 = 𝐴. 𝐵 + 𝐶 ′ Logic Function: ′ 𝑌 = ( 𝐴. 𝐵 ′. 𝐶′)′ VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Summary of Solutions Area Delay Power Comments Solution 1 10 20 50 Minimum Area Solution 2 13 17 55 Minimum Delay Solution 3 12 28 22 Minimum Power VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Technology Mapping: Approaches Two approaches: ▪ Structural Mapping ▪ Boolean Mapping VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh  References ▪ G. D. Micheli. “Synthesis and Optimization of Digital Circuits”. McGraw-Hill Higher Education, 1994. ▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press, 2023. inprotected.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh VLSI DESIGN FLOW: RTL TO GDS Lecture 28 Timing-driven Optimizations Sneh Saurabh Electronics and Communications Engineering IIIT Delhi Lecture Plan ▪ Timing-driven Optimizations VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Timing-driven Optimization: Flow VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Timing Driven Optimization: Resizing ▪ Libraries contain cells of same functionality Resizing: and different sizes ▪ Replace a cell C1 with another cell C2 Size of the cell increases, delay that produces the same Boolean function decreases but has a different size Example: cell C1 replaced with a functionally equivalent cell C2 of a larger size Effects: 1. Delay and output slew of C2 can reduce Delay of cells in the fanout of C2 can also reduce 2. Delay and output slew of the driver of C2 can increase Delay of the cells in its fanout, including that of C2, can increase VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Timing Driven Optimization: Restructure (1) Rewiring: ▪ Timing critical signals are moved closer to the sink in a cone of logic to reduce the overall path delay VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Timing Driven Optimization: Restructure (2) Shannon Expansion ▪ 𝐹0 = 𝐹(0, 𝑥1 , 𝑥2 , … , 𝑥𝑁 ) ▪ 𝐹1 = 𝐹(1, 𝑥1 , 𝑥2 , … , 𝑥𝑁 ) 𝑌 = 𝐹(𝑥0 , 𝑥1 , 𝑥2 , … , 𝑥𝑁 ) ▪ Let 𝑥0 be the signal that arrives last (AT of 𝑥0 is greatest) and is on the critical path ▪ How to restructure the circuit such that the worst delay of the circuit improves? VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Restructure: Illustration Arrival Time: 145 ps 𝑍 = 𝐹 𝐴, 𝐵, 𝐶 = 𝐴𝐵 + 𝐶 Arrival Time: 130 ps 𝐹𝐵=0 = 𝐶 𝐹𝐵=1 = 𝐴 + 𝐶 VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Fanout Optimization Fanout optimization: inserting buffers in a high-fanout VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Retiming Retiming: balance the amount of logic between registers VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh  References ▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press, 2023. inprotected.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh  VLSI Design Flow: RTL To GDS (NPTEL Course) Solution of numerical problem for Week 8 8. Consider the following synchronous circuit. The following attributes are valid for the flip-flops FF1 and FF2: setup time=45 ps, hold time=10 ps, and CLK-to-Q delay=20 ps. The delay of each inverter is 50 ps. Ignore the wire delay. Assume that we have define the following constraints in the SDC file (all time units are in picoseconds): create_clock -name CLK -period 1000 [get_ports CLK] set_input_delay -clock [get_clocks CLK] 150 [get_ports A] set_output_delay -clock [get_clocks CLK] 125 [get_ports Z] What is the setup slack at the timing end-point FF1/D? a. 755 ps b. 700 ps c. 850 ps d. 905 ps Solution: Clock period = 1000 ps [from the command create_clock] Arrival time at FF1/D=150 [i.e., from set_input_delay command] + 50 [i.e., delay of inverter G1] = 200 ps Required time = Clock period – setup time of FF1 = 1000 – 45 ps = 955 ps Setup slack = Required time – Arrival time = 955 -200 = 755 ps Hence, option (a) 755 ps is correct. 9. For the question above, what is the hold slack at the timing end-point FF1/D? a. 200 ps b. 190 ps c. 0 ps d. -190 ps Solution: Arrival time at FF1/D=150 [i.e., from set_input_delay command] + 50 [i.e., delay of inverter G1] = 200 ps Required time = hold time of FF1 = 10 ps  Hold slack = Arrival time - Required time = 200-10 = 190 ps Hence, option (b) 190 ps is correct. 10. For the question above, what is the setup slack at the timing end-point port Z? a. 800 ps b. 900 ps c. 805 ps d. 905 ps Solution: Clock period = 1000 ps [from the command create_clock] Arrival time at Z = 20 [i.e., CLK-to-Q delay] + 50 [i.e., delay of inverter G3] = 70 ps Required time at Z = Clock period – output-delay specified at Z = 1000 – 125 ps = 875 ps Setup slack = Required time – Arrival time = 875 - 70 = 805 ps Hence, option (c) 805 ps is correct.