VLSI Design Flow: RTL to GDS PDF Lecture 15

VLSI DESIGN FLOW: RTL TO GDS Lecture 15 Logic Optimization: Part II Sneh Saurabh Electronics and Communications Engineering...

VLSI DESIGN FLOW: RTL TO GDS Lecture 15 Logic Optimization: Part II Sneh Saurabh Electronics and Communications Engineering IIIT Delhi Lecture Plan ▪ Multilevel Logic Optimization VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Multilevel Logic Optimization VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Multilevel Logic Optimization: Introduction Multilevel Logic: more than two levels of logic ▪ Can appear naturally in RTL Limitations of two-level logic ▪ Sum of Product (SOP) representations of some functions can become too big Example: parity functions, adders, and multipliers. ▪ Cannot reduce area by trading off speed Multilevel logic circuits offer more flexibility in exploring area–delay trade-off Multilevel Logic Representations ▪ Factored Form ▪ Boolean Logic Network VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Factored Form A factored form consists of: A factored form is an SOP, of SOP, of SOP, a) literals …, of arbitrary depth. b) sum (logical OR) of factored form c) product (logical AND) of factored form. ▪ Given an SOP, it can be converted to a factored form by factoring ▪ Consider the following Boolean function in the SOP form: 𝑎𝑐 + 𝑎𝑑 + 𝑏𝑐 + 𝑏𝑑 + 𝑐𝑒 ▪ Factoring can convert a two-level representation to a multilevel ▪ We can obtain a factored form representation. representation as: (𝑎 + 𝑏)(𝑐 + 𝑑) + 𝑐𝑒 ▪ Given an SOP, its factored form is not (𝑎 + 𝑏)𝑑 + (𝑎 + 𝑏 + 𝑒)𝑐 unique ▪ Number of literals in the factored form correlates with the circuit area VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Boolean Logic Network (1) ▪ Boolean logic network is a directed acyclic graph annotate each vertex with a single-output local Boolean function ▪ It can conveniently represent multilevel logic circuit with more than one output. ▪ Consider the following set of equations: 𝑝 = 𝑎 + 𝑏 𝑞 = 𝑒𝑓 𝑟 = 𝑝 + 𝑐′𝑑 + 𝑞 𝑠 = 𝑑′ + 𝑞′ 𝑥 = 𝑟 𝑦 = 𝑠 ▪ Assume that inputs are 𝑎, 𝑏, 𝑐, 𝑑, 𝑒, and 𝑓. ▪ Assume that 𝑥 and 𝑦 are outputs ▪ The incoming edges to a vertex denote the variables on which the local function at that vertex depends VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Boolean Logic Network (2) Flexibility of Boolean logic network: ▪ Local functions in a Boolean logic network can be arbitrarily complicated ▪ Both its underlying graph and the local functions can be manipulated during optimization ▪ Optimization can explore both the behavioral and the structural features of the implementation Estimating Area and Delay: ▪ Local functions restricted to be in an SOP form and made minimal with respect to single- implicant containment ▪ Estimating area: sum of all the literal counts of the local functions ▪ Estimating delay: number of stages of vertices in the logic network VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Multilevel Logic Optimization Transformations VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Transformations ▪ Multilevel logic optimization is performed by applying transformations. These transformations can be viewed as operators for the Boolean logic network. ▪ These operators applied iteratively until no more improvement in some QoR measures is possible. The final QoR depends on the order of operation and is hard to predict. VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Eliminate ▪ It removes a vertex from the graph and replaces all its occurrences in the network with the corresponding local function ▪ We carry out eliminate in the hope that subsequent transformations can reduce the cost (area) VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Simplify ▪ It simplifies the associated local SOP expression to reduce the literal count (two-level logic optimization carried out on each local function individually) ▪ Reduces the literal count from 8 to 4 VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Substitute ▪ It replaces the local function with a simpler SOP by creating new dependencies and possibly removing other dependencies. ▪ Creates dependencies by searching for an appropriate match. It adds more structural information to the network. ▪ Reduces the literal count from 7 to 5 ▪ Substitute operator needs to find whether local function 𝑓𝑖 divides another local function 𝑓𝑗 If it divides, we can replace 𝑓𝑗 = 𝑄. 𝑓𝑖 + 𝑅 Need to perform division efficiently VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Extract ▪ It finds a common subexpression for functions associated with two or more vertices. Subsequently, it creates a new vertex associated with the subexpression. Then replaces the common subexpressions in the original functions with the variable of the new vertex. ▪ Reduces the literal count from 14 to 10 ▪ Extract operator needs to find divisors for the local functions and then search vertices with matching divisors. Implementing extract operator is computationally challenging VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Challenges of Multilevel Logic Optimization ▪ Huge search space for optimization Division Operation: ▪ During multilevel logic optimization, we need to carry out division too many times. ▪ Practical circuits have thousands of vertices in the Boolean logic network. Might need to divide each vertex with the rest [𝑂(𝑛2 ) times, where 𝑛 is the number of vertices in the Boolean logic network] ▪ Efficiency of division of expressions is critical for multilevel logic optimization Divisors: ▪ Need to find good divisors (one that can reduce cost) for Boolean expressions ▪ Finding a good set of divisors for a given Boolean expression is nontrivial VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Algebraic Model Algebraic Model: ▪ Neglecting some Boolean properties of the local functions ▪ Simplified model treats the local Boolean functions as polynomials and employs rules of polynomial algebra Treat a variable and its complement as separate variables. Applications of algebraic model: ▪ Efficient algorithms can be designed to carry out division in the algebraic model (rather than in the Boolean model) ▪ Good divisors or common subexpressions in a complex Boolean logic network can be determined efficiently in a complex Boolean logic network By intelligently pruning the search space (applying properties of algebraic models) VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Algebraic Model versus Boolean Model ▪ Algebraic model (and associated mathematics) form the basis of fast multilevel optimization in the contemporary logic optimization tools. Boolean Model: ▪ An algebraic model is weaker than a Boolean model for optimization Cannot fully optimize a Boolean logic network. ▪ Post algebraic model-based optimization, transformations that utilize the power of the Boolean model is applied VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Multilevel Logic Optimization Boolean Model VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Don’t Care (DC) Conditions ▪ Don’t Care (DC) conditions arise naturally in Boolean logic network Due to the graph structure and dependencies among local functions. ▪ DCs are a rich source of optimization in multilevel logic synthesis Simplifying local functions and improving the circuit’s overall QoR. ▪ A logic synthesis tool needs to discover them using Boolean algebra (in contrast to given DCs) There are two types of DC that are useful in simplifying local functions in a Boolean logic network: 1. Controllability Don’t Cares (CDCs) 2. Observability Don’t Cares (ODCs). VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Controllability Don’t Cares (CDCs) ▪ The combination of input variables that can never occur at a given vertex in a Boolean logic network produces CDCs. ▪ Local functions can be simplified by accounting for CDCs and two-level logic minimizers ▪ At the input of vertex 𝑞, 𝑝 = 1 and 𝑏 = 0 can never occur ▪ 𝑝𝑏′ can be treated as CDC ▪ Cover is: 𝑞 = 𝑝 + 𝑏𝑐 ▪ Reduces the literal count by 1 Cover is: 𝑞 = 𝑝𝑏 + 𝑏𝑐 VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Satisfiability Don’t Cares (SDCs) ▪ CDCs can be computed using efficient algorithms by exploiting Satisfiability Don’t Cares (SDCs). ▪ SDCs get enforced by the local functions associated with a vertex at its output. Consider the vertex 𝑝 = 𝑎𝑏 ▪ The following function will never evaluate to 1: 𝑝 ⊕ 𝑎𝑏 = 𝑝𝑎′ + 𝑝𝑏′ + 𝑝′𝑎𝑏 ▪ Hence, the combination of values that make the above function 1 can never occur in the network: 𝑝 = 1, 𝑎 = 0, 𝑝 = 1, 𝑏 = 0, 𝑝 = 0, 𝑎 = 1, 𝑏 = 1 ▪ These values can be treated as DCs for the Boolean logic network ▪ Logic synthesis tools typically derive CDCs algorithmically using SDCs. ▪ Subsequently, the CDCs get utilized in simplifying local functions. VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Observability Don’t Cares (ODCs) ▪ The ODCs are input variable combinations that obstruct the vertex output from being observed at the network output. ▪ We derive ODCs induced by vertices in the fanout of a given vertex. ▪ If 𝑐 = 0, then 𝑥 = 0 irrespective of 𝑝 ▪ 𝑐 = 0, can be treated as ODC for 𝑝 Cover is: ▪ Cover is: 𝑝 = 𝑎 + 𝑏 𝑝 = 𝑎𝑏 + 𝑏𝑐 + 𝑎𝑐 ▪ Literal count reduces from 9 to 5 VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh  References ▪ G. D. Micheli. “Synthesis and Optimization of Digital Circuits”. McGraw-Hill Higher Education, 1994. ▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press, 2023. inprotected.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh