TPS51200 Sink and Source DDR Termination Regulator (PDF)

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Product Order Technical Tools & Support & Reference Folder Now Documents Software Community Design TPS51200 SLUS812D – FEBRUARY 2008 – REVISED FEBRUARY 2020 TPS51200 Sink and Source DDR Termination Regulator 1 Features 3 Description 1 Input Voltage: Supports 2.5-V Rail and 3.3-V Rail The TPS51200 device is a sink and source double data rate (DDR) termination regulator specifically VLDOIN Voltage Range: 1.1 V to 3.5 V designed for low input voltage, low-cost, low-noise Sink and Source Termination Regulator Includes systems where space is a key consideration. Droop Compensation The TPS51200 maintains a fast transient response Requires Minimum Output Capacitance of 20-μF and requires a minimum output capacitance of only (Typically 3 × 10-μF MLCCs) for Memory 20 μF. The TPS51200 supports a remote sensing Termination Applications (DDR) function and all power requirements for DDR, DDR2, PGOOD to Monitor Output Regulation DDR3, DDR3L, Low-Power DDR3 and DDR4 VTT bus termination. EN Input REFIN Input Allows for Flexible Input Tracking In addition, the TPS51200 provides an open-drain Either Directly or Through Resistor Divider PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT Remote Sensing (VOSNS) during S3 (suspend to RAM) for DDR applications. ±10-mA Buffered Reference (REFOUT) The TPS51200 is available in the thermally efficient Built-in Soft Start, UVLO, and OCL 10-pin VSON thermal pad package, and is rated both Thermal Shutdown Green and Pb-free. It is specified from –40°C to Supports DDR, DDR2, DDR3, DDR3L, Low- +85°C. Power DDR3, and DDR4 VTT Applications Device Information(1) 10-Pin VSON Package With Thermal Pad PART NUMBER PACKAGE BODY SIZE (NOM) TPS51200 VSON (10) 3.00 mm × 3.00 mm 2 Applications (1) For all available packages, see the orderable addendum at Memory Termination Regulator for DDR, DDR2, the end of the data sheet. DDR3, DDR3L, Low-Power DDR3 and DDR4 Notebooks, Desktops, and Servers Telecom and Datacom Base Stations LCD-TVs and PDP-TVs Copiers and Printers Set-Top Boxes Simplified DDR Application VDDQ 1 REFIN VIN 10 3.3 VIN TPS51200 VLDOIN 2 VLDOIN PGOOD 9 PGOOD VTT 3 VO GND 8 4 PGND EN 7 SLP_S3 5 VOSNS REFOUT 6 VTTREF Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS51200 SLUS812D – FEBRUARY 2008 – REVISED FEBRUARY 2020 www.ti.com Table of Contents 1 Features.................................................................. 1 8 Application and Implementation........................ 18 2 Applications........................................................... 1 8.1 Application Information............................................ 18 3 Description............................................................. 1 8.2 Typical Application................................................. 18 4 Revision History..................................................... 2 8.3 System Examples................................................... 21 5 Pin Configuration and Functions......................... 4 9 Power Supply Recommendations...................... 27 6 Specifications......................................................... 5 10 Layout................................................................... 27 6.1 Absolute Maximum Ratings...................................... 5 10.1 Layout Guidelines................................................. 27 6.2 ESD Ratings.............................................................. 5 10.2 Layout Example.................................................... 28 6.3 Recommended Operating Conditions....................... 5 10.3 Thermal Design Considerations............................ 28 6.4 Thermal Information.................................................. 5 11 Device and Documentation Support................. 30 6.5 Electrical Characteristics........................................... 6 11.1 Device Support...................................................... 30 6.6 Typical Characteristics.............................................. 8 11.2 Documentation Support....................................... 30 7 Detailed Description............................................ 11 11.3 Community Resources.......................................... 30 7.1 Overview................................................................. 11 11.4 Trademarks........................................................... 30 7.2 Functional Block Diagram....................................... 11 11.5 Electrostatic Discharge Caution............................ 30 7.3 Feature Description................................................. 11 11.6 Glossary................................................................ 30 7.4 Device Functional Modes........................................ 17 12 Mechanical, Packaging, and Orderable Information........................................................... 30 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (November 2016) to Revision D Page Added "keep total REFOUT capacitance below 0.47 μF" in Pin Functions table................................................................. 4 Changes from Revision B (September 2016) to Revision C Page Added references to DDR3L DRAM technology throughout.................................................................................................. 1 Added DDR3L test conditions to Output DC voltage, VO and REFOUT specification.......................................................... 6 Added Figure 4....................................................................................................................................................................... 8 Added Figure 9....................................................................................................................................................................... 9 Updated Figure 16 to include DDR3L data.......................................................................................................................... 10 Changes from Revision A (September 2015) to Revision B Page Changed " –10 mA < IREFOUT < 10 mA" to "–1 mA < IREFOUT < 1 mA" in all test conditions for the REFOUT voltage tolerance to VREFIN specification............................................................................................................................................. 7 Changed all MIN and MAX values from "15" to "12" for all test conditions for the REFOUT voltage tolerance to VREFIN specification................................................................................................................................................................. 7 Updated Figure 19............................................................................................................................................................... 12 Added REFOUT (VREF) Consideration for DDR2 Applications section................................................................................. 16 Updated Figure 28 and Table 3............................................................................................................................................ 21 Added clarity to Layout Guidelines section.......................................................................................................................... 27 Changes from Original (February 2008) to Revision A Page Added Pin Configuration and Functions section, ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section............................... 1 Changed “PowerPAD” references to “thermal pad” throughout............................................................................................. 4 2 Submit Documentation Feedback Copyright © 2008–2020, Texas Instruments Incorporated Product Folder Links: TPS51200  TPS51200 www.ti.com SLUS812D – FEBRUARY 2008 – REVISED FEBRUARY 2020 Deleted Dissipation Ratings table.......................................................................................................................................... 5 Copyright © 2008–2020, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS51200 TPS51200 SLUS812D – FEBRUARY 2008 – REVISED FEBRUARY 2020 www.ti.com 5 Pin Configuration and Functions DRC Package 10-Pin VSON Top View REFIN 1 10 VIN VLDOIN 2 9 PGOOD VO 3 8 GND PGND 4 7 EN Thermal Pad VOSNS 5 6 REFOUT Pin Functions PIN I/O (1) DESCRIPTION NAME NO. For DDR VTT application, connect EN to SLP_S3. For any other application, use the EN pin as the ON/OFF EN 7 I function. GND 8 G Signal ground. PGND (2) 4 G Power ground for the LDO. PGOOD 9 O Open-drain, power-good indicator. REFIN 1 I Reference input. Reference output. Connect to GND through 0.1-μF ceramic capacitor. If there is a REFOUT capacitors at DDR REFOUT 6 O side, keep total capacitance on REFOUT pin below 0.47 μF. The REFOUT pin can not be open. VIN 10 I 2.5-V or 3.3-V power supply. A ceramic decoupling capacitor with a value between 1-μF and 4.7-μF is required. VLDOIN 2 I Supply voltage for the LDO. VO 3 O Power output for the LDO. VOSNS 5 I Voltage sense input for the LDO. Connect to positive terminal of the output capacitor or the load. (1) I = Input, O = Output , G = Ground (2) Thermal pad connection. See Figure 35 in the Thermal Design Considerations section for additional information. 4 Submit Documentation Feedback Copyright © 2008–2020, Texas Instruments Incorporated Product Folder Links: TPS51200  TPS51200 www.ti.com SLUS812D – FEBRUARY 2008 – REVISED FEBRUARY 2020 6 Specifications 6.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT REFIN, VIN, VLDOIN, VOSNS –0.3 3.6 Input voltage (2) EN –0.3 6.5 V PGND to GND –0.3 0.3 REFOUT, VO –0.3 3.6 Output voltage (2) V PGOOD –0.3 6.5 Operating junction temperature, TJ –40 150 °C Storage temperature, Tstg –55 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to the network ground terminal unless otherwise noted. 6.2 ESD Ratings VALUE UNIT (1) Electrostatic Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2000 V(ESD) V discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Supply voltages VIN 2.375 3.500 V EN, VLDOIN, VOSNS –0.1 3.5 REFIN 0.5 1.8 Voltage PGOOD, VO –0.1 3.5 V REFOUT –0.1 1.8 PGND –0.1 0.1 Operating free-air temperature, TA –40 85 °C 6.4 Thermal Information TPS51200 THERMAL METRIC (1) DRC (VSON) UNIT 10 PINS RθJA Junction-to-ambient thermal resistance 55.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 84.6 °C/W RθJB Junction-to-board thermal resistance 30.0 °C/W ψJT Junction-to-top characterization parameter 5.5 °C/W ψJB Junction-to-board characterization parameter 30.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 10.9 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Copyright © 2008–2020, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TPS51200 TPS51200 SLUS812D – FEBRUARY 2008 – REVISED FEBRUARY 2020 www.ti.com 6.5 Electrical Characteristics Over recommended free-air temperature range, VVIN = 3.3 V, VVLDOIN = 1.8 V, VREFIN = 0.9 V, VVOSNS = 0.9 V, VEN = VVIN, COUT = 3 × 10 μF and circuit shown in Figure 24. (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT IIN Supply current TA = 25 °C, VEN = 3.3 V, No Load 0.7 1 mA TA = 25 °C, VEN = 0 V, VREFIN = 0, 65 80 No Load IIN(SDN) Shutdown current μA TA = 25 °C, VEN = 0 V, VREFIN > 0.4 V, No 200 400 Load ILDOIN Supply current of VLDOIN TA = 25 °C, VEN = 3.3 V, No Load 1 50 μA ILDOIN(SDN) Shutdown current of VLDOIN TA = 25 °C, VEN = 0 V, No Load 0.1 50 μA INPUT CURRENT IREFIN Input current, REFIN VEN = 3.3 V 1 μA VO OUTPUT 1.25 V VREFOUT = 1.25 V (DDR1), IO = 0 A –15 15 mV 0.9 V VREFOUT = 0.9 V (DDR2), IO = 0 A –15 15 mV 0.75 V VVOSNS Output DC voltage, VO VREFOUT = 0.75 V (DDR3), IO = 0 A –15 15 mV 0.675 V VREFOUT = 0.675 V (DDR3L), IO = 0 A –15 15 mV 0.6 V VREFOUT = 0.6 V (DDR4), IO = 0 A –15 15 mV VVOTOL Output voltage tolerance to REFOUT –2 A < IVO < 2 A –25 25 mV With reference to REFOUT, IVOSRCL VO source current Limit 3 4.5 A VOSNS = 90% × VREFOUT With reference to REFOUT, IVOSNCL VO sink current Limit 3.5 5.5 A VOSNS = 110% × VREFOUT VREFIN = 0 V, VVO = 0.3 V, VEN = 0 V, TA IDSCHRG Discharge current, VO 18 25 Ω = 25°C POWERGOOD COMPARATOR PGOOD window lower threshold with –23.5% –20% –17.5% respect to REFOUT VTH(PG) VO PGOOD threshold PGOOD window upper threshold with 17.5% 20% 23.5% respect to REFOUT PGOOD hysteresis 5% Start-up rising edge, VOSNS within 15% tPGSTUPDLY PGOOD start-up delay 2 ms of REFOUT VPGOODLOW Output low voltage ISINK = 4 mA 0.4 V VOSNS is outside of the ±20% PGOOD tPBADDLY PGOOD bad delay 10 μs window VOSNS = VREFIN (PGOOD high IPGOODLK Leakage current (1) 1 μA impedance), VPGOOD = VVIN + 0.2 V REFIN AND REFOUT VREFIN REFIN voltage range 0.5 1.8 V VREFINUVLO REFIN undervoltage lockout REFIN rising 360 390 420 mV REFIN undervoltage lockout VREFINUVHYS 20 mV hysteresis VREFOUT REFOUT voltage REFIN V (1) Ensured by design. Not production tested. 6 Submit Documentation Feedback Copyright © 2008–2020, Texas Instruments Incorporated Product Folder Links: TPS51200  TPS51200 www.ti.com SLUS812D – FEBRUARY 2008 – REVISED FEBRUARY 2020 Electrical Characteristics (continued) Over recommended free-air temperature range, VVIN = 3.3 V, VVLDOIN = 1.8 V, VREFIN = 0.9 V, VVOSNS = 0.9 V, VEN = VVIN, COUT = 3 × 10 μF and circuit shown in Figure 24. (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT –1 mA < IREFOUT < 1 mA, –12 12 VREFIN = 1.25 V –1 mA < IREFOUT < 1 mA, –12 12 VREFIN = 0.9 V –1 mA < IREFOUT < 1 mA, VREFOUTTOL REFOUT voltage tolerance to VREFIN –12 12 mV VREFIN = 0.75 V –1 mA < IREFOUT < 1 mA, –12 12 VREFIN = 0.675 V –1 mA < IREFOUT < 1 mA, –12 12 VREFIN = 0.6 V IREFOUTSRCL REFOUT source current limit VREFOUT = 0 V 10 40 mA IREFOUTSNCL REFOUT sink current limit VREFOUT = 0 V 10 40 mA UVLO AND EN LOGIC THRESHOLD Wake up, TA = 25°C 2.2 2.3 2.375 V VVINUVVIN UVLO threshold Hysteresis 50 mV VENIH High-level input voltage Enable 1.7 VENIL Low-level input voltage Enable 0.3 V VENYST Hysteresis voltage Enable 0.5 IENLEAK Logic input leakage current EN, TA = 25°C –1 1 μA THERMAL SHUTDOWN Shutdown temperature 150 TSON Thermal shutdown threshold (1) °C Hysteresis 25 Copyright © 2008–2020, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TPS51200 TPS51200 SLUS812D – FEBRUARY 2008 – REVISED FEBRUARY 2020 www.ti.com 6.6 Typical Characteristics 3 × 10-µF MLCCs (0805) are used on the output 1.3 940 TA TA ± 40°C ± 40°C 1.28 930 0°C 0°C 25°C 25°C 920 Output Voltage (mV) Output Voltage (V) 1.26 85°C 85°C 910 1.24 900 1.22 890 1.2 880 1.18 870 ±3 ±2 ±1 0 1 2 3 ±3 ±2 ±1 0 1 2 3 Output Current (A) Output Current (A) VVIN = 3.3 V DDR VVIN = 3.3 V DDR2 Figure 1. Load Regulation Figure 2. Load Regulation 790 720 TA TA 780 ± 40°C 710 ±40°C 0°C 0°C 770 700 25°C 25°C Output Voltage (mV) Output Voltage (mV) 85°C 760 85°C 690 750 680 740 670 730 660 720 710 650 700 640 ±3 ±2 ±1 0 1 2 3 ±3 ±2 ±1 0 1 2 3 Output Current (A) Output Current (A) VVIN = 3.3 V DDR3L VVIN = 3.3 V DDR3 Figure 4. Load Regulation Figure 3. Load Regulation 670 1.3 TA ± 40°C 1.25 650 0°C 25°C 1.2 Output Voltage (mV) Output Voltage (V) 630 85°C 1.15 610 1.1 1.05 590 TA 1 ± 40°C 570 0°C 0.95 25°C 85°C 550 0.9 ±3 ±2 ±1 0 1 2 3 ±3 ±2 ±1 0 1 2 3 Output Current (A) Output Current (A) VVIN = 3.3 V LP DDR3 or DDR4 VVIN = 2.5 V DDR Figure 5. Load Regulation Figure 6. Load Regulation 8 Submit Documentation Feedback Copyright © 2008–2020, Texas Instruments Incorporated Product Folder Links: TPS51200  TPS51200 www.ti.com SLUS812D – FEBRUARY 2008 – REVISED FEBRUARY 2020 Typical Characteristics (continued) 3 × 10-µF MLCCs (0805) are used on the output 1 800 TA ± 40°C 0.95 825 0°C 25°C Output Voltage (mV) Output Voltage (V) 0.9 750 85°C 0.85 725 0.8 TA 700 ± 40°C 0.75 0°C 675 25°C 85°C 0.8 650 ±3 ±2 ±1 0 1 2 3 ±3 ±2 ±1 0 1 2 3 Output Current (A) Output Current (A) VVIN = 2.5 V DDR2 VVIN = 2.5 V DDR3 Figure 7. Load Regulation Figure 8. Load Regulation 720 750 TA TA 710 ±40°C ± 40°C 700 0°C 700 0°C 25°C 25°C Output Voltage (mV) Output Voltage (mV) 690 85°C 85°C 680 650 670 660 600 650 640 550 630 620 500 ±3 ±2 ±1 0 1 2 3 ±3 ±2 ±1 0 1 2 3 Output Current (A) Output Current (A) VVIN = 2.5 V DDR3L VVIN = 2.5 V LP DDR3 or DDR4 Figure 9. Load Regulation Figure 10. Load Regulation 1.255 905 TA TA 1.254 ± 40°C 904 ± 40°C 25°C 25°C 1.253 85°C 903 85°C Output Voltage (mV) Output Voltage (V) 1.252 902 1.251 901 1.25 900 1.249 899 1.248 898 1.247 897 ±15 ±10 ±5 0 5 10 15 ±15 ±10 ±5 0 5 10 15 REFOUT Output Current (mA) REFOUT Output Current (mA) DDR DDR2 Figure 11. REFOUT Load Regulation Figure 12. REFOUT Load Regulation Copyright © 2008–2020, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: TPS51200 TPS51200 SLUS812D – FEBRUARY 2008 – REVISED FEBRUARY 2020 www.ti.com Typical Characteristics (continued) 3 × 10-µF MLCCs (0805) are used on the output 755 680 TA TA 754 ± 40°C 679 ±40°C 25°C 25°C 753 85°C 678 85°C Output Voltage (mV) Output Voltage (mV) 752 677 751 676 750 675 749 674 748 673 747 672 -15 -10 -5 0 5 10 15 ±15 ±10 ±5 0 5 10 15 REFOUT Output Current (mA) REFOUT Output Current (mA) DDR3L DDR3 Figure 14. REFOUT Load Regulation Figure 13. REFOUT Load Regulation 605 1.4 TA 604 ± 40°C 1.2 25°C 603 DROPOUT Voltage (V) 85°C 1 Output Voltage (mV) 602 0.8 601 0.6 600 0.4 VOUT (V) 599 0.6 0.675 598 0.2 0.75 0.9 1.25 597 0 ±15 ±10 ±5 0 5 10 15 0 0.5 1 1.5 2 2.5 3 3.5 REFOUT Output Current (mA) Output Current (A) LP DDR3 or DDR4 Figure 15. REFOUT Load Regulation Figure 16. DROPOUT Voltage vs. Output Current 60 200 60 200 50 150 50 150 40 40 100 100 30 30 50 50 Gain (dB) Gain (dB) Phase (°) Phase (°) 20 20 0 0 10 10 ±50 ±50 0 0 ±10 ±100 ±10 ±100 ±20 Gain ±150 ±20 Gain ±150 Phase Phase ±30 ±200 ±30 ±200 1k 10 k 100 k 1M 10 M 1k 10 k 100 k 1M 10 M Frequency (Hz) Frequency (Hz) DDR2 DDR3 Figure 17. Bode Plot Figure 18. Bode Plot 10 Submit Documentation Feedback Copyright © 2008–2020, Texas Instruments Incorporated Product Folder Links: TPS51200  TPS51200 www.ti.com SLUS812D – FEBRUARY 2008 – REVISED FEBRUARY 2020 7 Detailed Description 7.1 Overview The TPS51200 device is a sink and source double data rate (DDR) termination regulator specifically designed for low input voltage, low-cost, low-noise systems where space is a key consideration. The device maintains a fast transient response and only requires a minimum output capacitance of 20 μF. The device supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, DDR3L, Low Power DDR3, and DDR4 VTT bus termination. 7.2 Functional Block Diagram 2 VLDOIN REFIN 1 + 6 REFOUT 2.3 V UVLO VIN 10 + Gm DchgREF VOSNS 5 3 VO + ENVTT DchgVTT EN 7 Gm 4 PGND REFINOK GND 8 9 PGOOD + + Start-up Delay + + Copyright © 2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Sink and Source Regulator (VO Pin) The TPS51200 is a sink and source tracking termination regulator specifically designed for low input voltage, low-cost, and low external component count systems where space is a key application parameter. The device integrates a high-performance, low-dropout (LDO) linear regulator that is capable of both sourcing and sinking current. The LDO regulator employs a fast feedback loop so that small ceramic capacitors can be used to support the fast load transient response. To achieve tight regulation with minimum effect of trace resistance, connect a remote sensing terminal, VOSNS, to the positive terminal of each output capacitor as a separate trace from the high current path from VO. 7.3.2 Reference Input (REFIN Pin) The output voltage, VO, is regulated to REFOUT. When REFIN is configured for standard DDR termination applications, REFIN can be set by an external equivalent ratio voltage divider connected to the memory supply bus (VDDQ). The TPS51200 device supports REFIN voltages from 0.5 V to 1.8 V, making it versatile and ideal for many types of low-power LDO applications. Copyright © 2008–2020, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TPS51200 TPS51200 SLUS812D – FEBRUARY 2008 – REVISED FEBRUARY 2020 www.ti.com Feature Description (continued) 7.3.3 Reference Output (REFOUT Pin) When it is configured for DDR termination applications, REFOUT generates the DDR VTT reference voltage for the memory application. It is capable of supporting both a sourcing and sinking load of 10 mA. REFOUT becomes active when REFIN voltage rises to 0.390 V and VIN is above the UVLO threshold. When REFOUT is less than 0.375 V, it is disabled and subsequently discharges to GND through an internal 10-kΩ MOSFET. REFOUT is independent of the EN pin state. 7.3.4 Soft-Start Sequencing A current clamp implements the soft-start function of the VO pin. The current clamp allows the output capacitors to be charged with low and constant current, providing a linear ramp-up of the output voltage. When VO is outside of the powergood window, the current clamp level is one-half of the full overcurrent limit (OCL) level. When VO rises or falls within the PGOOD window, the current clamp level switches to the full OCL level. The soft-start function is completely symmetrical and the overcurrent limit works for both directions. The soft-start function works not only from GND to the REFOUT voltage, but also from VLDOIN to the REFOUT voltage. 7.3.5 Enable Control (EN Pin) When EN is driven high, the VO regulator begins normal operation. When the device drives EN low, VO discharges to GND through an internal 18-Ω MOSFET. REFOUT remains on when the device drives EN low. Ensure that the EN pin voltage remains lower than or equal to VVIN at all times. 7.3.6 Powergood Function (PGOOD Pin) The TPS51200 device provides an open-drain PGOOD output that goes high when the VO output is within ±20% of REFOUT. PGOOD de-asserts within 10 μs after the output exceeds the size of the powergood window. During initial VO start-up, PGOOD asserts high 2 ms (typ) after the VO enters power good window. Because PGOOD is an open-drain output, a pull-up resistor with a value between 1 kΩ and 100 kΩ, placed between PGOOD and a stable active supply voltage rail is required. 7.3.7 Current Protection (VO Pin) The LDO has a constant overcurrent limit (OCL). The OCL level reduces by one-half when the output voltage is not within the powergood window. This reduction is a non-latch protection. 7.3.8 UVLO Protection (VIN Pin) For VIN undervoltage lockout (UVLO) protection, the TPS51200 monitors VIN voltage. When the VIN voltage is lower than the UVLO threshold voltage, both the VO and REFOUT regulators are powered off. This shutdown is a non-latch protection. 7.3.9 Thermal Shutdown The TPS51200 monitors junction temperature. If the device junction temperature exceeds the threshold value, (typically 150°C), the VO and REFOUT regulators both shut off, discharged by the internal discharge MOSFETs. This shutdown is a non-latch protection. 7.3.10 Tracking Start-up and Shutdown The TPS51200 also supports tracking start-up and shutdown when the EN pin is tied directly to the system bus and not used to turn on or turn off the device. During tracking start-up, VO follows REFOUT once REFIN voltage is greater than 0.39 V. REFIN follows the rise of VDDQ rail through a voltage divider. The typical soft-start time (tSS) for the VDDQ rail is approximately 3 ms, however it may vary depending on the system configuration. The soft-start time of the VO output no longer depends on the OCL setting, but it is a function of the soft-start time of the VDDQ rail. PGOOD is asserted 2 ms after VVO is within ±20% of REFOUT. During tracking shutdown, the VO pin voltage falls following REFOUT until REFOUT reaches 0.37 V. When REFOUT falls below 0.37 V, the internal discharge MOSFETs turn on and quickly discharge both REFOUT and VO to GND. PGOOD is deasserted when VO is beyond the ±20% range of REFOUT. Figure 20 shows the typical timing diagram for an application that uses tracking start-up and shutdown. 12 Submit Documentation Feedback Copyright © 2008–2020, Texas Instruments Incorporated Product Folder Links: TPS51200  TPS51200 www.ti.com SLUS812D – FEBRUARY 2008 – REVISED FEBRUARY 2020 Feature Description (continued) 3.3VIN VVDDQ = 1.5 V VLDOIN REFIN REFOUT (VTTREF) EN (S3_SLP) tSS. VVO = 0.75 V VO COUT x VO tSS = IOOCL PGOOD 2 ms Figure 19. Typical Timing Diagram for S3 and Pseudo-S5 Support 3.3VIN EN VLDOIN REFIN REFOUT (VTTREF) tSS determined by the SS time VVO = 0.75 V of VLDOIN VO PGOOD 2 ms Figure 20. Typical Timing Diagram of Tracking Start-up and Shutdown Copyright © 2008–2020, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: TPS51200 TPS51200 SLUS812D – FEBRUARY 2008 – REVISED FEBRUARY 2020 www.ti.com Feature Description (continued) 7.3.11 Output Tolerance Consideration for VTT DIMM Applications The TPS51200 is specifically designed to power up the memory termination rail (as shown in Figure 21). The DDR memory termination structure determines the main characteristics of the VTT rail, which is to be able to sink and source current while maintaining acceptable VTT tolerance. See Figure 22 for typical characteristics for a single memory cell. DDR3 240 Pin Socket CA CA Vdd Vdd Vtt Vdd Vtt SPD DQ DQ VO TPS51200 10 mF 10 mF 10 mF UDG-08022 Figure 21. Typical Application Diagram for DDR3 VTT DIMM using TPS51200 VDDQ VTT Q1 25 W RS Receiver Ouput 20 W Buffer (Driver) Q2 VOUT VIN VSS UDG-08023 Figure 22. DDR Physical Signal System Bi-Directional SSTL Signaling In Figure 22, when Q1 is on and Q2 is off: Current flows from VDDQ via the termination resistor to VTT VTT sinks current In Figure 22, when Q2 is on and Q1 is off: Current flows from VTT via the termination resistor to GND VTT sources current 14 Submit Documentation Feedback Copyright © 2008–2020, Texas Instruments Incorporated Product Folder Links: TPS51200  TPS51200 www.ti.com SLUS812D – FEBRUARY 2008 – REVISED FEBRUARY 2020 Feature Description (continued) Because VTT accuracy has a direct impact on the memory signal integrity, it is imperative to understand the tolerance requirement on VTT. Equation 1 applies to both DC and AC conditions and is based on JEDEC VTT specifications for DDR and DDR2 (JEDEC standard: DDR JESD8-9B May 2002; DDR2 JESD8-15A Sept 2003). VVTTREF – 40 mV < VVTT < VVTTREF + 40 mV (1) The specification itself indicates that VTT must keep track of VTTREF for proper signal conditioning. The TPS51200 ensures the regulator output voltage to be as shown in Equation 2, which applies to both DC and AC conditions. VVTTREF –25 mV < VVTT < VVTTREF + 25 mV where –2 A < IVTT < 2 A (2) The regulator output voltage is measured at the regulator side, not the load side. The tolerance is applicable to DDR, DDR2, DDR3, DDR3L, Low Power DDR3, and DDR4 applications (see Table 1 for detailed information). To meet the stability requirement, a minimum output capacitance of 20 μF is needed. Considering the actual tolerance on the MLCC capacitors, three 10-μF ceramic capacitors sufficiently meet the VTT accuracy requirement. Table 1. DDR, DDR2, DDR3 and LP DDR3 Termination Technology DDR DDR2 DR3 LOW POWER DDR3 FSB Data 200, 266, 333, and 400 MHz 400, 533, 677, and 800 MHz 800, 1066, 1330, and 1600 MHz Rates On-die termination for data Motherboard termination to group. VTT termination for On-die termination for data group. VTT termination for Termination VTT for all signals address, command and address, command and control signals control signals Not as demanding Not as demanding Only 34 signals (address, Termination Maximum source/sink command, control) tied to Only 34 signals (address, command, control) tied to VTT Current transient currents of up to 2.6 VTT Demand A to 2.9 A ODT handles data signals ODT handles data signals Less than 1-A of burst Less than 1-A of burst current current 2.5-V Core and 1.8-V Core and 1.5-V Core and 1.2-V Core and Voltage Level I/O 1.25-V VTT I/O 0.9-V VTT I/O 0.75-V VTT I/O 0.6-V VTT The TPS51200 uses transconductance (gM) to drive the LDO. The transconductance and output current of the device determine the voltage droop between the reference input and the output regulator. The typical transconductance level is 250 S at 2 A and changes with respect to the load in order to conserve the quiescent current (that is, the transconductance is very low at no load condition). The (gM) LDO regulator is a single pole system. Only the output capacitance determines the unity gain bandwidth for the voltage loop, as a result of the bandwidth nature of the transconductance (see Equation 3). gM ƒUGBW = 2 ´ p ´ COUT where ƒUGBW is the unity gain bandwidth gM is transconductance COUT is the output capacitance (3) Consider these two limitations to this type of regulator that come from the output bulk capacitor requirement. In order to maintain stability, the zero location contributed by the ESR of the output capacitors must be greater than the –3-dB point of the current loop. This constraint means that higher ESR capacitors should not be used in the design. In addition, the impedance characteristics of the ceramic capacitor should be well understood in order to prevent the gain peaking effect around the transconductance (gM) –3-dB point because of the large ESL, the output capacitor and parasitic inductance of the VO pin voltage trace. Copyright © 2008–2020, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: TPS51200 TPS51200 SLUS812D – FEBRUARY 2008 – REVISED FEBRUARY 2020 www.ti.com 7.3.12 REFOUT (VREF) Consideration for DDR2 Applications During TPS51200 tracking start-up, the REFIN voltage follows the rise of the VDDQ rail through a voltage divider, and REFOUT (VREF) follows REFIN once the REFIN voltage is greater than 0.39 V. When the REFIN voltage is lower than 0.39 V, VREF is 0 V. The JEDEC DDR2 SDRAM Standard (JESD79-2E) states that VREF must track VDDQ/2 within ±0.3 V accuracy during the start-up period. To allow the TPS51200 device to meet the JEDEC DDR2 specification, a resistor divider can be used to provide the VREF signal to the DIMM. The resistor divider ratio is 0.5 to ensure that the VREF voltage equals VDDQ/2. VVDDQ DDR RREF VREF RREF Figure 23. Resistor Divider Circuit When selecting the resistor value, consider the impact of the leakage current from the DIMM VREF pin on the reference voltage. Use Equation 4 to calculate resistor values. 2 × ¿VREF R REF Q IREF where RREF is the resistor value ∆VREF is the VREF DC variation requirement IREF is the maximum total VREF leakage current from DIMMs (4) Consider the MT47H64M16 DDR2 SDRAM component from Micron as an example. The MT47H64M16 datasheet shows the maximum VREF leakage current of each DIMM is ±2 µA, and VREF(DC) variation must be within ±1% of VDDQ. In this DDR2 application, the VDDQ voltage is 1.8 V. Assuming one TPS51200 device needs to power 4 DIMMs, the maximum total VREF leakage current is ±8 µA. Based on the calculations, the resistor value should be lower than 4.5 kΩ. To ensure sufficient margin, 100 Ω is the suggested resistor value. With two 100-Ω resistors, the maximum VREF variation is 0.4 mV, and the power loss on each resistor is 8.1 mW. 16 Submit Documentation Feedback Copyright © 2008–2020, Texas Instruments Incorporated Product Folder Links: TPS51200  TPS51200 www.ti.com SLUS812D – FEBRUARY 2008 – REVISED FEBRUARY 2020 7.4 Device Functional Modes 7.4.1 Low Input Voltage Applications TPS51200 can be used in an application system that offers either a 2.5-V rail or a 3.3-V rail. If only a 5-V rail is available, consider using the TPS51100 device as an alternative. The TPS51200 device has a minimum input voltage requirement of 2.375 V. If a 2.5-V rail is used, ensure that the absolute minimum voltage (both DC and transient) at the device pin is be 2.375 V or greater. The voltage tolerance for a 2.5-V rail input is between –5% and 5% accuracy, or better. 7.4.2 S3 and Pseudo-S5 Support The TPS51200 provides S3 support by an EN function. The EN pin could be connected to an SLP_S3 signal in the end application. Both REFOUT and VO are on when EN = high (S0 state). REFOUT is maintained while VO is turned off and discharged via an internal discharge MOSFET when EN = low (S3 state). When EN = low and the REFIN voltage is less than 0.390 V, TPS51200 enters pseudo-S5 state. Both VO and REFOUT outputs are turned off and discharged to GND through internal MOSFETs when pseudo-S5 support is engaged (S4 or S5 state). Figure 19 shows a typical start-up and shutdown timing diagram for an application that uses S3 and pseudo-S5 support. Copyright © 2008–2020, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: TPS51200 TPS51200 SLUS812D – FEBRUARY 2008 – REVISED FEBRUARY 2020 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.2 Typical Application This design example describes a 3.3-VIN, DDR3 configuration. R1 TPS51200 10 kW VVDDQ = 1.5 V 1 REFIN VIN 10 3.3 VIN R2 C4 10 kW 1000 pF R3 C6 100 kW 4.7 mF VVLDOIN = VVDDQ = 1.5 V 2 VLDOIN PGOOD 9 PGOOD C7 C8 10 mF 10 mF VVTT = 0.75 V 3 VO GND 8 C1 C2 C3 4 PGND EN 7 SLP_S3 10 mF 10 mF 10 mF 5 VOSNS REFOUT 6 VTTREF C5 0.1 mF UDG-08029 Figure 24. 3.3-VIN, DDR3 Configuration Table 2. 3.3-VIN, DDR3 Application List of Materials REFERENCE DESCRIPTION SPECIFICATION PART NUMBER MANUFACTURER DESIGNATOR R1, R2 10 kΩ Resistor R3 100 kΩ C1, C2, C3 10 μF, 6.3 V GRM21BR70J106KE76L Murata C4 1000 pF C5 Capacitor 0.1 μF C6 4.7 μF, 6.3 V GRM21BR60J475KA11L Murata C7, C8 10 μF, 6.3 V GRM21BR70J106KE76L Murata 18 Submit Documentation Feedback Copyright © 2008–2020, Texas Instruments Incorporated Product Folder Links: TPS51200  TPS51200 www.ti.com SLUS812D – FEBRUARY 2008 – REVISED FEBRUARY 2020 8.2.1 Design Requirements VIN = 3.3 V VDDDQ = 1.5 V VVLDOIN = VVDDQ = 1.5 V VVTT = 0.75 V 8.2.2 Detailed Design Procedure 8.2.2.1 Input Voltage Capacitor Add a ceramic capacitor, with a value between 1.0-μF and 4.7-μF, placed close to the VIN pin, to stabilize the bias supply (2.5-V rail or 3.3-V rail) from any parasitic impedance from the supply. 8.2.2.2 VLDO Input Capacitor Depending on the trace impedance between the VLDOIN bulk power supply to the device, a transient increase of source current is supplied mostly by the charge from the VLDOIN input capacitor. Use a 10-μF (or greater) ceramic capacitor to supply this transient charge. Provide more input capacitance as more output capacitance is used at the VO pin. In general, use one-half of the COUT value for input. 8.2.2.3 Output Capacitor For stable operation, the total capacitance of the VO output pin must be greater than 20 μF. Attach three, 10-μF ceramic capacitors in parallel to minimize the effect of equivalent series resistance (ESR) and equivalent series inductance (ESL). If the ESR is greater than 2 mΩ, insert an RC filter between the output and the VOSNS input to achieve loop stability. The RC filter time constant should be almost the same as or slightly lower than the time constant of the output capacitor and its ESR. Copyright © 2008–2020, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: TPS51200 TPS51200 SLUS812D – FEBRUARY 2008 – REVISED FEBRUARY 2020 www.ti.com 8.2.3 Application Curves Figure 25 shows the bode plot simulation for this DDR3 design example of the TPS51200 device. The unity-gain bandwidth is approximately 1 MHz and the phase margin is 52°. The 0-dB level is crossed, the gain peaks because of the ESL effect. However, the peaking maintains a level well below 0 dB. Figure 26 shows the load regulation and Figure 27 shows the transient response for a typical DDR3 configuration. When the regulator is subjected to ±1.5-A load step and release, the output voltage measurement shows no difference between the dc and ac conditions. 80 0 40 ±90 Gain (dB) Phase (°) 0 ±180 ±270 ±40 Gain Phase ±80 ±360 1 10 100 1000 10 k 100 k 1M 10 M 100 M Frequency (Hz) VIN = 3.3 V VVLDOIN = 1.5 V VVO = 0.75 V IIO = 2 A 3 × 10-μF capacitors ESR = 2.5 mΩ ESL = 800 pH Figure 25. DDR3 Design Example Bode Plot 790 TA 780 ± 40°C 770 0°C 25°C Output Voltage (mV) 760 85°C 750 740 730 720 710 700 ±3 ±2 ±1 0 1 2 3 Output Current (A) VVIN = 3.3 V DDR3 Figure 26. Load Regulation Figure 27. Transient Waveform 20 Submit Documentation Feedback Copyright © 2008–2020, Texas Instruments Incorporated Product Folder Links: TPS51200  TPS51200 www.ti.com SLUS812D – FEBRUARY 2008 – REVISED FEBRUARY 2020 8.3 System Examples 8.3.1 3.3-VIN, DDR2 Configuration This section describes a 3.3-VIN, DDR2 configuration application. R1 TPS51200 10 k: VVDDQ = 1.8 V 1 REFIN VIN 10 3.3 VIN R2 C4 10 k: 1000 pF R3 C6 100 k: 4.7 PF VVLDOIN = VVDDQ = 1.8 V 2 VLDOIN PGOOD 9 PGOOD C7 C8 10 PF 10 PF VVDDQ = 1.8 V VVTT = 0.9 V 3 VO GND 8 R4 C1 C2 C3 4 PGND EN 7 SLP_S3 100 Ÿ 10 PF 10 PF 10 PF VTTREF 5 VOSNS REFOUT 6 C5 R5 0.1 PF 100 Ÿ Figure 28. 3.3-VIN, DDR2 Configuration Table 3. 3.3-VIN, DDR2 Configuration List of Materials REFERENCE DESCRIPTION SPECIFICATION PART NUMBER MANUFACTURER DESIGNATOR R1, R2 10 kΩ R3 Resistor 100 kΩ R4, R5 100 Ω C1, C2, C3 10 μF, 6.3 V GRM21BR70J106KE76L Murata C4 1000 pF C5