MicroProLectures.pdf

Lecture Note On Microprocessor and Microcontroller Theory and Applications Subject Code:BEE-1501 Semester: 5th Branch: EE and EEE Syllabus  Disclaimer This document does not claim any originality and cannot be used as a substitute for prescribed textbooks. The info...

Lecture Note On Microprocessor and Microcontroller Theory and Applications Subject Code:BEE-1501 Semester: 5th Branch: EE and EEE Syllabus  Disclaimer This document does not claim any originality and cannot be used as a substitute for prescribed textbooks. The information presented here is merely a collection by the committee members for their respective teaching assignments. Various sources as mentioned at the end of the document as well as freely available material from internet were consulted for preparing this document. The ownership of the information lies with the respective authors or institutions. Further, this document is not intended to be used for commercial purpose and the committee members are not accountable for any issues, legal, or otherwise, arising out of this document. The committee members make no representations or warranties with respect to the accuracy or completeness of the contents of this document and specially disclaim any implied warranties of merchantability or fitness for a particular purpose. The committee members shall not be liable for any loss or profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages. MODULE: 1 1. INTRODUCTION TO MICROPROCESSOR AND MICROCOMPUTER ARCHITECTURE: A microprocessor is a programmable electronics chip that has computing and decision making capabilities similar to central processing unit of a computer. Any microprocessor- based systems having limited number of resources are called microcomputers. Nowadays, microprocessor can be seen in almost all types of electronics devices like mobile phones, printers, washing machines etc. Microprocessors are also used in advanced applications like radars, satellites and flights. Due to the rapid advancements in electronic industry and large scale integration of devices results in a significant cost reduction and increase application of microprocessors and their derivatives. Fig.1 Microprocessor-based system  Bit: A bit is a single binary digit.  Word: A word refers to the basic data size or bit size that can be processed by the arithmetic and logic unit of the processor. A 16-bit binary number is called a word in a 16-bit processor.  Bus: A bus is a group of wires/lines that carry similar information.  System Bus: The system bus is a group of wires/lines used for communication between the microprocessor and peripherals.  Memory Word: The number of bits that can be stored in a register or memory element is called a memory word.  Address Bus: It carries the address, which is a unique binary pattern used to identify a memory location or an I/O port. For example, an eight bit address bus has eight lines and thus it can address 28 = 256 different locations. The locations in hexadecimal format can be written as 00H – FFH.  Data Bus: The data bus is used to transfer data between memory and processor or between I/O device and processor. For example, an 8-bit processor will generally have an 8-bit data bus and a 16-bit processor will have 16-bit data bus.  Control Bus: The control bus carry control signals, which consists of signals for selection of memory or I/O device from the given address, direction of data transfer and synchronization of data transfer in case of slow devices. A typical microprocessor consists of arithmetic and logic unit (ALU) in association with control unit to process the instruction execution. Almost all the microprocessors are based on the principle of store-program concept. In store-program concept, programs or instructions are sequentially stored in the memory locations that are to be executed. To do any task using a microprocessor, it is to be programmed by the user. So the programmer must have idea about its internal resources, features and supported instructions. Each microprocessor has a set of instructions, a list which is provided by the microprocessor manufacturer. The instruction set of a microprocessor is provided in two forms: binary machine code and mnemonics. Microprocessor communicates and operates in binary numbers 0 and 1. The set of instructions in the form of binary patterns is called a machine language and it is difficult for us to understand. Therefore, the binary patterns are given abbreviated names, called mnemonics, which forms the assembly language. The conversion of assembly-level language into binary machine-level language is done by using an application called assembler. Technology Used: The semiconductor manufacturing technologies used for chips are:  Transistor-Transistor Logic (TTL)  Emitter Coupled Logic (ECL)  Complementary Metal-Oxide Semiconductor (CMOS) Classification of Microprocessors: Based on their specification, application and architecture microprocessors are classified. Based on size of data bus:  4-bit microprocessor  8-bit microprocessor  16-bit microprocessor  32-bit microprocessor Based on application:  General-purpose microprocessor- used in general computer system and can be used by programmer for any application. Examples, 8085 to Intel Pentium.  Microcontroller- microprocessor with built-in memory and ports and can be programmed for any generic control application. Example, 8051.  Special-purpose processors- designed to handle special functions required for an application. Examples, digital signal processors and application-specific integrated circuit (ASIC) chips. Based on architecture:  Reduced Instruction Set Computer (RISC) processors  Complex Instruction Set Computer (CISC) processors 2. 8085 MICROPROCESSOR ARCHITECTURE The 8085 microprocessor is an 8-bit processor available as a 40-pin IC package and uses +5 V for power. It can run at a maximum frequency of 3 MHz. Its data bus width is 8-bit and address bus width is 16-bit, thus it can address 216 = 64 KB of memory. The internal architecture of 8085 is shown is Fig. 2. Fig. 2 Internal Architecture of 8085 Arithmetic and Logic Unit The ALU performs the actual numerical and logical operations such as Addition (ADD), Subtraction (SUB), AND, OR etc. It uses data from memory and from Accumulator to perform operations. The results of the arithmetic and logical operations are stored in the accumulator. Registers The 8085 includes six registers, one accumulator and one flag register, as shown in Fig. 3. In addition, it has two 16-bit registers: stack pointer and program counter. They are briefly described as follows. The 8085 has six general-purpose registers to store 8-bit data; these are identified as B, C, D, E, H and L. they can be combined as register pairs - BC, DE and HL to perform some 16-bit operations. The programmer can use these registers to store or copy data into the register by using data copy instructions. Fig. 3 Register organisation Accumulator The accumulator is an 8-bit register that is a part of ALU. This register is used to store 8-bit data and to perform arithmetic and logical operations. The result of an operation is stored in the accumulator. The accumulator is also identified as register A. Flag register The ALU includes five flip-flops, which are set or reset after an operation according to data condition of the result in the accumulator and other registers. They are called Zero (Z), Carry (CY), Sign (S), Parity (P) and Auxiliary Carry (AC) flags. Their bit positions in the flag register are shown in Fig. 4. The microprocessor uses these flags to test data conditions. Fig. 4 Flag register For example, after an addition of two numbers, if the result in the accumulator is larger than 8-bit, the flip-flop uses to indicate a carry by setting CY flag to 1. When an arithmetic operation results in zero, Z flag is set to 1. The S flag is just a copy of the bit D7 of the accumulator. A negative number has a 1 in bit D7 and a positive number has a 0 in 2’s complement representation. The AC flag is set to 1, when a carry result from bit D3 and passes to bit D4. The P flag is set to 1, when the result in accumulator contains even number of 1s. Program Counter (PC) This 16-bit register deals with sequencing the execution of instructions. This register is a memory pointer. The microprocessor uses this register to sequence the execution of the instructions. The function of the program counter is to point to the memory address from which the next byte is to be fetched. When a byte is being fetched, the program counter is automatically incremented by one to point to the next memory location. Stack Pointer (SP) The stack pointer is also a 16-bit register, used as a memory pointer. It points to a memory location in R/W memory, called stack. The beginning of the stack is defined by loading 16- bit address in the stack pointer. Instruction Register/Decoder It is an 8-bit register that temporarily stores the current instruction of a program. Latest instruction sent here from memory prior to execution. Decoder then takes instruction and decodes or interprets the instruction. Decoded instruction then passed to next stage. Control Unit Generates signals on data bus, address bus and control bus within microprocessor to carry out the instruction, which has been decoded. Typical buses and their timing are described as follows:  Data Bus: Data bus carries data in binary form between microprocessor and other external units such as memory. It is used to transmit data i.e. information, results of arithmetic etc between memory and the microprocessor. Data bus is bidirectional in nature. The data bus width of 8085 microprocessor is 8-bit i.e. 28 combination of binary digits and are typically identified as D0 – D7. Thus size of the data bus determines what arithmetic can be done. If only 8-bit wide then largest number is 11111111 (255 in decimal). Therefore, larger numbers have to be broken down into chunks of 255. This slows microprocessor.  Address Bus: The address bus carries addresses and is one way bus from microprocessor to the memory or other devices. 8085 microprocessor contain 16-bit address bus and are generally identified as A0 - A15. The higher order address lines (A8 – A15) are unidirectional and the lower order lines (A0 – A7) are multiplexed (time-shared) with the eight data bits (D0 – D7) and hence, they are bidirectional.  Control Bus: Control bus are various lines which have specific functions for coordinating and controlling microprocessor operations. The control bus carries control signals partly unidirectional and partly bidirectional. The following control and status signals are used by 8085 processor: I. ALE (output): Address Latch Enable is a pulse that is provided when an address appears on the AD0 – AD7 lines, after which it becomes 0.  II. RD (active low output): The Read signal indicates that data are being read from the selected I/O or memory device and that they are available on the data bus. III. WR (active low output): The Write signal indicates that data on the data bus are to be written into a selected memory or I/O location. IV. IO/M (output): It is a signal that distinguished between a memory operation and an I/O operation. When IO/M = 0 it is a memory operation and IO/M = 1 it is an I/O operation. V. S1 and S0 (output): These are status signals used to specify the type of operation being performed; they are listed in Table 1. Table 1 Status signals and associated operations S1 S0 States 0 0 Halt 0 1 Write 1 0 Read 1 1 Fetch The schematic representation of the 8085 bus structure is as shown in Fig. 5. The microprocessor performs primarily four operations: I. Memory Read: Reads data (or instruction) from memory. II. Memory Write: Writes data (or instruction) into memory. III. I/O Read: Accepts data from input device. IV. I/O Write: Sends data to output device. The 8085 processor performs these functions using address bus, data bus and control bus as shown in Fig. 5. Fig. 5 The 8085 bus structure 3. 8085 PIN DESCRIPTION Properties:  It is a 8-bit microprocessor  Manufactured with N-MOS technology  40 pin IC package  It has 16-bit address bus and thus has 216 = 64 KB addressing capability.  Operate with 3 MHz single-phase clock  +5 V single power supply The logic pin layout and signal groups of the 8085nmicroprocessor are shown in Fig. 6. All the signals are classified into six groups:  Address bus  Data bus  Control & status signals  Power supply and frequency signals  Externally initiated signals  Serial I/O signals Fig. 6 8085 microprocessor pin layout and signal groups Address and Data Buses:  A8 – A15 (output, 3-state): Most significant eight bits of memory addresses and the eight bits of the I/O addresses. These lines enter into tri-state high impedance state during HOLD and HALT modes.  AD0 – AD7 (input/output, 3-state): Lower significant bits of memory addresses and the eight bits of the I/O addresses during first clock cycle. Behaves as data bus  during third and fourth clock cycle. These lines enter into tri-state high impedance state during HOLD and HALT modes. Control & Status Signals:  ALE: Address latch enable  RD : Read control signal.  WR : Write control signal.  IO/M , S1 and S0 : Status signals. Power Supply & Clock Frequency:  Vcc: +5 V power supply  Vss: Ground reference  X1, X2: A crystal having frequency of 6 MHz is connected at these two pins  CLK: Clock output Externally Initiated and Interrupt Signals:  RESET IN : When the signal on this pin is low, the PC is set to 0, the buses are tri- stated and the processor is reset.  RESET OUT: This signal indicates that the processor is being reset. The signal can be used to reset other devices.  READY: When this signal is low, the processor waits for an integral number of clock cycles until it goes high.  HOLD: This signal indicates that a peripheral like DMA (direct memory access) controller is requesting the use of address and data bus.  HLDA: This signal acknowledges the HOLD request.  INTR: Interrupt request is a general-purpose interrupt.  INTA : This is used to acknowledge an interrupt.  RST 7.5, RST 6.5, RST 5,5 – restart interrupt: These are vectored interrupts and have highest priority than INTR interrupt.  TRAP: This is a non-maskable interrupt and has the highest priority. Serial I/O Signals:  SID: Serial input signal. Bit on this line is loaded to D7 bit of register A using RIM instruction.  SOD: Serial output signal. Output SOD is set or reset by using SIM instruction.  4. INSTRUCTION SET AND EXECUTION IN 8085 Based on the design of the ALU and decoding unit, the microprocessor manufacturer provides instruction set for every microprocessor. The instruction set consists of both machine code and mnemonics. An instruction is a binary pattern designed inside a microprocessor to perform a specific function. The entire group of instructions that a microprocessor supports is called instruction set. Microprocessor instructions can be classified based on the parameters such functionality, length and operand addressing. Classification based on functionality: I. Data transfer operations: This group of instructions copies data from source to destination. The content of the source is not altered. II. Arithmetic operations: Instructions of this group perform operations like addition, subtraction, increment & decrement. One of the data used in arithmetic operation is stored in accumulator and the result is also stored in accumulator. III. Logical operations: Logical operations include AND, OR, EXOR, NOT. The operations like AND, OR and EXOR uses two operands, one is stored in accumulator and other can be any register or memory location. The result is stored in accumulator. NOT operation requires single operand, which is stored in accumulator. IV. Branching operations: Instructions in this group can be used to transfer program sequence from one memory location to another either conditionally or unconditionally. V. Machine control operations: Instruction in this group control execution of other instructions and control operations like interrupt, halt etc. Classification based on length: I. One-byte instructions: Instruction having one byte in machine code. Examples are depicted in Table 2. I. Two-byte instructions: Instruction having two byte in machine code. Examples are depicted in Table 3 II. Three-byte instructions: Instruction having three byte in machine code. Examples are depicted in Table 4. Table 2 Examples of one byte instructions Opcode Operand Machine code/Hex code MOV A, B 78 ADD M 86  Table 3 Examples of two byte instructions Opcode Operand Machine code/Hex code Byte description MVI A, 7FH 3E First byte 7F Second byte ADI 0FH C6 First byte 0F Second byte Table 4 Examples of three byte instructions Opcode Operand Machine code/Hex code Byte description JMP 9050H C3 First byte 50 Second byte 90 Third byte LDA 8850H 3A First byte 50 Second byte 88 Third byte Addressing Modes in Instructions: The process of specifying the data to be operated on by the instruction is called addressing. The various formats for specifying operands are called addressing modes. The 8085 has the following five types of addressing: I. Immediate addressing II. Memory direct addressing III. Register direct addressing IV. Indirect addressing V. Implicit addressing Immediate Addressing: In this mode, the operand given in the instruction - a byte or word – transfers to the destination register or memory location. Ex: MVI A, 9AH  The operand is a part of the instruction.  The operand is stored in the register mentioned in the instruction. Memory Direct Addressing: Memory direct addressing moves a byte or word between a memory location and register. The memory location address is given in the instruction. Ex: LDA 850FH This instruction is used to load the content of memory address 850FH in the accumulator. Register Direct Addressing: Register direct addressing transfer a copy of a byte or word from source register to destination register. Ex: MOV B, C It copies the content of register C to register B. Indirect Addressing: Indirect addressing transfers a byte or word between a register and a memory location. Ex: MOV A, M Here the data is in the memory location pointed to by the contents of HL pair. The data is moved to the accumulator. Implicit Addressing In this addressing mode the data itself specifies the data to be operated upon. Ex: CMA The instruction complements the content of the accumulator. No specific data or operand is mentioned in the instruction. 5. INSTRUCTION SET OF 8085 Data Transfer Instructions: Arithmetic Instructions: 6. INSTRUCTION EXECUTION AND TIMING DIAGRAM: Each instruction in 8085 microprocessor consists of two part- operation code (opcode) and operand. The opcode is a command such as ADD and the operand is an object to be operated on, such as a byte or the content of a register. Instruction Cycle: The time taken by the processor to complete the execution of an instruction. An instruction cycle consists of one to six machine cycles. Machine Cycle: The time required to complete one operation; accessing either the memory or I/O device. A machine cycle consists of three to six T-states. T-State: Time corresponding to one clock period. It is the basic unit to calculate execution of instructions or programs in a processor. To execute a program, 8085 performs various operations as:  Opcode fetch  Operand fetch  Memory read/write  I/O read/write External communication functions are:  Memory read/write  I/O read/write  Interrupt request acknowledge Opcode Fetch Machine Cycle: It is the first step in the execution of any instruction. The timing diagram of this cycle is given in Fig. 7. The following points explain the various operations that take place and the signals that are changed during the execution of opcode fetch machine cycle: T1 clock cycle i. The content of PC is placed in the address bus; AD0 - AD7 lines contains lower bit address and A8 – A15 contains higher bit address. ii. IO/M signal is low indicating that a memory location is being accessed. S1 and S0 also changed to the levels as indicated in Table 1. iii. ALE is high, indicates that multiplexed AD0 – AD7 act as lower order bus. T2 clock cycle i. Multiplexed address bus is now changed to data bus. ii. The RD signal is made low by the processor. This signal makes the memory device load the data bus with the contents of the location addressed by the processor. T3 clock cycle i. The opcode available on the data bus is read by the processor and moved to the instruction register. ii. The RD signal is deactivated by making it logic 1. T4 clock cycle i. The processor decode the instruction in the instruction register and generate the necessary control signals to execute the instruction. Based on the instruction further operations such as fetching, writing into memory etc takes place. Fig. 7 Timing diagram for opcode fetch cycle Memory Read Machine Cycle: The memory read cycle is executed by the processor to read a data byte from memory. The machine cycle is exactly same to opcode fetch except: a) It has three T-states b) The S0 signal is set to 0. The timing diagram of this cycle is given in Fig. 8.  Fig. 8 Timing diagram for memory read machine cycle Memory Write Machine Cycle: The memory write cycle is executed by the processor to write a data byte in a memory location. The processor takes three T-states and WR signal is made low. The timing diagram of this cycle is given in Fig. 9. I/O Read Cycle: The I/O read cycle is executed by the processor to read a data byte from I/O port or from peripheral, which is I/O mapped in the system. The 8-bit port address is placed both in the lower and higher order address bus. The processor takes three T-states to execute this machine cycle. The timing diagram of this cycle is given in Fig. 10. Fig. 9 Timing diagram for memory write machine cycle Fig. 10 Timing diagram I/O read machine cycle I/O Write Cycle: The I/O write cycle is executed by the processor to write a data byte to I/O port or to a peripheral, which is I/O mapped in the system. The processor takes three T-states to execute this machine cycle. The timing diagram of this cycle is given in Fig. 11. Fig. 11 Timing diagram I/O write machine cycle Ex: Timing diagram for IN 80H. The instruction and the corresponding codes and memory locations are given in Table 5. Table 5 IN instruction Address Mnemonics Opcode 800F IN 80H DB 8010 80 i. During the first machine cycle, the opcode DB is fetched from the memory, placed in the instruction register and decoded. ii. During second machine cycle, the port address 80H is read from the next memory location. iii. During the third machine cycle, the address 80H is placed in the address bus and the data read from that port address is placed in the accumulator. The timing diagram is shown in Fig. 12.  Fig. 12 Timing diagram for the IN instruction 7. 8085 INTERRUPTS Interrupt Structure: Interrupt is the mechanism by which the processor is made to transfer control from its current program execution to another program having higher priority. The interrupt signal may be given to the processor by any external peripheral device. The program or the routine that is executed upon interrupt is called interrupt service routine (ISR). After execution of ISR, the processor must return to the interrupted program. Key features in the interrupt structure of any microprocessor are as follows: i. Number and types of interrupt signals available. ii. The address of the memory where the ISR is located for a particular interrupt signal. This address is called interrupt vector address (IVA). iii. Masking and unmasking feature of the interrupt signals. iv. Priority among the interrupts. v. Timing of the interrupt signals. vi. Handling and storing of information about the interrupt program (status information). Types of Interrupts: Interrupts are classified based on their maskability, IVA and source. They are classified as:  i. Vectored and Non-Vectored Interrupts  Vectored interrupts require the IVA to be supplied by the external device that gives the interrupt signal. This technique is vectoring, is implemented in number of ways.  Non-vectored interrupts have fixed IVA for ISRs of different interrupt signals. ii. Maskable and Non-Maskable Interrupts  Maskable interrupts are interrupts that can be blocked. Masking can be done by software or hardware means.  Non-maskable interrupts are interrupts that are always recognized; the corresponding ISRs are executed. iii. Software and Hardware Interrupts  Software interrupts are special instructions, after execution transfer the control to predefined ISR.  Hardware interrupts are signals given to the processor, for recognition as an interrupt and execution of the corresponding ISR. Interrupt Handling Procedure: The following sequence of operations takes place when an interrupt signal is recognized: i. Save the PC content and information about current state (flags, registers etc) in the stack. ii. Load PC with the beginning address of an ISR and start to execute it. iii. Finish ISR when the return instruction is executed. iv. Return to the point in the interrupted program where execution was interrupted. Interrupt Sources and Vector Addresses in 8085: Software Interrupts: 8085 instruction set includes eight software interrupt instructions called Restart (RST) instructions. These are one byte instructions that make the processor execute a subroutine at predefined locations. Instructions and their vector addresses are given in Table 6. Table 6 Software interrupts and their vector addresses Instruction Machine hex code Interrupt Vector Address RST 0 C7 0000H RST 1 CF 0008H RST 2 D7 0010H RST 3 DF 0018H RST 4 E7 0020H RST 5 EF 0028H RST 6 F7 0030H RST 7 FF 0032H The software interrupts can be treated as CALL instructions with default call locations. The concept of priority does not apply to software interrupts as they are inserted into the program as instructions by the programmer and executed by the processor when the respective program lines are read. Hardware Interrupts and Priorities: 8085 have five hardware interrupts – INTR, RST 5.5, RST 6.5, RST 7.5 and TRAP. Their IVA and priorities are given in Table 7. Table 7 Hardware interrupts of 8085 Interrupt Interrupt vector Maskable or non- Edge or level priority address maskable triggered TRAP 0024H Non-makable Level 1 RST 7.5 003CH Maskable Rising edge 2 RST 6.5 0034H Maskable Level 3 RST 5.5 002CH Maskable Level 4 INTR Decided by hardware Maskable Level 5 Masking of Interrupts: Masking can be done for four hardware interrupts INTR, RST 5.5, RST 6.5, and RST 7.5. The masking of 8085 interrupts is done at different levels. Fig. 13 shows the organization of hardware interrupts in the 8085. Fig. 13 Interrupt structure of 8085 The Fig. 13 is explained by the following five points:  i. The maskable interrupts are by default masked by the Reset signal. So no interrupt is recognized by the hardware reset. ii. The interrupts can be enabled by the EI instruction. iii. The three RST interrupts can be selectively masked by loading the appropriate word in the accumulator and executing SIM instruction. This is called software masking. iv. All maskable interrupts are disabled whenever an interrupt is recognized. v. All maskable interrupts can be disabled by executing the DI instruction. RST 7.5 alone has a flip-flop to recognize edge transition. The DI instruction reset interrupt enable flip-flop in the processor and the interrupts are disabled. To enable interrupts, EI instruction has to be executed. SIM Instruction: The SIM instruction is used to mask or unmask RST hardware interrupts. When executed, the SIM instruction reads the content of accumulator and accordingly mask or unmask the interrupts. The format of control word to be stored in the accumulator before executing SIM instruction is as shown in Fig. 14. Fig. 14 Accumulator bit pattern for SIM instruction In addition to masking interrupts, SIM instruction can be used to send serial data on the SOD line of the processor. The data to be send is placed in the MSB bit of the accumulator and the serial data output is enabled by making D6 bit to 1. RIM Instruction: RIM instruction is used to read the status of the interrupt mask bits. When RIM instruction is executed, the accumulator is loaded with the current status of the interrupt masks and the pending interrupts. The format and the meaning of the data stored in the accumulator after execution of RIM instruction is shown in Fig. 15. In addition RIM instruction is also used to read the serial data on the SID pin of the processor. The data on the SID pin is stored in the MSB of the accumulator after the execution of the RIM instruction.  Fig. 15 Accumulator bit pattern after execution of RIM instruction Ex: Write an assembly language program to enables all the interrupts in 8085 after reset. EI : Enable interrupts MVI A, 08H : Unmask the interrupts SIM : Set the mask and unmask using SIM instruction Timing of Interrupts: The interrupts are sensed by the processor one cycle before the end of execution of each instruction. An interrupts signal must be applied long enough for it to be recognized. The longest instruction of the 8085 takes 18 clock periods. So, the interrupt signal must be applied for at least 17.5 clock periods. This decides the minimum pulse width for the interrupt signal. The maximum pulse width for the interrupt signal is decided by the condition that the interrupt signal must not be recognized once again. This is under the control of the programmer. QUESTIONS: 1. What is the function of a microprocessor in a system? 2. Why is the data bus in 8085 bidirectional? 3. How does microprocessor differentiate between data and instruction? 4. How long would the processor take to execute the instruction LDA 1753H if the T-state duration is 2μs? 5. Draw the timing diagram of the instruction LDAX B. 6. Sketch and explain the various pins of the 8085. 7. Explain direct addressing mode of 8085 with an example? 8. Draw and explain the timing diagram of the instruction IN 82H. 9. What is meant by ‘priority of the interrupts’? Explain the operation of the interrupts structure of the 8085, with the help of a circuit diagram. 10. Explain the bit pattern for SIM instruction. Write the assembly language program lines to enable all the interrupts in the 8085 after reset. 11. Write the logical instructions which affect and which does not affect flags in 8085. 12. Write an ALP in 8085 MPU to reject all the negative readings and add all the positive reading from a set of ten reading stored in memory locations starting at XX60H. When the sum exceeds eight bits produce output FFH to PORT1 to indicate overload otherwise display the sum. 13. Write an ALP in 8085 to eliminate the blanks (bytes with zero value) from a string of eight data bytes. Use two memory pointers: one to get a byte and the other to store the byte. 14. Design an up-down counter to count from 0 to 9 and 9 to 0 continuously with a 1.5 second delay between each count, and display the count at one of the output ports. MODULE: 2 1. INTERFACING MEMORY AND I/O DEVICES WITH 8085 The programs and data that are executed by the microprocessor have to be stored in ROM/EPROM and RAM, which are basically semiconductor memory chips. The programs and data that are stored in ROM/EPROM are not erased even when power supply to the chip is removed. Hence, they are called non-volatile memory. They can be used to store permanent programs. In a RAM, stored programs and data are erased when the power supply to the chip is removed. Hence, RAM is called volatile memory. RAM can be used to store programs and data that include, programs written during software development for a microprocessor based system, program written when one is learning assembly language programming and data enter while testing these programs. Input and output devices, which are interfaced with 8085, are essential in any microprocessor based system. They can be interfaced using two schemes: I/O mapped I/O and memory-mapped I/O. In the I/O mapped I/O scheme, the I/O devices are treated differently from memory. In the memory-mapped I/O scheme, each I/O device is assumed to be a memory location. 2. INTERFACING MEMORY CHIPS WITH 8085 8085 has 16 address lines (A0 - A15), hence a maximum of 64 KB (= 216 bytes) of memory locations can be interfaced with it. The memory address space of the 8085 takes values from 0000H to FFFFH. The 8085 initiates set of signals such as IO/M , RD and WR when it wants to read from and write into memory. Similarly, each memory chip has signals such as CE or CS (chip enable or chip select), OE or RD (output enable or read) and WE or WR (write enable or write) associated with it. Generation of Control Signals for Memory: When the 8085 wants to read from and write into memory, it activates IO/M , RD and WR signals as shown in Table 8. Table 8 Status of IO/M , RD and WR signals during memory read and write operations IO/M RD WR Operation 0 0 1 8085 reads data from memory 0 1 0 8085 writes data into memory Using IO/M , RD and WR signals, two control signals MEMR (memory read) and MEMW (memory write) are generated. Fig. 16 shows the circuit used to generate these signals.  Fig. 16 Circuit used to generate MEMR and MEMW signals When is IO/M high, both memory control signals are deactivated irrespective of the status of RD and WR signals. Ex: Interface an IC 2764 with 8085 using NAND gate address decoder such that the address range allocated to the chip is 0000H – 1FFFH. Specification of IC 2764:  8 KB (8 x 210 byte) EPROM chip  13 address lines (213 bytes = 8 KB) Interfacing:  13 address lines of IC are connected to the corresponding address lines of 8085.  Remaining address lines of 8085 are connected to address decoder formed using logic gates, the output of which is connected to the CE pin of IC.  Address range allocated to the chip is shown in Table 9.  Chip is enabled whenever the 8085 places an address allocated to EPROM chip in the address bus. This is shown in Fig. 17. Fig. 17 Interfacing IC 2764 with the 8085 Table 9 Address allocated to IC 2764 Ex: Interface a 6264 IC (8K x 8 RAM) with the 8085 using NAND gate decoder such that the starting address assigned to the chip is 4000H. Specification of IC 6264:  8K x 8 RAM  8 KB = 213 bytes  13 address lines The ending address of the chip is 5FFFH (since 4000H + 1FFFH = 5FFFH). When the address 4000H to 5FFFH are written in binary form, the values in the lines A15, A14, A13 are 0, 1 and 0 respectively. The NAND gate is designed such that when the lines A15 and A13 carry 0 and A14 carries 1, the output of the NAND gate is 0. The NAND gate output is in turn connected to the CE1 pin of the RAM chip. A NAND output of 0 selects the RAM chip for read or write operation, since CE2 is already 1 because of its connection to +5V. Fig. 18 shows the interfacing of IC 6264 with the 8085. Fig. 18 Interfacing 6264 IC with the 8085 Ex: Interface two 6116 ICs with the 8085 using 74LS138 decoder such that the starting addresses assigned to them are 8000H and 9000H, respectively. Specification of IC 6116:  2 K x 8 RAM  2 KB = 211 bytes  11 address lines 6116 has 11 address lines and since 2 KB, therefore ending addresses of 6116 chip 1 is and chip 2 are 87FFH and 97FFH, respectively. Table 10 shows the address range of the two chips. Table 10 Address range for IC 6116 Interfacing:  Fig. 19 shows the interfacing.  A0 – A10 lines of 8085 are connected to 11 address lines of the RAM chips.  Three address lines of 8085 having specific value for a particular RAM are connected to the three select inputs (C, B and A) of 74LS138 decoder.  Table 10 shows that A13=A12=A11=0 for the address assigned to RAM 1 and A13=0, A12=1 and A11=0 for the address assigned to RAM 2.  Remaining lines of 8085 which are constant for the address range assigned to the two RAM are connected to the enable inputs of decoder.  When 8085 places any address between 8000H and 87FFH in the address bus, the select inputs C, B and A of the decoder are all 0. The Y0 output of the decoder is also 0, selecting RAM 1.  When 8085 places any address between 9000H and 97FFH in the address bus, the select inputs C, B and A of the decoder are 0, 1 and 0. The Y2 output of the decoder is also 0, selecting RAM 2.  Fig. 19 Interfacing two 6116 RAM chips using 74LS138 decoder 3. PERIPHERAL MAPPED I/O INTERFACING In this method, the I/O devices are treated differently from memory chips. The control signals I/O read ( IOR ) and I/O write ( IOW ), which are derived from the IO/M , RD and WR signals of the 8085, are used to activate input and output devices, respectively. Generation of these control signals is shown in Fig. 20. Table 11 shows the status of IO/M , RD and WR signals during I/O read and I/O write operation. Fig. 20 Generation of IOR and IOW signals IN instruction is used to access input device and OUT instruction is used to access output device. Each I/O device is identified by a unique 8-bit address assigned to it. Since the control signals used to access input and output devices are different, and all I/O device use 8-bit address, a maximum of 256 (28) input devices and 256 output devices can be interfaced with 8085. Table 11 Status of IOR and IOW signals in 8085. IO/M RD WR IOR IOW Operation 1 0 1 0 1 I/O read operation 1 1 0 1 0 I/O write operation 0 X X 1 1 Memory read or write operation Ex: Interface an 8-bit DIP switch with the 8085 such that the address assigned to the DIP switch if F0H. IN instruction is used to get data from DIP switch and store it in accumulator. Steps involved in the execution of this instruction are: i. Address F0H is placed in the lines A0 – A7 and a copy of it in lines A8 – A15. ii. The IOR signal is activated ( IOR = 0), which makes the selected input device to place its data in the data bus. iii. The data in the data bus is read and store in the accumulator. Fig. 21 shows the interfacing of DIP switch. A7 A6 A5 A4 A3 A2 A1 A0 1 1 1 1 0 0 0 0 = F0H A0 – A7 lines are connected to a NAND gate decoder such that the output of NAND gate is 0. The output of NAND gate is ORed with the IOR signal and the output of OR gate is connected to 1G and 2G of the 74LS244. When 74LS244 is enabled, data from the DIP switch is placed on the data bus of the 8085. The 8085 read data and store in the accumulator. Thus data from DIP switch is transferred to the accumulator. Fig. 21 interfacing of 8-bit DIP switch with 8085 4. MEMORY MAPPED I/O INTERFACING In memory-mapped I/O, each input or output device is treated as if it is a memory location. The MEMR and MEMW control signals are used to activate the devices. Each input or output device is identified by unique 16-bit address, similar to 16-bit address assigned to memory location. All memory related instruction like LDA 2000H, LDAX B, MOV A, M can be used. Since the I/O devices use some of the memory address space of 8085, the maximum memory capacity is lesser than 64 KB in this method. Ex: Interface an 8-bit DIP switch with the 8085 using logic gates such that the address assigned to it is F0F0H. Since a 16-bit address has to be assigned to a DIP switch, the memory-mapped I/O technique must be used. Using LDA F0F0H instruction, the data from the 8-bit DIP switch can be transferred to the accumulator. The steps involved are: i. The address F0F0H is placed in the address bus A0 – A15. ii. The MEMR signal is made low for some time. iii. The data in the data bus is read and stored in the accumulator. Fig. 22 shows the interfacing diagram. Fig. 22 Interfacing 8-bit DIP switch with 8085 When 8085 executes the instruction LDA F0F0H, it places the address F0F0H in the address lines A0 – A15 as: A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 = F0F0H The address lines are connected to AND gates. The output of these gates along with MEMR signal are connected to a NAND gate, so that when the address F0F0H is placed in the address bus and MEMR = 0 its output becomes 0, thereby enabling the buffer 74LS244. The data from the DIP switch is placed in the 8085 data bus. The 8085 reads the data from the data bus and stores it in the accumulator. INTEL 8255: (Programmable Peripheral Interface) The 8255A is a general purpose programmable I/O device designed for use with Intel microprocessors. It consists of three 8-bit bidirectional I/O ports (24I/O lines) that can be configured to meet different system I/O needs. The three ports are PORT A, PORT B & PORT C. Port A contains one 8-bit output latch/buffer and one 8-bit input buffer. Port B is same as PORT A or PORT B. However, PORT C can be split into two parts PORT C lower (PC0-PC3) and PORT C upper (PC7-PC4) by the control word. The three ports are divided in two groups Group A (PORT A and upper PORT C) Group B (PORT B and lower PORT C). The two groups can be programmed in three different modes. In the first mode (mode 0), each group may be programmed in either input mode or output mode (PORT A, PORT B, PORT C lower, PORT C upper). In mode 1, the second’s mode, each group may be programmed to have 8-lines of input or output (PORT A or PORT B) of the remaining 4-lines (PORT C lower or PORT C upper) 3-lines are used for hand shaking and interrupt control signals. The third mode of operation (mode 2) is a bidirectional bus mode which uses 8-line (PORT A only for a bidirectional bus and five lines (PORT C upper 4 lines and borrowing one from other group) for handshaking. The 8255 is contained in a 40-pin package, whose pin out is shown below:  PIN Names RESET – Reset input - Chip selected - Read input - Write input A0 A1 – Port Address PA7 – PA0 – PORT A PB7 – PB0 – PORT B PC7 – PC0 – PORT C VCC - +5v GND - Ground The block diagram is shown below: Functional Description: This support chip is a general purpose I/O component to interface peripheral equipment to the microcomputer system bus. It is programmed by the system software so that normally no external logic is necessary to interface peripheral devices or structures. Data Bus Buffer: It is a tri-state 8-bit buffer used to interface the chip to the system data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer. The data lines are connected to BDB of p. Read/Write and logic control: The function of this block is to control the internal operation of the device and to control the transfer of data and control or status words. It accepts inputs from the CPU address and control buses and in turn issues command to both the control groups. Chip Select: A low on this input selects the chip and enables the communication between the 8255 A & the CPU. It is connected to the output of address decode circuitry to select the device when it (Read). A low on this input enables the 8255 to send the data or status information to the CPU on the data bus.  (Write): A low on this input pin enables the CPU to write data or control words into the 8255 A. A1, A0 port select: These input signals, in conjunction with the and inputs, control the selection of one of the three ports or the control word registers. They are normally connected to the least significant bits of the address bus (A0 and A1). Following Table gives the basic operation, A1 A0 Input operation 0 0 0 1 0 PORT A Data bus 0 1 0 1 0 PORT B Data bus 1 0 0 1 0 PORT C Data bus Output operation 0 0 1 0 0 Data bus PORT A 0 1 1 0 0 Data bus PORT B 1 0 1 0 0 Data bus PORT C 1 1 1 0 0 Data bus control All other states put data bus into tri-state/illegal condition. RESET: A high on this input pin clears the control register and all ports (A, B & C) are initialized to input mode. This is connected to RESET OUT of 8255. This is done to prevent destruction of circuitry connected to port lines. If port lines are initialized as output after a power up or reset, the port might try to output into the output of a device connected to same inputs might destroy one or both of them. PORTs A, B and C: The 8255A contains three 8-bit ports (A, B and C). All can be configured in a variety of functional characteristic by the system software. PORTA: One 8-bit data output latch/buffer and one 8-bit data input latch. PORT B: One 8-bit data output latch/buffer and one 8-bit data input buffer. PORT C: One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the control signal outputs and status signals inputs in conjunction with ports A and B. Group A & Group B control: The functional configuration of each port is programmed by the system software. The control words outputted by the CPU configure the associated ports of the each of the two groups. Each control block accepts command from Read/Write content logic receives control words from the internal data bus and issues proper commands to its associated ports. Control Group A – Port A & Port C upper Control Group B – Port B & Port C lower The control word register can only be written into No read operation if the control word register is allowed. Operation Description: Mode selection: There are three basic modes of operation that can be selected by the system software. Mode 0: Basic Input/output Mode 1: Strobes Input/output Mode 2: Bi-direction bus. When the reset input goes HIGH all poets are set to mode’0’ as input which means all 24 lines are in high impedance state and can be used as normal input. After the reset is removed the 8255A remains in the input mode with no additional initialization. During the execution of the program any of the other modes may be selected using a single output instruction. The modes for PORT A & PORT B can be separately defined, while PORT C is divided into two portions as required by the PORT A and PORT B definitions. The ports are thus divided into two groups Group A & Group B. All the output register, including the status flip-flop will be reset whenever the mode is changed. Modes of the two group may be combined for any desired I/O operation e.g. Group A in mode ‘1’ and group B in mode ‘0’. The basic mode definitions with bus interface and the mode definition format are given in fig (a) & (b), INTEL 8259A Programmable Interrupt Controller The 8259A is a programmable interrupt controller designed to work with Intel microprocessor 8080 A, 8085, 8086, 8088. The 8259 A interrupt controller can 1) Handle eight interrupt inputs. This is equivalent to providing eight interrupt pins on the processor in place of one INTR/INT pin. 2) Vector an interrupt request anywhere in the memory map. However, all the eight interrupt are spaced at the interval of either four or eight location. This eliminates the major drawback, 8085 interrupt, in which all interrupts are vectored to memory location on page 00H. 3) Resolve eight levels of interrupt priorities in a variety of modes. 4) Mask each interrupt request individually. 5) Read the status of pending interrupts, in service interrupts, and masked interrupts. 6) Be set up to accept either the level triggered or edge triggered interrupt request. 7) Mine 8259 as can be cascade in a master slave configuration to handle 64 interrupt inputs. The 8259 A is contained in a 28-element in line package that requires only a compatible with 8259. The main difference between the two is that the 8259 A can be used with Intel 8086/8088 processor. It also induces additional features such as level triggered mode, buffered mode and automatic end of interrupt mode. The pin diagram and interval block diagram is shown below: The pins are defined as follows: : Chip select To access this chip, is made low. A LOW on this pin enables & communication between the CPU and the 8259A. This pin is connected to address bus through the decoder logic circuits. INTA functions are independent of. : A low on this pin. When is low enables the 8259 A to accept command words from CPU.  : A low on this pin when is low enables these 8259 A to release status on to the data bus for the CPU. The status in dudes the contents of IMR, ISR or TRR register or a priority level. D7-D0: Bidirectional data bus control status and interrupt in a this bus. This bus is connected to BDB of 8085. CAS0-CAS2: Cascade lines: The CAS lines form a private 8259A bus to control a multiple 8259A structure ie to identify a particular slave device. These pins are outputs of a master 8259A and inputs for a slave 8259A. / : Salve program/enable buffer: This is a dual function pin. It is used as an input to determine whether the 8259A is to a master ( / = 1) or as a slave ( / = 0). It is also used as an output to disable the data bus transceivers when data are being transferred from the 8259A to the CPU. When in buffered mode, it can be used as an output and when not in the buffered mode it is used as an input. INT: This pin goes high whenever a valid interrupt request is asserted. It is used to interrupt the CPU, thus it is connected to the CPU’s interrupt pin (INTR). : Interrupt: Acknowledge. This pin is used to enable 8259A interrupt vector data on the data bus by a sequence of interrupt request pulses issued by the CPU. IR0-IR7: Interrupt Requests: Asynchronous interrupt inputs. An interrupt request is executed by raising an IR input (low to high), and holding it high until it is acknowledged. (Edge triggered mode).or just by a high level on an IR input (levels triggered mode). A0: A0 address line: This pin acts in conjunction with the , & pins. It is used by the 8259A to send various command words from the CPU and to read the status. If is connected to the CPU A0 address line. Two addresses must be reserved in the I/O address space for each 8259 in the system. Functional Description: The 8259 A has eight interrupt request inputs, TR2 IR0. The 8259 A uses its INT output to interrupt the 8085A via INTR pin. The 8259A receives interrupt acknowledge pulses from the at its input. Vector address used by the 8085 A to transfer control to the service subroutine of the interrupting device, is provided by the 8259 A on the data bus. The 8259A is a programmable device that must be initialized by command words sent by the. After initialization the 8259 A mode of operation can be changed by operation command words from the. The descriptions of various blocks are, Data bus buffer: This 3- state, bidirectional 8-bit buffer is used to interface the 8259A to the system data bus. Control words and status information are transferred through the data bus buffer. Read/Write & control logic: The function of this block is to accept OUTPUT commands from the CPU. It contains the initialization command word (ICW) register and operation command word (OCW) register which store the various control formats for device operation. This function block also allows the status of 8159A to be transferred to the data bus. Interrupt request register (IRR): IRR stores all the interrupt inputs that are requesting service. Basically, it keeps track of which interrupt inputs are asking for service. If an interrupt input is unmasked, and has an interrupt signal on it, then the corresponding bit in the IRR will be set. Interrupt mask register (IMR): The IMR is used to disable (Mask) or enable (Unmask) individual interrupt inputs. Each bit in this register corresponds to the interrupt input with the same number. The IMR operation on the IRR. Masking of higher priority input will not affect the interrupt request lines of lower priority. To unmask any interrupt the corresponding bit is set ‘0’. In service register (ISR): The in service registers keeps tracks of which interrupt inputs are currently being serviced. For each input that is currently being serviced the corresponding bit will be set in the in service register. Each of these 3-reg can be read as status reg. Priority Resolver: This logic block determines the priorities of the set in the IRR. The highest priority is selected and strobed into the corresponding bit of the ISR during pulse. Cascade buffer/comparator: This function blocks stores and compare the IDS of all 8259A’s in the reg. The associated 3-I/O pins (CAS0-CAS2) are outputs when 8259A is used a master. Master and are inputs when 8259A is used as a slave. As a master, the 8259A sends the ID of the interrupting slave device onto the cas2-cas0. The slave thus selected will send its pre- programmed subroutine address on to the data bus during the next one or two successive pulses. 8257: Direct Memory Access Controller The Direct Memory Access or DMA mode of data transfer is the fastest amongst all the modes of data transfer. In this mode, the device may transfer data directly to/from memory without any interference from the CPU. The device requests the CPU (through a DMA controller) to hold its data, address and control bus, so that the device may transfer data directly to/from memory. The DMA data transfer is initiated only after receiving HLDA signal from the CPU. Intel’s 8257 is a four channel DMA controller designed to be interfaced with their family of microprocessors. The 8257, on behalf of the devices, requests the CPU for bus access using local bus request input i.e. HOLD in minimum mode. In maximum mode of the microprocessor RQ/GT pin is used as bus request input. On receiving the HLDA signal (in minimum mode) or RQ/GT signal (in maximum mode) from the CPU, the requesting devices gets the access of the bus, and it completes the required number of DMA cycles for the data transfer and then hands over the control of the bus back to the CPU. Internal Architecture of 8257 The internal architecture of 8257 is shown in figure. The chip support four DMA channels, i.e. four peripheral devices can independently request for DMA data transfer through these channels at a time. The DMA controller has 8-bit internal data buffer, a read/write unit, a control unit, a priority resolving unit along with a set of registers. Register Organization of 8257 The 8257 performs the DMA operation over four independent DMA channels. Each of four channels of 8257 has a pair of two 16-bit registers, viz. DMA address register and terminal count register. There are two common registers for all the channels, namely, mode set register and status register. Thus there are a total of ten registers. The CPU selects one of these ten registers using address lines Ao-A3. Table shows how the Ao-A3 bits may be used for selecting one of these registers. DMA Address Register Each DMA channel has one DMA address register. The function of this register is to store the address of the starting memory location, which will be accessed by the DMA channel. Thus the starting address of the memory block which will be accessed by the device is first loaded in the DMA address register of the channel. The device that wants to transfer data over a DMA channel, will access the block of the memory with the starting address stored in the DMA Address Register. Terminal Count Register Each of the four DMA channels of 8257 has one terminal count register (TC). This 16-bit register isused for ascertaining that the data transfer through a DMA channel ceases or stops after the required number of DMA cycles. The low order 14-bits of the terminal count register are initialised with the binary equivalent of the number of required DMA cycles minus one. After each DMA cycle, the terminal count register content will be decremented by one and finally it becomes zero after the required number of DMA cycles are over. The bits 14 and 15 of this register indicate the type of the DMA operation (transfer). If the device wants to write data into the memory, the DMA operation is called DMA write operation. Bit 14 of the register in this case will be set to one and bit 15 will be set to zero. Table gives detail of DMA operation selection and corresponding bit configuration of bits 14 and 15 of the TC register. Mode Set Register The mode set register is used for programming the 8257 as per the requirements of the system. The function of the mode set register is to enable the DMA channels individually and also to set the various modes of operation. The DMA channel should not be enabled till the DMA address register and the terminal count register contain valid information, otherwise, an unwanted DMA request may initiate a DMA cycle, probably destroying the valid memory data. The bits Do-D3 enable one of the four DMA channels of 8257. for example, if Do is ‘1’, channel 0 is enabled. If bit 4 is set, rotating priority is enabled, otherwise, the normal, i.e. fixed priority is enabled. If the TC STOP bit is set, the selected channel is disabled after the terminal count condition is reached, and it further prevents any DMA cycle on the channel. To enable the channel again, this bit must be reprogrammed. If the TC STOP bit is programmed to be zero, the channel is not disabled, even after the count reaches zero and further request are allowed on the same channel. The auto load bit, if set, enables channel 2 for the repeat block chaining operations, without immediate software intervention between the two successive blocks. The channel 2 registers are used as usual, while the channel 3 registers are used to store the block reinitialisation parameters, i.e. the DMA starting address and terminal count. After the first block is transferred using DMA, the channel 2 registers are reloaded with the corresponding channel 3 registers for the next block transfer, if the update flag is set. The extended write bit, if set to ‘1’, extends the duration of MEMW and IOW signals by activating them earlier, this is useful in interfacing the peripherals with different access times. If the peripheral is not accessed within the stipulated time, it is expected to give the ‘NOT READY’ indication to 8257, to request it to add one or more wait states in the DMA CYCLE. The mode set register can only be written into. Status Register The status register of 8257 is shown in figure. The lower order 4-bits of this register contain the terminal count status for the four individual channels. If any of these bits is set, it indicates that the specific channel has reached the terminal count condition. These bits remain set till either the status is read by the CPU or the 8257 is reset. The update flag is not affected by the read operation. This flag can only be cleared by resetting 8257 or by resetting the auto load bit of the mode set register. If the update flag is set, the contents of the channel 3 registers are reloaded to the corresponding registers of channel 2 whenever the channel 2 reaches a terminal count condition, after transferring one block and the next block is to be transferred using the autoload feature of 8257. The update flag is set every time, the channel 2 registers are loaded with contents of the channel 3 registers. It is cleared by the completion of the first DMA cycle of the new block. This register can only read. Data Bus Buffer, Read/Write Logic, Control Unit and Priority Resolver The 8-bit. Tristate, bidirectional buffer interfaces the internal bus of 8257 with the external system bus under the control of various control signals. In the slave mode, the read/write logic accepts the I/O Read or I/O Write signals, decodes the Ao-A3 lines and either writes the contents of the data bus to the addressed internal register or reads the contents of the selected register depending upon whether IOW or IOR signal is activated. In master mode, the read/write logic generates the IOR and IOW signals to control the data flow to or from the selected peripheral. The control logic controls the sequences of operations and generates the required control signals like AEN, ADSTB, MEMR, MEMW, TC and MARK along with the address lines A4-A7, in master mode. The priority resolver resolves the priority of the four DMA channels depending upon whether normal priority or rotating priority is programmed. Signal Description of 8257 DRQo-DRQ3 : These are the four individual channel DMA request inputs, used by the peripheral devices for requesting the DMA services. The DRQo has the highest priority while DRQ3 has the lowest one, if the fixed priority mode is selected. DACKo-DACK3 : These are the active-low DMA acknowledge output lines which inform the requesting peripheral that the request has been honoured and the bus is relinquished by the CPU. These lines may act as strobe lines for the requesting devices. Do-D7: These are bidirectional, data lines used to interface the system bus with the internal data bus of 8257. These lines carry command words to 8257 and status word from 8257, in slave mode, i.e. under the control of CPU. The data over these lines may be transferred in both the directions. When the 8257 is the bus master (master mode, i.e. not under CPU control), it uses Do-D7 lines to send higher byte of the generated address to the latch. This address is further latched using ADSTB signal. the address is transferred over Do-D7 during the first clock cycle of the DMA cycle. During the rest of the period, data is available on the data bus. IOR: This is an active-low bidirectional tristate input line that acts as an input in the slave mode. In slave mode, this input signal is used by the CPU to read internal registers of 8257.this line acts output in master mode. In master mode, this signal is used to read data from a peripheral during a memory write cycle. IOW : This is an active low bidirection tristate line that acts as input in slave mode to load the contents of the data bus to the 8-bit mode register or upper/lower byte of a 16-bit DMA address register or terminal count register. In the master mode, it is a control output that loads the data to a peripheral during DMA memory read cycle (write to peripheral). CLK: This is a clock frequency input required to derive basic system timings for the internal operation of 8257. RESET : This active-high asynchronous input disables all the DMA channels by clearing the mode register and tristates all the control lines. Ao-A3: These are the four least significant address lines. In slave mode, they act as input which select one of the registers to be read or written. In the master mode, they are the four least significant memory address output lines generated by 8257. CS: This is an active-low chip select line that enables the read/write operations from/to 8257, in slave mode. In the master mode, it is automatically disabled to prevent the chip from getting selected (by CPU) while performing the DMA operation. A4-A7 : This is the higher nibble of the lower byte address generated by 8257 during the master mode of DMA operation. READY: This is an active-high asynchronous input used to stretch memory read and write cycles of 8257 by inserting wait states. This is used while interfacing slower peripherals.. HRQ: The hold request output requests the access of the system bus. In the non- cascaded 8257 systems, this is connected with HOLD pin of CPU. In the cascade mode, this pin of a slave is connected with a DRQ input line of the master 8257, while that of the master is connected with HOLD input of the CPU. HLDA : The CPU drives this input to the DMA controller high, while granting the bus to the device. This pin is connected to the HLDA output of the CPU. This input, if high, indicates to the DMA controller that the bus has been granted to the requesting peripheral by the CPU. MEMR: This active –low memory read output is used to read data from the addressed memory locations during DMA read cycles. MEMW :  This active-low three state output is used to write data to the addressed memory location during DMA write operation. ADST : This output from 8257 strobes the higher byte of the memory address generated by the DMA controller into the latches. AEN: This output is used to disable the system data bus and the control the bus driven by the CPU, this may be used to disable the system address and data bus by using the enable input of the bus drivers to inhibit the non-DMA devices from responding during DMA operations. If the 8257 is I/O mapped, this should be used to disable the other I/O devices, when the DMA controller addresses is on the address bus. Pin diagram of 8257 TC: Terminal count output indicates to the currently selected peripherals that the present DMA cycle is the last for the previously programmed data block. If the TC STOP bit in the mode set register is set, the selected channel will be disabled at the end of the DMA cycle. The TC pin is activated when the 14-bit content of the terminal count register of the selected channel becomes equal to zero. The lower order 14 bits of the terminal count register are to be programmed with a 14-bit equivalent of (n-1), if n is the desired number of DMA cycles. MARK : The modulo 128 mark output indicates to the selected peripheral that the current DMA cycle is the 128th cycle since the previous MARK output. The mark will be activated after each 128 cycles or integral multiples of it from the beginning if the data block (the first DMA cycle), if the total number of the required DMA cycles (n) is completely divisible by 128. Vcc : This is a +5v supply pin required for operation of the circuit. GND : This is a return line for the supply (ground pin of the IC). Interfacing 8257 with 8086 Once a DMA controller is initialised by a CPU property, it is ready to take control of the system bus on a DMA request, either from a peripheral or itself (in case of memory-to- memory transfer). The DMA controller sends a HOLD request to the CPU and waits for the CPU to assert the HLDA signal. The CPU relinquishes the control of the bus before asserting the HLDA signal. A conceptual implementation of the system is shown in Figure Once the HLDA signal goes high, the DMA controller activates the DACK signal to the requesting peripheral and gains the control of the system bus. The DMA controller is the sole master of the bus, till the DMA operation is over. The CPU remains in the HOLD status (all of its signals are tristate except HOLD and HLDA), till the DMA controller is the master of the bus. In other words, the DMA controller interfacing circuit implements a switching arrangement for the address, data and control busses of the memory and peripheral subsystem from/to the CPU to/from the DMA controller. QUESTIONS: 1. What are the functions of RAM and ROM chips in a microprocessor-based system? 2. How much memory, in terms of bytes, can be interfaced with the 8085? why? 3. What are the differences between memory-mapped I/O and I/O-mapped I/O schemes? 4. Interface two 8K x 8 RAM and a 8K x 8 EPROM chip with the 8085, using 74LS138 decoder, such that the starting address assigned to them are 6000H, 8000H and 0000K respectively. 5. Name the registers available in 8255. 6. Write the control word format for the I/O mode of the 8255. 7. Write a brief note on the I/O modes of the 8255. 8. List the internal registers of the 8259. 9. Write a note on cascaded mode of operation in the 8259. 10. Explain the initialization process of the 8259. 11. Draw the block diagram of the 8259 and explain how it can be used for increasing the interrupt capabilities of the 8085. 12. How is DMA better than programmed data transfer? 13. Give examples of I/O devices that can be interfaced with DMA. 14. Write the sequence of operation carried out in DMA. 15. Describe in detail how the 8257 can be interfaced with the processor.  MODULE: 3 8086 Microprocessor Architecture and Operation: It is a 16 bit µp. 8086 has a 20 bit address bus can access upto 220 memory locations ( 1 MB). It can support upto 64K I/O ports. It provides 14, 16-bit registers. It has multiplexed address and data bus AD0- AD15 and A16 – A19. It requires single phase clock with 33% duty cycle to provide internal timing. 8086 is designed to operate in two modes, Minimum and Maximum. It can prefetches upto 6 instruction bytes from memory and queues them in order to speed up instruction execution. It requires +5V power supply. A 40 pin dual in line package. Minimum and Maximum Modes: The minimum mode is selected by applying logic 1 to the MN / MX# input pin. This is a single microprocessor configuration. The maximum mode is selected by applying logic 0 to the MN / MX# input pin. This is a multi micro processors configuration. Fig. Architecture of 8086 Internal Architecture of 8086 8086 has two blocks BIU and EU. The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue. EU executes instructions from the instruction system byte queue. Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance. BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder. EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register. Bus Interfacr Unit: It provides a full 16 bit bidirectional data bus and 20 bit address bus. The bus interface unit is responsible for performing all external bus operations. Specifically it has the following functions: Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus control. The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture. This queue permits prefetch of up to six bytes of instruction code. When ever the queue of the BIU is not full, it has room for at least two more bytes and at the same time the EU is not requesting it to read or write operands from memory, the BIU is free to look ahead in the program by prefetching the next sequential instruction. These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU fetches two instruction bytes in a single memory cycle. After a byte is loaded at the input end of the queue, it automatically shifts up through the FIFO to the empty location nearest the output. The EU accesses the queue from the output end. It reads one instruction byte after the other from the output of the queue. If the queue is full and the EU is not requesting access to operand in memory. These intervals of no bus activity, which may occur between bus cycles are known as Idle state. If the BIU is already in the process of fetching an instruction when the EU request it to read or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before initiating the operand read / write cycle. The BIU also contains a dedicated adder which is used to generate the 20 bit physical address that is output on the address bus. This address is formed by adding an appended 16 bit segment address and a 16 bit offset address. For example, the physical address of the next instruction to be fetched is formed by combining the current contents of the code segment CS register and the current contents of the instruction pointer IP register. The BIU is also responsible for generating bus control signals such as those for memory read or write and I/O read or write. EXECUTION UNIT : The Execution unit is responsible for decoding and executing all instructions. The EU extracts instructions from the top of the queue in the BIU, decodes them, generates operands if necessary, passes them to the BIU and requests it to perform the read or write bys cycles to memory or I/O and perform the operation specified by the instruction on the operands. During the execution of the instruction, the EU tests the status and control flags and updates them based on the results of executing the instruction. If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top of the queue. When the EU executes a branch or jump instruction, it transfers control to a location corresponding to another set of sequential instructions. Whenever this happens, the BIU automatically resets the queue and then begins to fetch instructions from this new location to refill the queue. Internal Registers of 8086 The 8086 has four groups of the user accessible internal registers. They are the instruction pointer, four data registers, four pointer and index register, four segment registers. The 8086 has a total of fourteen 16-bit registers including a 16 bit register called the status register, with 9 of bits implemented for status and control flags. Most of the registers contain data/instruction offsets within 64 KB memory segment. There are four different 64 KB segments for instructions, stack, data and extra data. To specify where in 1 MB of processor memory these 4 segments are located the processor uses four segment registers: Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions. Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register can be changed directly using POP instruction. Data segment (DS) is a 16-bit register containing address of 64KB segment with program data. By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. DS register can be changed directly using POP and LDS instructions. Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with program data. By default, the processor assumes that the DI register references the ES segment in string manipulation instructions. ES register can be changed directly using POP and LES instructions. It is possible to change default segments used by general and index registers by prefixing instructions with a CS, SS, DS or ES prefix. All general registers of the 8086 microprocessor can be used for arithmetic and logic operations. The general registers are: Accumulator register consists of two 8-bit registers AL and AH, which can be combined together and used as a 16-bit register AX. AL in this case contains the low-order byte of the word, and AH contains the high-order byte. Accumulator can be used for I/O operations and string manipulation. Base register consists of two 8-bit registers BL and BH, which can be combined together and used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains the high-order byte. BX register usually contains a data pointer used for based, based indexed or register indirect addressing. Count register consists of two 8-bit registers CL and CH, which can be combined together and used as a 16-bit register CX. When combined, CL register contains the low-order byte of the word, and CH contains the high-order byte. Count register can be used in Loop, shift/rotate instructions and as a counter in string manipulation,. Data register consists of two 8-bit registers DL and DH, which can be combined together and used as a 16-bit register DX. When combined, DL register contains the low-order byte of the word, and DH contains the high- order byte. Data register can be used as a port number in I/O operations. In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number. The following registers are both general and index registers: Stack Pointer (SP) is a 16-bit register pointing to program stack. Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for based, based indexed or register indirect addressing. Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data address in string manipulation instructions. Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions. Other registers: Instruction Pointer (IP) is a 16-bit register. Flags is a 16-bit register containing 9 one bit flags. Overflow Flag (OF) - set if the result is too large positive number, or is too small negative number to fit into destination operand. Direction Flag (DF) - if set then string manipulation instructions will auto-decrement index registers. If cleared then the index registers will be auto-incremented. Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts. Single-step Flag (TF) - if set then single-step interrupt will occur after the next instruction. Sign Flag (SF) - set if the most significant bit of the result is set. Zero Flag (ZF) - set if the result is zero Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the AL register. Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result is even. Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit during last result calculation. Addressing Modes Implied - the data value/data address is implicitly associated with the instruction. Register - references the data in a register or in a register pair. Immediate - the data is provided in the instruction. Direct - the instruction operand specifies the memory address where data is located. Register indirect - instruction specifies a register containing an address, where data is located. This addressing mode works with SI, DI, BX and BP registers. Based :- 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP), the resulting value is a pointer to location where data resides. Indexed :- 8-bit or 16-bit instruction operand is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides. Based Indexed :- the contents of a base register (BX or BP) is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides. Based Indexed with displacement :- 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP) and index register (SI or DI), the resulting value is a pointer to location where data resides. Interrupts The processor has the following interrupts: INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using STI/CLI instructions or using more complicated method of updating the FLAGS register with the help of the POPF instruction. When an interrupt occurs, the processor stores FLAGS register into stack, disables further interrupts, fetches from the bus one byte representing interrupt type, and jumps to interrupt processing routine address of which is stored in location 4 *. Interrupt processing routine should return with the IRET instruction. NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is stored in location 0008h. This interrupt has higher priority then the maskable interrupt. Software interrupts can be caused by: INT instruction - breakpoint interrupt. This is a type 3 interrupt. INT instruction - any one interrupt from available 256 interrupts. INTO instruction - interrupt on overflow Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When the CPU processes this interrupt it clears TF flag before calling the interrupt processing routine. Processor exceptions: Divide Error (Type 0), Unused Opcode (type 6) and Escape opcode (type 7). Software interrupt processing is the same as for the hardware interrupts. The figure below shows the 256 interrupt vectors arranged in the interrupt vector table in the memory.  Interrupt Vector Table in the 8086 Minimum Mode Interface When the Minimum mode operation is selected, the 8086 provides all control signals needed to implement the memory and I/O interface. The minimum mode signal can be divided into the following basic groups : address/data bus, status, control, interrupt and DMA. Address/Data Bus : these lines serve two functions. As an address bus is 20 bits long and consists of signal lines A0 through A19. A19 represents the MSB and A0 LSB. A 20bit address gives the 8086 a 1Mbyte memory address space. More over it has an independent I/O address space which is 64K bytes in length. The 16 data bus lines D0 through D15 are actually multiplexed with address lines A0 through A15 respectively. By multiplexed we mean that the bus work as an address bus during first machine cycle and as a data bus during next machine cycles. D15 is the MSB and D0 LSB. When acting as a data bus, they carry read/write data for memory, input/output data for I/O devices, and interrupt type codes from an interrupt controller. Status signal : The four most significant address lines A19 through A16 are also multiplexed but in this case with status signals S6 through S3. These status bits are output on the bus at the same time that data are transferred over the other bus lines. Bit S4 and S3 together from a 2 bit binary code that identifies which of the 8086 internal segment registers are used to generate the physical address that was output on the address bus during the current bus cycle. Code S4S3 = 00 identifies a register known as extra segment register as the source of the segment address. Memory segment status code Status line S5 reflects the status of another internal characteristic of the 8086. It is the logic level of the internal enable flag. The last status bit S6 is always at the logic 0 level. Control Signals : The control signals are provided to support the 8086 memory I/O interfaces. They control functions such as when the bus is to carry a valid address in which direction data are to be transferred over the bus, when valid write data are on the bus and when to put read data on the system bus. ALE is a pulse to logic 1 that signals external circuitry when a valid address word is on the bus. This address must be latched in external circuitry on the 1-to-0 edge of the pulse at ALE. Another control signal that is produced during the bus cycle is BHE bank high enable. Logic 0 on this used as a memory enable signal for the most significant byte half of the data bus D8 through D1. These lines also serves a second function, which is as the S7 status line. Using the M/IO and DT/R lines, the 8086 signals which type of bus cycle is in progress and in which direction data are to be transferred over the bus. The logic level of M/IO tells external circuitry whether a memory or I/O transfer is taking place over the bus. Logic 1 at this output signals a memory operation and logic 0 an I/O operation. The direction of data transfer over the bus is 74ignallin by the logic level output at DT/R. When this line is logic 1 during the data transfer part of a bus cycle, the bus is in the transmit mode. Therefore, data are either written into memory or output to an I/O device. On the other hand, logic 0 at DT/R signals that the bus is in the receive mode. This corresponds to reading data from memory or input of data from an input port. The signal read RD and write WR indicates that a read bus cycle or a write bus cycle is in progress. The 8086 switches WR to logic 0 to signal external device that valid write or output data are on the bus. On the other hand, RD indicates that the 8086 is performing a read of data of the bus. During read operations, one other control signal is also supplied. This is DEN (data enable) and it signals external devices when they should put data on the bus. There is one other control signal that is involved with the memory and I/O interface. This is the READY signal. READY signal is used to insert wait states into the bus cycle such that it is extended by a number of clock periods. This signal is provided by an external clock generator device and can be supplied by the memory or I/O sub- system to signal the 8086 when they are ready to permit the data transfer to be completed. Maximum Mode Interface When the 8086 is set for the maximum-mode configuration, it provides signals for implementing a multiprocessor / coprocessor system environment. By multiprocessor environment we mean that one microprocessor exists in the system and that each processor is executing its own program. Usually in this type of system environment, there are some system resources that are common to all processors. They are called as global resources. There are also other resources that are assigned to specific processors. These are known as local or private resources. Coprocessor also means that there is a second processor in the system. In this two processor does not access the bus at the same time. One passes the control of the system bus to the other and then may suspend its operation. In the maximum- mode 8086 system, facilities are provided for implementing allocation of global resources and passing bus control to other microprocessor or coprocessor. 8288 Bus Controller – Bus Command and Control Signals: 8086 does not directly provide all the signals that are required to control the memory, I/O and interrupt interfaces. Specially the WR, M/IO, DT/R, DEN, ALE and INTA, signals are no longer produced by the 8086. Instead it outputs three status signals S0, S1, S2 prior to the initiation of each bus cycle. This 3- bit bus status code identifies which type of bus cycle is to follow. S2S1S0 are input to the external bus controller device, the bus controller generates the appropriately timed command and control signals. The 8288 produces one or two of these eight command signals for each b us cycles. For instance, when the 8086 outputs the code S2S1S0 equals 001, it indicates that an I/O read cycle is to be performed. In the code 111 is output by the 8086, it is 75ignalling that no bus activity is to take place. The control outputs produced by the 8288 are DEN, DT/R and ALE. These 3 signals provide the same functions as those described for the minimum system mode. This set of bus commands and control signals is compatible with the Multibus and industry standard for interfacing microprocessor systems. 8289 Bus Arbiter – Bus Arbitration and Lock Signals: This device permits processors to reside on the system bus. It does this by implementing the Multibus arbitration protocol in an 8086-based system. Addition of the 8288 bus controller and 8289 bus arbiter frees a number of the 8086 pins for use to produce control signals that are needed to support multiple processors. Bus priority lock (LOCK) is one of these signals. It is input to the bus arbiter together with status signals S0 through S2. Queue Status Signals: Two new signals that are produced by the 8086 in the maximum- mode system are queue status outputs QS0 and QS1. Together they form a 2-bit queue status code, QS1QS0. Following table shows the four different queue status. QUESTIONS: 1. What is the size of address and data bus in the 8086? 2. Draw the register organization of the 8086 and explain typical applications of each register. 3. How is the 20-bit physical memory address calculated in the 8086 processor? 4. Write the different memory segments used in the 8086 and their functions. 5. Write the function of the DF, IF and TF bits in the 8086. 6. The content of the different registers in the 8086 is CS = F000H, DS = 1000H, SS = 2000H and ES = 3000H. Find the base address of the different segments in the memory. 7. What is the difference between the minimum and maximum mode operation of the 8086? 8. What is meant by DMA operation? Which pins of the 8086 are used to perform the DMA operation in the minimum and maximum modes of the 8086? 9. Explain the architecture of the 8086 with a neat functional block diagram. 10. Explain the function of different flags in the 8086. 11. What is the function of segment override prefix? Give two examples. 12. What is the difference between inter-segment and intra-segment jump in the 8086? 13. What is the difference between short and near jump in the 8086? 14. What are the different uses of stack in a microprocessor? 15. What is the difference between the MUL and IMUL instructions in the 8086? 16. What is the difference between the DIV and IDIV instructions in the 8086? 17. What is the function of DAA instruction in the 8086? 18. Write the operations performed when the instruction AAD is executed in the 8086. 19. What is the difference between maskable and non-maskable interrupts? 20. What is the difference between hardware and software interrupts? 21. What is an interrupt vector? What is the maximum number of interrupt vectors that can be stored in the IVT of the 8086? 22. Write a program to move a word string 200 bytes (i.e. 100 words) long from the offset address 1000H to the offset address 3000H in the segment 5000H. 23. Write a program to find the smallest word in an array of 100 words stored sequentially in the memory; starting at the offset address 1000H in the segment address 5000H. Store the result at the offset address 2000H in the same segment. 24. Write a program to add the two BCD data 29H and 98H and store the result in BCD form in the memory locations 2000H: 3000H and 2000H: 3001H. MODULE: 4 8051 microcontroller What is a Microcontroller? A Microcontroller is a programmable digital processor with necessary peripherals. Both microcontrollers and microprocessors are complex sequential digital circuits meant to carry out job according to the program / instructions. Sometimes analog input/output interface makes a part of microcontroller circuit of mixed mode(both analog and digital nature). Microcontrollers Vs Microprocessors 1. A microprocessor requires an external memory for program/data storage. Instruction execution requires movement of data from the external memory to the microprocessor or vice versa. Usually, microprocessors have good computing power and they have higher clock speed to facilitate faster computation. 2. A microcontroller has required on-chip memory with associated peripherals. A microcontroller can be thought of a microprocessor with inbuilt peripherals. 3. A microcontroller does not require much additional interfacing ICs for operation and it functions as a stand alone system. The operation of a microcontroller is multipurpose, just like a Swiss knife. 4. Microcontrollers are also called embedded controllers. A microcontroller clock speed is limited only to a few tens of MHz. Microcontrollers are numerous and many of them are application specific. Development/Classification of microcontrollers (Invisible) Microcontrollers have gone through a silent evolution (invisible). The evolution can be rightly termed as silent as the impact or application of a microcontroller is not well known to a common user, although microcontroller technology has undergone significant change since early 1970's. Development of some popular microcontrollers is given as follows. 4 bit (2300 PMOS trans, 108 Intel 4004 1971 kHz) Intel 8048 8 bit 1976 Intel 8031 8 bit (ROM-less). Intel 8051 8 bit (Mask ROM) 1980 Microchip PIC16C64 8 bit 1985 Motorola 68HC11 8 bit (on chip ADC). Intel 80C196 16 bit 1982 Atmel AT89C51 8 bit (Flash memory). Microchip PIC 8 bit (Flash memory + ADC). 16F877 Development of microprocessors (Visible) Microprocessors have undergone significant evolution over the past fo