Introduction to Microprocessors and Microcontrollers PDF

Introduction to Microprocessors and Microcontrollers Mrs. Savita C. Raut EXTC Dept,KJSCE  What is Microprocessor?? Block diagram of a computer  What is a Microprocessor? Computer's Central Processing Unit (CPU) built on a single Integrated Circuit...

Introduction to Microprocessors and Microcontrollers Mrs. Savita C. Raut EXTC Dept,KJSCE  What is Microprocessor?? Block diagram of a computer  What is a Microprocessor? Computer's Central Processing Unit (CPU) built on a single Integrated Circuit (IC) is called a microprocessor. A digital computer with one microprocessor which acts as a CPU is called microcomputer. It is a programmable, multipurpose, clock -driven, register-based electronic device that reads binary instructions from a storage device called memory, accepts binary data as input and processes data according to those instructions and provides results as output.  Evolution of Microprocessor The first microprocessor was introduced in the year 1971. It was introduced by Intel and was named Intel 4004. Intel 4004 is a 4 bit microprocessor and it was not a powerful microprocessor. It can perform addition and subtraction operation on 4 bits at a time. However it was Intel’s 8080 was the first microprocessor to make it to Home computers. It was introduced during the year 1974 and it can perform 8 bit operations. Then during the year 1976, Intel introduced 8085 processors which is nothing but an update of 8080 processors.8080 processors are updated by adding two Enable/Disable Instructions, Three added interrupt pins and serial I/O pins.  Intel introduced 8086 pins during the year 1976. The major difference between 8085 and 8086 processor is that 8085 is an 8 bit processor, but 8086 processor is a 16 bit processor. Intel later introduced 8087 processor which was the first math co-processor and later the 8088 processor which was incorporated into IBM personal computers. As the years progressed lots of processors from 8088,80286,80386,80486,Pentium II, Pentium III, Pentium IV and now Core2Duo,Dual Core and Quad core processors are the latest in the market. Pentium II 32 233 to 500M 1997 Pentium III 32 500M to 1.4G 1999 Pentium IV 32 1.3 to 3.8G 2000 8086 Microprocessor Dual core 32-bit 1.2 to 3 G 2006 Core 2 Duo 64 1.2 to 3G 2006 i3, i5 and i7 64 2.4G to 3.6G 2010 Microprocessor generations First Generation (4 - bit Microprocessors) The first generation microprocessors were introduced in the year 1971-1972 by Intel Corporation. It was named Intel 4004 since it was a 4-bit processor. It was a processor on a single chip. It could perform simple arithmetic and logical operations such as addition, subtraction, Boolean OR and Boolean AND. It had a control unit capable of performing control functions like fetching an instruction from storage memory, decoding it, and then generating control pulses to execute it. Second Generation (8 - bit Microprocessor) The second generation microprocessors were introduced in 1973 again by Intel. It was a first 8 - bit microprocessor which could perform arithmetic and logic operations on 8-bit words. It was Intel 8008, and another improved version was Intel 8088. Third Generation (16 - bit Microprocessor) The third generation microprocessors, introduced in 1978 were represented by Intel's 8086, Zilog Z800 and 80286, which were 16 - bit processors with a performance like minicomputers. Fourth Generation (32 - bit Microprocessors) Several different companies introduced the 32-bit microprocessors, but the most popular one is the Intel 80386. Fifth Generation (64 - bit Microprocessors) From 1995 to now we are in the fifth generation. After 80586, Intel came out with a new processor namely Pentium processor followed by Pentium Pro CPU, which allows multiple CPUs in a single system to achieve multiprocessing. Other improved 64-bit processors are Celeron, Dual, Quad, Octa Core processors.  Suggested Reading : (for additional information) Intel Processors Over the Years https://www.businessnewsdaily.com/10817- slideshow-intel-processors-over-the-years.html What is a Microcontroller?  What is a Microcontroller? A microcontroller is a small, low-cost and self contained computer- on-a-chip that can be used as an embedded system. A few microcontrollers may utilize four-bit expressions and work at clock rate frequencies, which usually include: An 8 or 16 bit microprocessor. A little measure of RAM. Programmable ROM and flash memory. Parallel and serial I/O. Timers and signal generators. Analog to Digital and Digital to Analog conversion Microcontrollers usually must have low-power requirements since many devices they control are battery-operated. Microcontrollers are used in many consumer electronics, car engines, computer peripherals and test or measurement equipment. And these are well suited for long lasting battery applications. The dominant part of microcontrollers being used now a days are implanted in other apparatus.  Classification According to Number of Bits 8-bit microcontroller: The internal bus is 8-bit, then the ALU performs the arithmetic and logic operations. The examples of 8-bit microcontrollers are Intel 8031/8051, PIC1x and Motorola MC68HC11 families. 16-bit microcontroller: It can operate on two 16 bit numbers. Some examples of 16-bit microcontroller are 16-bit MCUs are extended 8051XA, PIC2x, Intel 8096 and Motorola MC68HC12 families. 32-bit microcontroller: uses the 32-bit instructions to perform the arithmetic and logic operations. These are used in automatically controlled devices including implantable medical devices, engine control systems, office machines, appliances and other types of embedded systems. Some examples are Intel/Atmel 251 family, PIC3x.  KEY DIFFERENCES: Microprocessor Vs Microcontroller Microprocessor consists of only a Central Processing Unit, whereas Micro Controller contains a CPU, Memory, I/O all integrated into one chip. Microprocessor is used in Personal Computers whereas Micro Controller is used in an embedded system. Microprocessor uses an external bus to interface to RAM, ROM, and other peripherals, on the other hand, Microcontroller uses an internal controlling bus. Microprocessors are based on Von Neumann model Micro controllers are based on Harvard architecture.(When data and code lie in different memory blocks, then the architecture is referred as Harvard architecture. In case data and code lie in the same memory block, then the architecture is referred as Von Neumann architecture. ) Microprocessor is complicated and expensive, with a large number of instructions to process but Microcontroller is inexpensive and straightforward with fewer instructions to process. Reference and suggested reaading: https://en.wikipedia.org/wiki/List_of_common_mic rocontrollers Instruction set of 8086 Compiled by Mrs. Savita C. Raut The Instruction set of 8086 microprocessor is classified into : 1. Data transfer instructions 2. Arithmetic instructions 3. Bit Manipulation instructions 4. String instructions 5. Program control transfer instructions 6. Process control instructions  Data transfer instructions A. General purpose instructions: MOV − Used to copy the byte or word from the provided source to the provided destination. PUSH − Used to put a word at the top of the stack. POP − Used to get a word from the top of the stack to the provided location. XCHG − Used to exchange the data from two locations. XLAT − Used to translate a byte in AL using a table in the memory.  Data transfer instructions..cntd B. Instructions for input and output port transfer IN − Used to read a byte or word from the provided port to the accumulator. OUT − Used to send out a byte or word from the accumulator to the provided port. C. Instructions to transfer the address LEA − Used to load the address of operand into the provided register. LDS − Used to load DS register and other provided register from the memory LES − Used to load ES register and other provided register from the memory.  Data transfer instructions..cntd D. Instructions to transfer flag registers LAHF − Used to load AH with the low byte of the flag register. SAHF − Used to store AH register to low byte of the flag register. PUSHF − Used to copy the flag register at the top of the stack. POPF − Used to copy a word at the top of the stack to the flag register.  MOV destination,Source Copies a word or byte from source to destination No flags are affected Any addressing mode is possible except implied. Valid source and destination pairs Destination Source Register Register Memory register Register Memory Register Immediate Memory Immediate Seg. Register Register (16-bit) Register (16-bit) Seg. Register Seg. Register Memory Memory Seg. Register # can not set the value of CS and IP  MOV instruction Note: Following data transfers are invalid Memory to Memory Destination can not be Immediate Segment register to Segment Register Immediate data to segment register Examples: Mov Ax,Bx Mov Ax,[SI] Mov [DI],Bx Mov DS, Ax Mov ES,[1234h] etc  Instruction :POP Destination This instruction copies a word from memory location pointed by SS:SP to the destination. When it is executed: I. Data from memory location (in stack segment) SS:SP is first copied to the destination II. And then SP is incremented by 2 (SP=SP+2) Note : destination can be a general purpose register,Flag register ,segment register or memory location. EX: POP AX POP DS  Instruction :PUSH Source When this instruction is executed: i) SP=SP-2 (i.e. First SP is decremented by 2 ) ii) Copy the word from source register to the location in Stack Segment where SP points. Note :1.Source operand (16-bit) can be a general purpose register,Flag register ,segment register or memory. 2. Addressing mode – register Indirect EX: PUSH Ax PUSH BX PUSH DS Port related instructions:IN and OUT Port related instructions:IN and OUT Conditional Transfer Arithmetic Instructions String related instructions String instructions..cntd This instruction copies a byte/word from a location in Data Segment to a location in Extra Segment String instructions..cntd This instruction compares a byte/word from a location in Data Segment to a location in Extr a Segment String instructions..cntd String instructions..cntd String instructions..cntd  String instructions-Summary STOSB AL=>ES:[DI] After string opr, if DF = 0, then DI is incremented by 1 and viceversa LODSB ALES:[DI] After string opr, if DF = 0, then SI and DI is incremented by 1 and viceversa SCASB AL – ES:[DI] After string opr, if DF = 0, then DI is incremented by 1 and viceversa CMPSB DS:[SI] – ES:[DI] After string opr, if DF = 0, then SI and DI is incremented by 1 and viceversa  Prefix:REP String instructions can handle at a time one byte or one word, but to handle large block of data, REP prefix is used with CX as a counter Types REP dec CX by 1 and repeat that string instruction if CX is non zero. Otherwise control continues sequentially REPNE/REPNZ dec CX by 1 and repeat that string instruction if CX is non zero AND if that string inst. Produced non – zero result. Otherwise control continues sequentially REPE/REPZ dec CX by 1 and repeat that string instruction if CX is non zero AND if that string inst. Produced zero result. Otherwise control continues sequentially  LOOP Instruction It is used to execute series of instructions for a given number of times and that number of times is stored in CX Types LOOP AGAIN dec CX by 1 and transfer control to the instruction having label AGAIN if CX is non zero. Otherwise control continues sequentially LOOPNE/LOOPNZ dec CX by 1 and transfer control to the instruction having label AGAIN if CX is non zero AND if previous instruction produced non zero result. Otherwise control continues sequentially LOOPE/LOOPZ dec CX by 1 and transfer control to the instruction having label AGAIN if CX is non zero AND if previous instruction produced zero result. Otherwise control continues sequentially  Sample Program: Problem statement – clear the contents of three memory location Memory content location 62380 00 62381 00 62382 00  Using MOV instruction MOV AX,6000H move 6000h into AX MOV DS,AX move AX contents into DS MOV DI,2380H move 2380H into DI MOV CX,0003H move 0003H into CX MOV AL,00H move 00H into AL Again MOV [DI],AL AL => DS:[DI] INC DI Increment the contents of DI DEC CX JNZ AGAIN dec CX, and if CX is NZ go to again HLT Halt  Using Loop instruction MOV AX,6000H move 6000h into AX MOV DS,AX move AX contents into DS MOV DI,2380H move 2380H into DI MOV CX,0003H move 0003H into CX MOV AL,00H move 00H into AL Again MOV [DI],AL AL => DS:[DI} INC DI Increment the contents of DI LOOP AGAIN dec CX, and if CX is NZ go to again HLT Halt  Using string instructions (Use of Prefix) MOV AX,6000H move 6000h into AX MOV ES,AX move AX contents into ES MOV DI,2380H move 2380H into DI CLD clear the direction flag MOV CX,0003H move 0003H into CX MOV AL,00H move 00H into AL REP STOSB AL => ES:[DI]and increment DI (rep this CX times) HLT Halt  Prog 2:Problem statement block transfer Transfer contents of 52500 to 62500 and 52501 to 62501  Block transfer MOV AX,5000 H MOV DS,AX MOV AX,6000H MOV ES,AX MOV SI,2500H MOV DI,2500H CLD MOV CX,0002H REP MOVSB DS:[SI] =>ES:[DI] and increment DI and SI (rep this CX times) HLT  FIND THE GIVEN BYTE 03 IN AN ARRAY Memory location Content 2000:0500 78 h MOV AX,2000H 2000:0501 19 h MOV ES,AX 2000:0502 65 h 2000:0503 45 h MOV DI,0500H 2000:0504 03 h MOV CX,0006 2000:0505 32 h MOV AL, 03 2000:0506 13 h CLD 2000:0507 26 h REPNE SCASB DEC DI hlt  Shift Instructions Shift instructions move the binary data to the left or right by shifting them within the register or memory location. They also can perform multiplication of powers of 2+𝑛 and division of powers of 2−𝑛 There are two type of shifts logical shifting and arithmetic shifting, later is used with signed numbers while former with unsigned. Shift instruction General Format: SHR destination, count Rotate Instructions ROR – ROTATE RIGHT (LSB INTO CARRY AND MSB AND OTHER BITS SHIFT TO RIGHT) ROL- ROTATE LEFT (MSB INTO CARRY AND LSB AND OTHER BITS SHIFT TO LEFT) RCR - ROTATE RIGHT THRU CARRY (LSB INTO CARRY AND CARRY INTO MSB AND OTHER BITS SHIFT TO RIGHT) RCL - ROTATE LEFT THRU CARRY (MSB INTO CARRY AND CARRY INTO LSB AND OTHER BITS SHIFT TO LEFT) FORMAT FOR EXAMPLE: RCR BX,01 RCR BX,CL (If shifting is to be done more than once, count has to be stored in CL)  Program: to count the Zero ,positive, negative numbers MOV AX, 0000 MOV DS, AX MOV BX, D000 If MSB =1,then Negative no. MOV CL, [BX] MOV DX, 0000 If MSB=0 ,then positive no. MOV AH, 00 UP: INC BX Reg Dh -- Zeros MOV AL, [BX] ADD AL, 00 Reg Dl – positive no.s JNZ DOWN1 INC DH Reg Ah-negative no.s JMP DOWN 3 DOWN1: RCL AL, 01 JNC DOWN2 INC AH JMP DOWN3 DOWN2: INC DL DOWN3: DEC CL JNZ UP INT 3  Introduction to Microprocessor 8086 Savita C. Raut EXTC Department  Contents : Architecture of 8086 microprocessor Register organization 8086 flag register and its functions Addressing modes of 8086 Pin diagram of 8086 Minimum mode & Maximum mode system Timing diagrams  8086 Microprocessor features 1. It is 16-bit microprocessor 2. It has a 16-bit data bus, so it can read data from or write data to memory and ports either 16-bit or 8-bit at a time. 3. It has 20 bit address bus and can access up to 220 memory locations (1 MB). 4. It can support up to 64K I/O ports 5. It provides 14, 16-bit registers 6. It has multiplexed address and data bus AD0-AD15 & A16-A19 7. It requires single phase clock with 33% duty cycle to provide internal timing. 8. Pre-fetches up to 6 instruction bytes from memory and queues them in order to speed up the processing. 9. 8086 supports 2 modes of operation a. Minimum mode b. Maximum mode  Architecture of 8086 microprocessor: As shown in the below figure, the 8086 CPU is divided into two independent functional parts o Bus Interface Unit(BIU) o Execution Unit(EU) Dividing the work between these two units’ speeds up processing. Architecture of 8086 microprocessor  The execution unit (EU) The execution unit of the 8086 tells the BIU where to fetch instructions or data from, decodes instructions,and executes instructions. The EU contains control circuitry, which directs internal operations. A decoder in the EU translates instructions fetched from memory into a series of actions, which the EU carries out. The EU has a 16-bit arithmetic logic unit (ALU) which can add, subtract, AND, OR, XOR, increment, decrement,complement or shift binary numbers. The main functions of EU are: Decoding of Instructions Execution of instructions  Cntd..EU The main functions of EU are: o Decoding of Instructions o Execution of instructions Steps  EU extracts instructions from the queue in BIU  Decode the instructions  Generates operands if necessary  Passes operands to BIU & requests it to perform read or write bus cycles to memory or I/O  Perform the operation specified by the instruction on operands  Bus Interface Unit (BIU) The BIU sends out addresses, fetches instructions from memory, reads data from ports and memory, and writes data to ports and memory. In simple words, the BIU handles all transfers of data and addresses on the buses for the execution unit.  8086 HAS PIPELINING ARCHITECTURE: While the EU is decoding an instruction or executing an instruction, which does not require use of the buses,the BIU fetches up to six instruction bytes for the following instructions. The BIU stores these pre-fetched bytes in a first-in-first-out register set called a queue. When the EU is ready for its next instruction from the queue in the BIU. This is much faster than sending out an address to the system memory and waiting for memory to send back the next instruction byte or bytes. Except in the case of JMP and CALL instructions, where the queue must be dumped and then reloaded starting from a new address, this pre-fetch and queue scheme greatly speeds up processing. Fetching the next instruction while the current instruction executes is called pipelining.  Register organization: 8086 has a powerful set of registers known as general purpose registers and special purpose registers. All of them are 16-bit registers. General purpose registers: o These registers can be used as either 8-bit registers or 16-bit registers. o They may be either used for holding data, variables and intermediate results temporarily or for other purposes like a counter or for storing offset address for some particular addressing modes etc. Special purpose registers: o These registers are used as segment registers, pointers, index registers or as offset storage registers for particular addressing modes. The 8086 registers are classified into the following types: o General Data Registers o Segment Registers o Pointers and Index Registers o Flag Register  General Data Registers: The registers AX, BX, CX and DX are the general purpose 16- bit registers. AX is used as 16-bit accumulator. The lower 8-bit is designated as AL and higher 8-bit is designated as AH. ALcan be used as an 8-bit accumulator for 8-bit operation. All data register can be used as either 16 bit or 8 bit. BX is a 16 bit register, but BL indicates the lower 8-bit of BX and BH indicates the higher 8-bit of BX. The register BX is used as offset storage for forming physical address in case of certain addressing modes. The register CX is used default counter in case of string and loop instructions. DX register is a general purpose register which may be used as an implicit operand or destination in case of a few instructions  Segment Registers: There are 4 segment registers: o Code Segment Register(CS) o Data Segment Register(DS) o Extra Segment Register(ES) o Stack Segment Register(SS) The 8086 architecture uses the concept of segmented memory. 8086 able to address a memory capacity of 1 Megabyte and it is byte organized. This 1 megabyte memory is divided into 16 logical segments. Each segment contains 64 k bytes of memory. Code segment register (CS): is used for addressing memory location in the code segment of the memory,where the executable program is stored. Data segment register (DS): points to the data segment of the memory where the data is stored.  Segment Registers: Extra Segment Register (ES) : also refers to a segment in the memory which is another data segment in the memory. Stack Segment Register (SS): is used for addressing stack segment of the memory. The stack segment is that segment of memory which is used to store stack data. While addressing any location in the memory bank, the physical address is calculated from two parts: Physical address= segment address + offset address The first is segment address, the segment registers contain 16-bit segment base addresses, related to different segment. The second part is the offset value in that segment.  Pointers and Index Registers: The index and pointer registers are given below: o IP—Instruction pointer-store memory location of next instruction to be executed o BP—Base pointer o SP—Stack pointer o SI—Source index o DI—Destination index The pointers registers contain offset within the particular segments. The pointer register IP contains offset within the code segment. The pointer register BP and SP contains offset within the stack segment.  Pointers and Index Registers…cntd.. The index registers are used as general purpose registers as well as for offset storage in case of indexed, base indexed and relative base indexed addressing modes. The register SI is used to store the offset of source data in data segment. The register DI is used to store the offset of destination in data or extra segment. The index registers are particularly useful for string manipulation. Flag registor  flag register and its functions: The 8086 flag register contents indicate the results of computation in the ALU. It also contains some flag bits to control the CPU operations. A 16 bit flag register is used in 8086. It is divided into two parts. o Condition code or status flags o Machine control flags The condition code flag register is the lower byte of the 16-bit flag register. The condition code flag register is identical to 8085 flag register, with an additional overflow flag. The control flag register is the higher byte of the flag register. It contains three flags namely direction flag (DF),interrupt flag (IF) and trap flag (TF).  Cntd.. Flag register SF- Sign Flag: This flag is set, when the result of any computation is negative. For signed computations the sign flag equals the MSB of the result. ZF- Zero Flag: This flag is set, if the result of the computation or comparison performed by the previous instruction is zero. PF- Parity Flag: This flag is set to 1, if the lower byte of the result contains even number of 1’s. CF- Carry Flag: This flag is set, when there is a carry out of MSB in case of addition or a borrow in case of subtraction. AF-Auxilary Carry Flag: This is set, if there is a carry from the lowest nibble, i.e, bit three during addition, or borrow for the lowest nibble, i.e, bit three, during subtraction.  OF- Over flow Flag: This flag is set, if an overflow occurs, i.e, if the result of a signed operation is large enough to accommodate in a destination register. The result is of more than 7-bits in size in case of 8-bit signed operation and more than 15-bits in size in case of 16-bit sign operations, and then the overflow will be set. TF- Tarp Flag: If this flag is set, the processor enters the single step execution mode. The processor executes the current instruction and the control is transferred to the Trap interrupt service routine.  Cntd.. Flag register IF- Interrupt Flag: If this flag is set, the mask able interrupts are recognized by the CPU, otherwise they are ignored. D- Direction Flag: This is used by string manipulation instructions. If this flag bit is ‘0’, the string is processed beginning from the lowest address to the highest address, i.e., auto incrementing mode. Otherwise, the string is processed from the highest address towards the lowest address, i.e., auto decrementing mode.  Memory Segmentation The memory in an 8086 based system is organized as segmented memory. The CPU 8086 is able to access 1MB of physical memory. The complete 1MB of memory can be divided into 16 segments, each of 64KB size and is addressed by one of the segment register. The 16-bit contents of the segment register actually point to the starting location of a particular segment. The address of the segments may be assigned as 0000H to F000h respectively. To address a specific memory location within a segment, we need an offset address. The offset address values are from 0000H to FFFFH so that the physical addresses range from 00000H to FFFFFH. Physical address is calculated as below: Ex: Segment address ------- 1005H Offset address ----------5555H Segment address -------1005H ----- 0001 0000 0000 0101 Shifted left by 4 Positions------ 0001 0000 0000 0101 0000 + Offset address --- 5555H ------ 0101 0101 0101 0101 Physical address -------155A5H 0001 0101 0101 1010 0101 Physical address = Segment address * 10H + Offset address. The main advantages of the segmented memory scheme are as follows: 1. Allows the memory capacity to be 1MB although the actual addresses to be handled are of 16-bit size. 2. Allows the placing of code, data and stack portions of the same program in different parts (segments) of memory, for data and code protection. 3. Permits a program and/or its data to be put into different areas of memory each time the program is executed, i.e., provision for relocation is done. Overlapping and Non-Overlapping Segments Segment register-Offset register pairs  8051 Interrupts Compiled by-SCR Interrupts 1  INTERRUPTS An interrupt is an external or internal event that interrupts the microcontroller to inform it that a device needs its service A single microcontroller can serve several devices by two ways: 1. Interrupt 2. Polling Interrupts 2  Interrupt Vs Polling 1. Interrupts – Whenever any device needs its service, the device notifies the microcontroller by sending it an interrupt signal. – Upon receiving an interrupt signal, the microcontroller interrupts whatever it is doing and serves the device. – The program which is associated with the interrupt is called the interrupt service routine (ISR) or interrupt handler. 2. Polling – The microcontroller continuously monitors the status of a given device. – When the conditions met, it performs the service. – After that, it moves on to monitor the next device until every one is serviced. Interrupts 3  Interrupt Vs Polling The polling method is not efficient, since it wastes much of the microcontroller’s time by polling devices that do not need service. The advantage of interrupts is that the microcontroller can serve many devices (not all at the same time). Each devices can get the attention of the microcontroller based on the assigned priority. For the polling method, it is not possible to assign priority since it checks all devices in a round-robin fashion. The microcontroller can also ignore (mask) a device request for service in Interrupt. Interrupts 4  Steps in Executing an Interrupt 1. It finishes the instruction it is executing and saves the address of the next instruction (PC) on the stack. 2. It also saves the current status of all the interrupts internally (i.e: not on the stack). 3. It jumps to a fixed location in memory, called the interrupt vector table, that holds the address of the ISR. 4. The microcontroller gets the address of the ISR from the interrupt vector table and jumps to it. 5. It starts to execute the interrupt service subroutine until it reaches the last instruction of the subroutine which is RETI (return from interrupt). 6. Upon executing the RETI instruction, the microcontroller returns to the place where it was interrupted. Interrupts 5  Six Interrupts in 8051 Six interrupts are allocated as follows: 1. Reset – power-up reset. 2. Two interrupts are set aside for the timers. – one for timer 0 and one for timer 1 3. Two interrupts are set aside for hardware external interrupts. – P3.2 and P3.3 are for the external hardware interrupts INT0 (or EX1), and INT1 (or EX2) 4. Serial communication has a single interrupt that belongs to both receive and transfer. Interrupts 6  What events can trigger Interrupts? We can configure the 8051 so that any of the following events will cause an interrupt: – Timer 0 Overflow. – Timer 1 Overflow. – Reception/Transmission of Serial Character. – External Event 0. – External Event 1. We can configure the 8051 so that when Timer 0 Overflows or when a character is sent/received, the appropriate interrupt handler routines are called. Interrupts 7  8051 Interrupt Vectors Interrupts 8  8051 Interrupt related Registers The various registers associated with the use of interrupts are: – TCON - Edge and Type bits for External Interrupts 0/1 – SCON - RI and TI interrupt flags for RS232 – IE - Enable interrupt sources – IP - Specify priority of interrupts Interrupts 9  Enabling and Disabling an Interrupt Upon reset, all interrupts are disabled (masked), meaning that none will be responded to by the microcontroller if they are activated. The interrupts must be enabled by software in order for the microcontroller to respond to them. There is a register called IE (interrupt enable) that is responsible for enabling (unmasking) and disabling (masking) the interrupts. Interrupts 10  Interrupt Enable (IE) Register -- EA : Global enable/disable. If EA = 0 ,all the interrupts are disabled. If EA=1 ,each interrupt is individually enabled or disabled. MOV IE,#08h --- : Reserved for additional interrupt hardware. or SETB ET1 ES : Enable Serial port interrupt. ET1 : Enable Timer 1 control bit. EX1 : Enable External 1 interrupt. ET0 : Enable Timer 0 control bit. Interrupts 11 EX0 : Enable External 0 interrupt.  Enabling and Disabling an Interrupt Example: Show the instructions to (a) enable the serial interrupt, timer 0 interrupt, and external hardware interrupt 1 and (b) disable (mask) the timer 0 interrupt, then (c) show how to disable all the interrupts with a single instruction. Solution: – (a) MOV IE,#10010110B ;enable serial, timer 0, EX1 Another way to perform the same manipulation is: – SETB IE.7 ;EA=1, global enable – SETB IE.4 ;enable serial interrupt – SETB IE.1 ;enable Timer 0 interrupt – SETB IE.2 ;enable EX1 – (b) CLR IE.1 ;mask (disable) timer 0 interrupt only – (c) CLR IE.7 ;disable all interrupts Interrupts 12  Interrupt Priority When the 8051 is powered up, the priorities are assigned according to the following. In reality, the priority scheme is nothing but an internal polling sequence in which the 8051 polls the interrupts in the sequence listed and responds accordingly. Interrupts 13  Interrupt Priority We can alter the sequence of interrupt priority by assigning a higher priority to any one of the interrupts by programming a register called IP (interrupt priority). To give a higher priority to any of the interrupts, we make the corresponding bit in the IP register high. Interrupts 14  Interrupt Priority (IP) Register Reserved PS PT1 PX1 PT0 PX0 Serial Port INT 0 Pin Timer 1 Pin INT 1 Pin Timer 0 Pin Priority bit=1 assigns high priority Priority bit=0 assigns low priority Interrupts 15  Programming the Timer Interrupts Interrupts 16 Interrupts 17 Interrupts 18  PROGRAMMING EXTERNAL HARDWARE INTERRUPTS There are only two external hardware interrupts in the 8051: INTO and INT1. They are located on pins P3.2 and P3.3 of port 3, respectively. The interrupt vector table locations 0003H and 0013H are set aside for INTO and INT1, respectively. They are enabled and disabled using the IE register. There are two types of activation for the external hardware interrupts: (1) level triggered, and (2) edge triggered. 1)Level triggered Interrupts In the level-triggered mode, INTO and INT1 pins are normally high and if a low-level signal is applied to them, it triggers the interrupt. Then the microcontroller stops whatever it is doing and jumps to the interrupt vector table to service that interrupt. This is called a level-triggered or level-activated interrupt and is the default mode upon reset of the 8051. Interrupts 19  PROGRAMMING EXTERNAL HARDWARE INTERRUPTS..cntd The low-level signal at the INT pin must be removed before the execution of the last instruction of the interrupt service routine, RETI; otherwise, another interrupt will be generated. In other words, if the low-level interrupt signal is not removed before the ISR is finished it is interpreted as another interrupt and the 8051 jumps to the vector table to execute the ISR again. After the hardware interrupts in the IE register are enabled, the controller keeps sampling the INT pin for a low-level signal once each machine cycle. According to one manufacturer’s data sheet “the pin must be held in a low state until the start of the execution of ISR. If the INTn pin is brought back to a logic high before the start of the execution of ISR there will be no interrupt.” However, upon activation of the interrupt due to the low level, it must be brought back to high before the execution of RETI. Interrupts 20  PROGRAMMING EXTERNAL HARDWARE INTERRUPTS..cntd Again, according to one manufacturer’s data sheet, “If the INT pin is left at a logic low after the RETI instruction of the ISR, another interrupt will be activated after one instruction is executed.” Therefore, to ensure the activation of the hardware interrupt at the INT pin, make sure that the duration of the low-level signal is around 4 machine cycles, but no more. This is due to the fact that the level- triggered interrupt is not latched. Thus the pin must be held in a low state until the start of the ISR execution. Figure : Minimum Duration of the Low Level-Triggered Interrupt (XTAL = 11.0592 MHz) Interrupts 21  PROGRAMMING EXTERNAL HARDWARE INTERRUPTS..cntd 2) Edge-triggered Interrupts As stated before, upon reset the 8051 makes INTO and INT1 low- level triggered interrupts. To make them edge-triggered interrupts, we must program the bits of the TCON register. The ITO and IT1 flag bits of TCON register determine level- or edge- triggered mode of the hardware interrupts. They are referred to as TCON.O and TCON.2 (TCON register is bit-addressable). By making the TCON.O and TCON.2 bits high with instructions such as “SETB TCON. 0″ and “SETB TCON. 2″, the external hardware interrupts of INTO and INT1 become edge-triggered. For example, the instruction “SETB CON. 2″ makes INT1 what is called an edge- triggered interrupt, in which, when a high-to-low signal is applied to pin P3.3, in this case, the controller will be interrupted and forced to jump to location 0013H in the vector table to service the ISR (assuming that the interrupt bit is enabled in the IE register). Interrupts 22 PROGRAMMING EXTERNAL HARDWARE..INTERRUPTS..cntd IE1 TCON.3 External interrupt 1 edge flag. Set by CPU when the external interrupt edge (H-to-L transition) is detected. Cleared by CPU when the interrupt is processed. Note: This flag does not latch low-level triggered interrupts. IT1 TCON.2 Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low-level triggered external interrupt. IE0 TCON.1 External interrupt 0 edge flag. Set by CPU when external interrupt (H-to-L transition) edge is detected. Cleared by CPU when interrupt is processed. Note: This flag does not latch low-level triggered interrupts. IT0 TCON.0 Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low-level triggered external interrupt. Interrupts 23 PROGRAMMING EXTERNAL HARDWARE..INTERRUPTS..cntd In edge-triggered interrupts, the external source must be held high for at least one machine cycle, and then held low for at least one machine cycle to ensure that the transition is seen by the microcontroller. The falling edge is latched by the 8051 and is held by the TCON register. The TCON. 1 and TCON.3 bits hold the latched falling edge of pins INTO and INT1, respectively. TCON.l and TCON.3 are also called IEO and IE1, respectively, as shown in Figure 11-6. They function as interrupt-in-service flags. When an interrupt-in-service flag is raised, it indicates to the external world that the interrupt is being serviced and no new interrupt on this INTw pin will be responded to until this service is finished. Interrupts 24  PROGRAMMING THE SERIAL COMMUNICATION INTERRUPT (interrupt-based serial communication) TI (transfer interrupt) is raised when the last bit of the framed data, the stop bit, is transferred, indicating that the SBUF register is ready to transfer the next byte. RI (received interrupt), is raised when the entire frame of data, including the stop bit, is received. In other words, when the SBUF register has a byte, RI is raised to indicate that the received byte needs to be picked up before it is lost (overrun) by new incoming serial data. In the polling method, we wait for the flag (TI or RI) to be raised; while we wait we cannot do anything else. In the interrupt method, we are notified when the 8051 has received a byte, or is ready to send the next byte; we can do other things while the serial communication needs are served. 25 Interrupts  PROGRAMMING THE SERIAL COMMUNICATION INTERRUPT (interrupt-based serial communication) In the 8051 only one interrupt is set aside for serial communication. This interrupt is used to both send and receive data. If the interrupt bit in the IE register (IE.4) is enabled, when RI or TI is raised the 8051 gets interrupted and jumps to memory address location 0023H to execute the ISR. In that ISR we must examine the TI and RI flags to see which one caused the interrupt and respond accordingly. 26 Interrupts  PROGRAMMING THE SERIAL COMMUNICATION INTERRUPT (interrupt-based serial communication) Use of serial COM in the 8051 In the vast majority of applications, the serial interrupt is used mainly for receiving data and is never used for sending data serially. This is like receiving a telephone call, where we need a ring to be notified. If we need to make a phone call there are other ways to remind ourselves and so no need for ringing.. In receiving the phone call, however, we must respond immediately no matter what we are doing or we will miss the call. Similarly, we use the serial interrupt to receive incoming data so that it is not lost. 27 Interrupts Write a program in which the 8051 reads data from PI and writes it to P2 continuously while giving a copy of it to the serial COM port to be transferred serially. Assume that XTAL = 11.0592 MHz. Set the baud rate at 9600. Interrupts 28 Clearing RI and TI before the RETI instruction Notice in this Example that the last instruction before the RETI is the clearing of the RI or TI flags. This is necessary since there is only one interrupt for both receive and transmit, and the 8051 does not know who generated it; therefore, it is the job of the ISR to clear the flag. Contrast this with the external and timer interrupts where it is the job of the 8051 to clear the interrupt flags. Interrupts 29 Write a program in which the 8051 gets data from PI and sends it to P2 continuously while incoming data from the serial port is sent to PO. Assume that XTAL = 11.0592 MHz. Set the baud rate at 9600. Interrupts 30 8051 Microcontroller Compiled by Prof. Mrs. Savita Raut Microprocessor Vs Microcontroller Generalized block diagram of microcontroller  Features of 8051 Microcontroller 4KB bytes on-chip program memory (ROM) 128 bytes on-chip data memory (RAM) Four register banks 128 user defined software flags 8-bit bidirectional data bus 16-bit unidirectional address bus 32 general purpose registers each of 8-bit 16 bit Timers (usually 2, but may have more or less) Three internal and two external Interrupts Four 8-bit ports,(short model have two 8-bit ports) 16-bit program counter and data pointer 8051 may also have a number of special features such as UARTs, ADC, Op-amp, etc. Pin Diagram of 8051  In 8051, I/O operations are done using four ports and 40 pins. The pin diagram shows the details of the 40 pins. I/O operation port reserves 32 pins where each port has 8 pins. The other 8 pins are designated as Vcc, GND, XTAL1, XTAL2, RST, EA (bar), ALE/PROG (bar), and PSEN.  I/O Ports and their Functions The four ports P0, P1, P2, and P3, each use 8 pins, making them 8-bit ports. Upon RESET, all the ports are configured as inputs, ready to be used as input ports. When the first 0 is written to a port, it becomes an output. To reconfigure it as an input, a 1 must be sent to a port. Port 0 (Pin No 32 – Pin No 39) It has 8 pins (32 to 39). It can be used for input or output. Unlike P1, P2, and P3 ports, we normally connect P0 to 10K-ohm pull-up resistors to use it as an input or output port being an open drain. It is also designated as AD0-AD7, allowing it to be used as both address and data. Port 1 (Pin 1 through 8) It is an 8-bit port (pin 1 through 8) and can be used either as input or output. It doesn't require pull-up resistors because they are already connected internally. Upon reset, Port 1 is configured as an input port. Port 2 (Pins 21 through 28) Port 2 occupies a total of 8 pins (pins 21 through 28) and can be used for both input and output operations. Just as P1 (Port 1), P2 also doesn't require external Pull- up resistors because they are already connected internally. It must be used along with P0 to provide the 16-bit address for the external memory. So it is also designated as (A0–A7), as shown in the pin diagram. When the 8051 is connected to an external memory, it provides path for upper 8-bits of 16-bits address, and it cannot be used as I/O. Upon reset, Port 2 is configured as an input port.  Dual Role of Port 0 and Port 2 Dual role of Port 0 − Port 0 is also designated as AD0–AD7, as it can be used for both data and address handling. While connecting an 8051 to external memory, Port 0 can provide both address and data. The 8051 microcontroller then multiplexes the input as address or data in order to save pins. Dual role of Port 2 − Besides working as I/O, Port P2 is also used to provide 16-bit address bus for external memory along with Port 0. Port P2 is also designated as (A8– A15), while Port 0 provides the lower 8-bits via A0–A7. In other words, we can say that when an 8051 is connected to an external memory (ROM) which can be maximum up to 64KB and this is possible by 16 bit address bus. Port2 is used for the upper 8-bit of the 16 bits address, and it cannot be used for I/O and this is the way any Program code of external ROM is addressed.  Hardware Connection of Pins Vcc − Pin 40 provides supply to the Chip and it is +5 V. Gnd − Pin 20 provides ground for the Reference. XTAL1, XTAL2 (Pin no 18 & Pin no 19) − 8051 has on-chip oscillator but requires external clock to run it. A quartz crystal is connected between the XTAL1 & XTAL2 pin of the chip. This crystal also needs two capacitors of 30pF for generating a signal of desired frequency. One side of each capacitor is connected to ground. 8051 IC is available in various speeds and it all depends on this Quartz crystal, for example, a 20 MHz microcontroller requires a crystal with a frequency no more than 20 MHz.  RST (Pin No. 9) − It is an Input pin and active High pin. Upon applying a high pulse on this pin, that is 1, the microcontroller will reset and terminate all activities. This process is known as Power-On Reset. Activating a power-on reset will cause all values in the register to be lost. It will set a program counter to all 0's. To ensure a valid input of Reset, the high pulse must be high for a minimum of two machine cycles before it is allowed to go low, which depends on the capacitor value and the rate at which it charges. (Machine Cycle is the minimum amount of frequency a single instruction requires in execution). EA or External Access (Pin No. 31) − It is an input pin. This pin is an active low pin; upon applying a low pulse, it gets activated. In case of microcontroller (8051/52) having on-chip ROM, the EA (bar) pin is connected to Vcc. But in an 8031 microcontroller which does not have an on-chip ROM, the code is stored in an external ROM and then fetched by the microcontroller. In this case, we must connect the (pin no 31) EA to Gnd to indicate that the program code is stored externally.  PSEN or Program store Enable (Pin No 29) − This is also an active low pin, i.e., it gets activated after applying a low pulse. It is an output pin and used along with the EA pin in 8031 based (i.e. ROMLESS) Systems to allow storage of program code in external ROM. ALE or (Address Latch Enable) − This is an Output Pin and is active high. It is especially used for 8031 IC to connect it to the external memory. It can be used while deciding whether P0 pins will be used as Address bus or Data bus. When ALE = 1, then the P0 pins work as Data bus and when ALE = 0, then the P0 pins act as Address bus. I/O Ports and Bit Addressability Internal block diagram of 8051  An 8051 microcontroller has the following 12 major components: 1. ALU (Arithmetic and Logic Unit) 2. PC (Program Counter) 3. Registers 4. Timers and counters 5. Internal RAM and ROM 6. Four general purpose parallel input/output ports 7. Interrupt control logic with five sources of interrupt 8. Serial date communication 9. PSW (Program Status Word) 10. Data Pointer (DPTR) 11. Stack Pointer (SP) 12. Data and Address bus. 1. ALU All arithmetic and logical functions are carried out by the ALU. Addition, subtraction with carry, and multiplication come under arithmetic operations. Logical AND, OR and exclusive OR (XOR) come under logical operations. 2. Registers Registers are usually known as data storage devices. 8051 microcontroller has 2 registers, namely Register A and Register B. Register A serves as an accumulator while Register B functions as a general purpose register. These registers are used to store the output of mathematical and logical instructions. The operations of addition, subtraction, multiplication and division are carried out by Register A. Register B is used for multiplication and division operations. Register A also involved in data transfers between the microcontroller and external memory.  Registers 8051 microcontroller also has 7 Special Function Registers (SFRs). They are: 1. Serial Port Data Buffer (SBUF) 2. Timer/Counter Control (TCON) 3. Timer/Counter Mode Control (TMOD) 4. Serial Port Control (SCON) 5. Power Control (PCON) 6. Interrupt Priority (IP) 7. Interrupt Enable Control (IE)  Timers and Counters The 8051 has two counters/timers which can be used either as timer to generate a time delay or as counter to count events happening outside the microcontroller. The 8051 has two timers: timer0 and timer1. They can be used either as timers or as counters. Both timers are 16 bits wide. Since the 8051 has an 8-bit architecture, each 16-bit is accessed as two separate registers of low byte and high byte. Timer 0 registers is a 16 bits register and accessed as low byte and high byte. The low byte is referred as a TL0 and the high byte is referred as TH0. These registers can be accessed like any other registers. Timer 0  Timer 1 Timer1 registers is also a 16 bits register and is split into two bytes, referred to as TL1 and TH1.  TMOD (timer mode) Register This is an 8-bit register which is used by both timers 0 and 1 to set the various timer modes. In this TMOD register, lower 4 bits are set aside for timer0 and the upper 4 bits are set aside for timer1. In each case, the lower 2 bits are used to set the timer mode and upper 2 bits to specify the operation.  TMOD 1. In upper or lower 4 bits, first bit is a GATE bit. Every timer has a means of starting and stopping. Some timers do this by software, some by hardware, and some have both software and hardware controls. The hardware way of starting and stopping the timer by an external source is achieved by making GATE=1 in the TMOD register. And if we change to GATE=0 then we do not need external hardware to start and stop the timers. 2. The second bit is C/T bit and is used to decide whether a timer is used as a time delay generator or an event counter. If this bit is 0 then it is used as a timer and if it is 1 then it is used as a counter.  TMOD In upper or lower 4 bits, the last bits third and fourth are known as M1 and M0 respectively. These are used to select the timer mode. M1 M0 Mode 0 0 0 13-bit timer mode, 8-bit timer/counter THx and TLx as 5-bit 0 1 1 16-bit timer mode, 16-bit timer/counters THx and TLx are cascaded 1 0 2 8-bit auto reload mode, 8-bit auto reload timer/counter; THx holds a value which is to be reloaded into TLx each time it overflows. 1 1 3 Spilt timer mode.  Mode 1 Mode 1- It is a 16-bit timer; therefore it allows values from 0000 to FFFFH to be loaded into the timer’s registers TL and TH. After TH and TL are loaded with a 16-bit initial value, the timer must be started. We can do it by “SETB TR0” for timer 0 and “SETB TR1” for timer 1. After the timer is started. It starts count up until it reaches its limit of FFFFH. When it rolls over from FFFF to 0000H, it sets high a flag bit called TF (timer flag). This timer flag can be monitored. When this timer flag is raised, one option would be stop the timer with the instructions “CLR TR0“ or CLR TR1 for timer 0 and timer 1 respectively. Again, it must be noted that each timer flag TF0 for timer 0 and TF1 for timer1. After the timer reaches its limit and rolls over, in order to repeat the process the registers TH and TL must be reloaded with the original value and TF must be reset to 0  Mode 0 Mode 0 Mode 0 is exactly same like mode 1 except that it is a 13-bit timer instead of 16-bit. The 13-bit counter can hold values between 0000 to 1FFFH in TH-TL. Therefore, when the timer reaches its maximum of 1FFH, it rolls over to 0000, and TF is raised.  Mode 2 Mode 2- It is an 8 bit timer that allows only values of between 00 to FFH to be loaded into the timer’s register TH. After TH is loaded with 8 bit value, the 8051 gives a copy of it to TL. Then the timer must be started. It is done by the instruction “SETB TR0” for timer 0 and “SETB TR1” for timer1. This is like mode 1. After timer is started, it starts to count up by incrementing the TL register. It counts up until it reaches its limit of FFH. When it rolls over from FFH to 00. It sets high the TF (timer flag). If we are using timer 0, TF0 goes high; if using TF1 then TF1 is raised. When Tl register rolls from FFH to 00 and TF is set to 1, TL is reloaded automatically with the original value kept by the TH register. To repeat the process, we must simply clear TF and let it go without any need by the programmer to reload the original value. This makes mode 2 auto reload, in contrast in mode 1 in which programmer has to reload TH and TL.  Mode 3 Mode 3 is also known as a split timer mode. Timer 0 and 1 may be programmed to be in mode 0, 1 and 2 independently of similar mode for other timer. This is not true for mode 3; timers do not operate independently if mode 3 is chosen for timer 0. Placing timer 1 in mode 3 causes it to stop counting; the control bit TR1 and the timer 1 flag TF1 are then used by timer0.  TCON register TF1 : Timer1 over flow flag. Set when timer rolls from all 1s to 0. Cleared When the processor vectors to execute interrupt service routine Located at program address 001Bh.  TR1 :Timer 1 run control bit. Set to 1 by programmer to enable timer to count; Cleared to 0 by program to halt timer. TF0 : Timer 0 over flow flag. Same as TF1. TR0 : Timer 0 run control bit. Same as TR1. IE1 : External interrupt 1 Edge flag. Not related to timer operations. IT1 : External interrupt1 signal type control bit. Set to 1 by program to Enable external interrupt 1 to be triggered by a falling edge signal. Set to 0 by program to enable a low level signal on external interrupt1 to generate an interrupt.  IE0 : External interrupt 0 Edge flag. Not related to timer operations. IT0 : External interrupt 0 signal type control bit. Same as IT0.  Four General Purpose Parallel Input/Output Ports The 8051 microcontroller has four 8-bit input/output ports. These are: PORT P0: When there is no external memory present, this port acts as a general purpose input/output port. In the presence of external memory, it functions as a multiplexed address and data bus. It performs a dual role. PORT P1: This port is used for various interfacing activities. This 8- bit port is a normal I/O port i.e. it does not perform dual functions. PORT P2: Similar to PORT P0, this port can be used as a general purpose port when there is no external memory but when external memory is present it works in conjunction with PORT PO as an address bus. This is an 8-bit port and performs dual functions. PORT P3: PORT P3 behaves as a dedicated I/O port  Internal RAM and ROM ROM A code of 4K memory is incorporated as on-chip ROM in 8051. The 8051 ROM is a non-volatile memory meaning that its contents cannot be altered and hence has a similar range of data and program memory, i.e, they can address program memory as well as a 64K separate block of data memory.Internal ROM address range is 0000 h to 0FFF h RAM The 8051 microcontroller is composed of 128 bytes of internal RAM. This is a volatile memory since its contents will be lost if power is switched off. These 128 bytes of internal RAM are divided into 32 working registers which in turn constitute 4 register banks (Bank 0-Bank 3) with each bank consisting of 8 registers (R0 - R7). There are 128 addressable bits in the internal RAM. The internal RAM address range is 00 h to FF h Internal RAM and ROM..cntd Data Memory Organization of 8051 Program Memory Organization of 8051  Interrupt Control There are two ways of giving interrupts to a microcontroller – one is by sending software instructions and the other is by sending hardware signals. The interrupt mechanism keeps the normal program execution in a "put on hold" mode and executes a subroutine program and after the subroutine is executed, it gets back to its normal program execution. This subroutine program is also called an interrupt handler. A subroutine is executed when a certain event occurs. In 8051, 5 sources of interrupts are provided. They are: a) 2 external interrupt sources connected through INT0 and INT1 b) 3 external interrupt sources- serial port interrupt, Timer Flag 0 and Timer Flag 1. The pins connected are as follows: 1. ALE (Address Latch Enable) - Latches the address signals on Port P0 2. EA (External Address) - Holds the 4K bytes of program memory 3. PSEN (Program Store Enable) - Reads external program memory 4. RST (Reset) - Reset the ports and internal registers upon start up  Serial Data Communication A method of establishing communication among computers is by transmitting and receiving data bits is a serial connection network. In 8051, the SBUF (Serial Port Data Buffer) register holds the data; the SCON (Serial Control) register manages the data communication and the PCON (Power Control) register manages the data transfer rates. Further, two pins - RXD and TXD, establish the serial network. The SBUF register has 2 parts – one for storing the data to be transmitted and another for receiving data from outer sources. The first function is done using TXD pin and the second function is done using RXD pin. There are 4 programmable modes in serial data communication. They are: 1. Serial Data mode 0 (shift register mode) 2. Serial Data mode 1 (standard UART) 3. Serial Data mode 2 (multiprocessor mode) 4. Serial Data mode 3  PSW (Program Status Word) Program Status Word or PSW is a hardware register which is a memory location which holds a program's information and also monitors the status of the program this is currently being executed. PSW also has a pointer which points towards the address of the next instruction to be executed. PSW register has 3 fields namely are instruction address field, condition code field and error status field. We can say that PSW is an internal register that keeps track of the computer at every instant. Generally, the instruction of the result of a program is stored in a single bit register called a 'flag'. The are7 flags in the PSW of 8051. Among these 7 flags, 4 are math flags and 3 are general purpose or user flags. The 4 Math flags are: Carry (c) Auxiliary carry (AC) Overflow (OV) Parity (P) The physical address of PSW starts from D0H. The individual bits are then accessed using D1, D2 … D7. The various individual bits are explained below. Program Status Word-PSW  Program Counter (PC) A program counter is a 16-bit register and it has no internal address. The basic function of program counter is to fetch from memory the address of the next instruction to be executed. The PC holds the address of the next instruction residing in memory and when a command is encountered, it produces that instruction. This way the PC increments automatically, holding the address of the next instruction. Data Pointer (DPTR) The data pointer or DPTR is a 16-bit register. It is made up of two 8-bit registers called DPH and DPL. Separate addresses are assigned to each of DPH and DPL. These 8-bit registers are used for the storing the memory addresses that can be used to access internal and external data/code. Stack Pointer (SP) The stack pointer (SP) in 8051 is an 8-bit register. The main purpose of SP is to access the stack. As it has 8-bits it can take values in the range 00 H to FF H. Stack is a special area of data in memory. The SP acts as a pointer for an address that points to the top of the stack.  Data and Address Bus A bus is group of wires using which data transfer takes place from one location to another within a system. Buses reduce the number of paths or cables needed to set up connection between components. There are mainly two kinds of buses - Data Bus and Address Bus Data Bus: The purpose of data bus is to transfer data. It acts as an electronic channel using which data travels. Wider the width of the bus, greater will be the transmission of data. Address Bus: The purpose of address bus is to transfer information but not data. The information tells from where within the components, the data should be sent to or received from. The capacity or memory of the address bus depends on the number of wires that transmit a single address bit. Addressing Modes of 8051 Compiled by : Prof. savita C. Raut  Immediate Addressing Mode Register Addressing Mode Direct Addressing Mode Register Indirect Addressing Mode Indexed Addressing Mode Implied Addressing Mode  Immediate addressing mode In this Immediate Addressing Mode, the data is provided in the instruction itself. The data is provided immediately after the opcode. These are some examples of Immediate Addressing Mode. In this mode, the # symbol is used for immediate data. MOV A, #0AFH MOV R3, #45H MOV DPTR, #FE00H In the last instruction, there is DPTR. The DPTR stands for Data Pointer. It points the external data memory location. In the first instruction, the immediate data is AFH, but one 0 is added at the beginning. So when the data is starting with A to F, the data should be preceded by 0.  Register addressing mode In the register addressing mode the source or destination data should be present in a register (R0 to R7). These are some examples of Register Addressing Mode. MOV A, R5 MOV R0, A In 8051, there is no instruction like MOV R5, R7. But we can get the same result by using this instruction MOV R5, 07H, or by using MOV 05H, R7. But this two instruction will work when the selected register bank is RB-0. To use another register bank and to get the same effect, we have to add the starting address of that register bank with the register number. For an example, if the RB-2 is selected, and we want to access R5, then the address will be (10H + 05H = 15H), so the instruction will look like this MOV 15H, R7. Here 10H is the starting address of Register Bank 2.  Direct Addressing Mode In the Direct Addressing Mode, the source or destination address is specified by using 8-bit data in the instruction. Only the internal data memory can be used in this mode. Here some of the examples of direct Addressing Mode. MOV 80H, R6 MOV R2, 45H MOV R0, 05H The first instruction will send the content of registerR6 to port P0 (Address of Port 0 is 80H). The second one is for copying the content from m.l. 45H to R2. The third one is used to get data from Register R5 (When register bank RB0 is selected) to register R0.  Stack and Direct Addressing Mode: The direct addressing mode is allowed for pushing onto the stack. The instruction "PUSH A" is invalid. Pushing the accumulator onto the stack must be coded as "PUSH 0E0H". 0E0H is the address of the register accumulator A. Pushing R2 of 'Bank 0' is coded as "PSUH 02". Direct addressing mode must also be used for POP instruction as well. e.g; "POP 03" will pop the top of the stack into into R3 of 'Bank 0'.  Stack..cntd Example # 1: Lets show the code to PUSH R1,R2 and A onto the stack and then POP them back into R3,R4 and B, where B=register A, R3=R2, R4=R1 PUSH 01 ; PUSH R1 onto stack PUSH 02 ; PUSH R2 onto stack PUSH 0E0H; PUSH register A onto stack POP 0F0H ; POP top of stack into register B, now register B = register A POP 03 ; POP top of stack into register R3, now R3 = R2 POP 04; POP top of stack into register R4, now R4 = R1  Register indirect addressing Mode In this mode, the source or destination address is given in the register. By using register indirect addressing mode, the internal or external addresses can be accessed. The R0 and R1 are used for 8-bit addresses, and DPTR is used for 16-bit addresses, no other registers can be used for addressing purposes. some examples of this mode. MOV 0E5H, @R0; MOV @R1, 80H In the instructions, the @ symbol is used for register indirect addressing. In the first instruction, it is showing that the R0 register is used. If the content of R0 is 40H, then that instruction will take the data which is located at location 40H of the internal RAM. In the second one, if the content of R1 is 30H, then it indicates that the content of port P0 will be stored at location 30H in the internal RAM.  indirect..cntd.. MOVX A, @R1; MOV @DPTR, A; In these two instructions, the X in MOVX indicates the external data memory. The external data memory can only be accessed in register indirect mode. In the first instruction if the R0 is holding 40H, then A will get the content of external RAM location40H. And in the second one, the content of A is overwritten in the location pointed by DPTR.  Indexed addressing mode In the indexed addressing mode, the source memory can only be accessed from program memory only. The destination operand is always the register A. These are some examples of Indexed addressing mode. MOVC A, @A+PC; MOVC A, @A+DPTR; The C in MOVC instruction refers to code byte. For the first instruction, let us consider A holds 30H. And the PC value is1125H. The contents of program memory location 1155H (30H + 1125H) are moved to register A.  Implied Addressing Mode In the implied addressing mode, there will be a single operand. These types of instruction can work on specific registers only. These types of instructions are also known as register specific instruction. Here are some examples of Implied Addressing Mode. RL A SWAP A These are 1- byte instruction. The first one is used to rotate the A register content to the Left. The second one is used to swap the nibbles in A. Bit-Addressable RAM  Assembler Directives Assembler directives are instructions/statements to the assembler to perform various tasks, storage reservation, and other control functions. The speciality of a similar directives is that they are effective only during the assembly of the program and they do not generate any machine executable code. Frequently Used assembler directive of 8051 are: DB (Define Byte) , ORG (Origin) , EQU (Equate) , END  Assembler directives ORG (origin):- The origin (ORG) directive is used to indicate the beginning of the addresses the number that comes after ORG can be either in hex or in decimal if the number is not followed by H it is decimal and the assembler will convert it to hex some assembler use “.ORG” instead of “ORG” for the origin directive. Ex: ORG 00H EQU (equate):- This is used to define a constant without occupying a memory location. The EQU directive does not set aside storage for a data item but associates a constant value with a data label so that when the label appears in the program it constant value will be substituted for the label use EQU for the counter constant and then the constant is used to load the R3 register. Ex:- COUNT EQU 25 MOV R3, # COUNT  Assembler directives END:- Important pseudo code is the END directive this indicates to the assembler at the end of the source (asm) file the END directive is the last line of an 8051 program meaning that in the source code anything after the END directive is ignored by the assembler. DB (Define byte):- The DB directive is the most widely used data directive in the assembler it is used to define the 8-bit data when DB is used to define data, the numbers can be in decimal binary, hex or ASCII format for decimal “D” after the decimal number, for binary ‘B’ and hexadecimal ‘H’ required. DB directive is the only directive that can be used to define ASCII strings larger than the character therefore it should be used for all ASCII data definitions. Ex: - ORG 5000 H DATA 1: DB 28 -(Decimal) DATA 2: DB 39H - (HEX) DATA 3: 0101001 B -(Binary) Program to add 2 8 bit no.s Add 2- 8 bit nos Sub Mul Div Block addition  Block addition WAP to add 5 bytes stored at m.l. 30 h to 34 h and store the result at m.l. 35h(lower byte) 36h(higher byte)  Block addition MOV R0,# 30h MOV R1,# 04h MOV R2,#00h MOV A,@R0 Go: Inc R0 ADD A,@R0 JNC next INC R2 Next: DJNZ R1, Go MOV 35h,A MOV 36h, R2 Here : Sjmp here  Program to Add 2-16 bit numbers :25F2H and 3189H Instruction : ADDC – Add with Carry 8086 Interrupt Structure Compiled by Mrs.Savita Raut  What is an Interrupt? An interrupt is the method of processing the microprocessor by peripheral device(hardware interrupt). The meaning of ‘interrupts’ is to break the sequence of operation. An interrupt is used to cause a temporary halt in the execution of program. Microprocessor responds to the interrupt with an interrupt service routine, which is short program or subroutine that instructs the microprocessor on how to handle the interrupt. After executing ISR , the control is transferred back again to the main program  Types of Interrupts in 8086 An 8086 interrupt can come from any one of the three sources: Hardware Interrupt: One source is an external signal applied to the Non Maskable Interrupt (NMI) input pin or to the Interrupt (INTR) input pin. Software Interrupt : A second source of an interrupt is execution of the Interrupt instruction- INT Interrupt due to internally generated error conditions (Reffered to as Type or Exception): The third source of an interrupt is some error condition produced in the 8086 by the execution of an instruction. An example of this is the divide by zero error (**Type - Intel or Exception - Motorolla)  Hardware and Software Interrupt The two basic type of hardware interrupts are: maskable and non-maskable. Nonmaskable interrupt requires an immediate response by microprocessor, it usually used for serious circumstances like power failure. A maskable interrupt is an interrupt that the microprocessor can ignore depending upon some predetermined condition defined by status register. Hardware and Software Interrupts:  The non-maskable interrupt is generated by en external device, through a rising edge on the NMI pin A maskable interrupt is generated by external device, through a high logic level on the INTR pin (the external device has to specify the interrupt number). Software interrupts: Software interrupts (exceptions) using the INT instruction (followed by the interrupt number (type)).  Interrupt Vector table The 8086 provides a 256 entry interrupt vector table beginning at address 0:0 in memory. This is a 1KB table containing 256 entries 4-bytes each. Each entry in this table contains a segmented address that points at the interrupt service routine in memory. The lowest five types are dedicated to specific interrupts such as the divide by zero interrupt and the non maskable interrupt. The next 27 interrupt types, from 5 to 31 are High priority 3 reserved by Intel for use in future microprocessors. The upper 224 interrupt types, from32 to 255, are available to use for hardware and software interrupts  The first 1Kbyte of memory of 8086 (00000 to003FF) is set aside as a table for storing the starting addresses of Interrupt Service Procedures (ISP). Since 4-bytes are required for storing starting addresses of ISPs, the table can hold 256 Interrupt procedures. The starting address of an ISP is often called the Interrupt Vector or Interrupt Pointer. Therefore the table is referred as Interrupt Vector Table. In this table, IP value is put in as low word of the vector & CS is put in high vector. Interrupt Vector table Interrupt priority  Contd.. ISR procedure Mainline Program PUSH Flags PUSH registers CLEAR IF , TF PUSH CS - PUSH IP - FETCH ISR ADDRESS - POP registers POP IP IRET POP CS POP FLAGS 10  How does 8086 responds to the Interrupt 1. It decrements SP by 2 and pushes the flag register on the stack 2. Disables INTR by clearing the IF 3. It resets the TF in the flag Register 4. It decrements SP by 2 and pushes CS on the stack. 5. It decrements SP by 2 and pushes IP on the stack 6. Fetch the ISR address from the interrupt vector table  Interrupt Vector Table INT Number Physical Address INT 00 00000 INT 01 00004 INT 02 00008 : : : : INT FF 003FC 13  Physical Address of ISR for the particular Interrupt is obtained by multiplying the the type number by 4 Find the physical address in the interrupt vector table associated with a) INT 12H b) INT 8H Solution: a) 12H * 4 = 48H Physical Address: 00048H ( 48 through 4BH are set aside for CS & IP) b) 8 * 4 = 20H Memory Address : 00020H Minimum and Maximum Mode of 8086 Compiled by- Mrs Savita C. Raut  Minimum and maximum Moode Minimum Mode : Uniprocessor Mode Maximum Mode : Multiple processor mode Some Common Components of 8086 system are:  8284- Clock Generator and driver  8282/8283 – Octal Latch  8286 – Octal bus Transceiver  74138- Decoder  8288- Bus Controller Minimum Mode -8086 Maximum Mode- 8086  8284-Clock Generator & driver Clock requirement of 8086: 8284- Pin diagram Interfacing 8284 with 8086 Cntd.. Interfacing 8284 with 8086 Octal Latch – 8282/8283 Cntd..Octal Latch Internal Diagram of 8282/8283 Bus Transceiver 8286 8286: Pin description Interfacing 8286 with 8086 Decoder-74138  8288- Bus Controller Used in maximum mode configuration of 8086. 8288 accepts the CLK signal along with So ,S1, S2 outputs of 8086 and generates the command , control and timing signals at its output. It also provides the bipolar bus drive capability and optimizes the system performance. 8288 8288 8288 Interfacing 8288 with 8086  Timing Diagrams for 8086 All the operations in 8086 are carried out with a particular sequence in a synchronized manner, so it is necessary to understand the Timing Diagrams. Clock Waveform: It represents the crystal controlled signal sent to 8086 from an external clock generator 8284. Clock, T- State and Machine cycle Timing diagram for Read machine cycle Timing diagram for Write machine cycle Maximum Mode-Read machine cycle Maximum Mode-Write machine cycle Addressing modes of 8086 Compiled by Mrs. Savita C. Raut EXTC Dept ,KJSCE  Address registers The segment address is stored in the segment registers; CS,DS, ES ,SS registers. The Offset address is stored in IP,SP , BP, SI, DI ,BX register. The CS: IP pair gives the address of the next instruction to be executed in the program sequence The SS:SP pair gives the address of the top of the stack (a temporary storage memory locations used by processor) The SS:BP pair is used as a pointer into the stack,for random access of the stack.  Address registers The DS:SI pair is used to access the memory locations in the data segment. Also register BX is used as memory pointer in the data segment with DS register(i,e.DS:BX) DS: SI is used as a source pointer and ES: DI is used as destination pointer for string instructions. For all other instructions DI register is used with DS register. Default Segment Register and Offset pointer pairs  Addressing modes of 8086 When 8086 executes an instruction , it performs specific operation/function on data.The data is referred to as Operands. Operands may be present in the registers or within the instruction itself or in memory or I/O ports. The different methods of accessing (selecting) the Operands is referred to as Addressing modes.  Addressing modes of 8086….cntd The Addressing Modes can be categorized as: 1. Register Addressing Mode 2. Immediate Addressing Mode 3. Memory Addressing Mode: I. Direct II. Indirect: a. Register indirect b. Based Indexed c. Register Relative d. Relative Based Indexed 4. String Addressing Mode 5. I/O Addressing Mode a. Direct Port Addressing b. Indirect Port Addressing 6. Implied Addressing Mode  Addressing modes of 8086….cntd 1.Register Addressing Mode In register addressing mode, the data is stored in a register. All the registers, except IP, may be used in this mode. The registers may be 8 /16 bits Ex: MOV BX, AX ADD BX,CX  Addressing modes of 8086….cntd 2. Immediate Addressing Mode In this type of addressing, source operand is a part of instruction and is known as immediate data and appears in the form of successive byte or bytes. Immediate data can only be used as source operand. Ex: MOV AX, 2345H MOV CH,4A H In the above example, 2345H is the immediate data. The immediate data may be 8-bit or 16-bit in size.  Addressing modes of 8086….cntd 1. Memory Addressing Mode: I. Direct II. Indirect: a. Register indirect b. Based Indexed c. Register Relative d. Relative Based Indexed I.Direct Memory Addressing Mode: In this mode ,the 16 bit Effective (Offset )address is directly specified in the instruction as a part of it. DS register is default segment register for Direct addressing mode. Ex: MOV AX, [2100H] (The contents of memory location with physical address = DS*10 H + 2100 are copied to register AX) Direct Memory addressing mode- Ex: MOV AX, CS : (The contents of memory location with physical address = CS*10 H + 2100 are copied to register AX)  Addressing modes of 8086….cntd Indirect Memory Addressing Mode a. Register Indirect: The address of the memory location, which contains data or operand, is determined in an indirect way, using the offset register. This mode of addressing is known as register indirect mode. If registers BX or SI or DI are used as Effective Address register then the default segment register is DS. If BP is used ,then SS is default segment register. Programmer can use Segment override prefix to change the default segment register. Ex: MOV AX, [BX] MOV CX, [SI] MOV BL,[DI] MOV CL, ES: [SI] (here ES is Segment override prefix)  Addressing modes of 8086….cntd Indirect Memory Addressing Mode b.Based Indexed: The effective address of data is formed, in this addressing mode, by adding content of a base register (any one of BX or BP) to the content of an index register (any one of SI or DI). The default segment register may be DS or ES. Ex1: MOV AX, [BX][SI] (Here, BX is the base register and SI is the index register the effective address is computed as 10H * DS + [BX] + [SI]) EX2: Mov [BP] [SI],AL EX3: MOV CL, CS:[BX][DI]  Addressing modes of 8086….cntd Indirect Memory Addressing Mode c. Register Relative: In this addressing mode, the data is available at an effective address formed by adding an 8-bit or 16-bit displacement with the content of any one of the registers BX, BP, SI and DI in the default segment DS (or ES) segment. Ex: MOV AX, [BX+12H] (Here, the physical address is given as 10H *DS+BX+12H) EX2: MOV AL, CS:[BP+23H]  Addressing modes of 8086….cntd Indirect Memory Addressing Mode d. Relative Based Indexed: The effective address is formed by adding an 8 or 16- bit displacement with the sum of the contents of any one of the base register (BX or BP) and any one of the index register, in a default segment. Ex: MOV AX, [BX+SI + 50H] (Here, 50H is an immediate displacement, BX is base register and SI is an index register the physical address of data is computed as: 10H * DS + [BX + SI+ 50H] EX2:MOV AX, CS:[BX+SI + 50H] (Segment override prefix)  Addressing modes of 8086….cntd 4.String Addressing Mode When a string instruction is executed:  SI is assumed to point to the 1st byte or word of source string and DS is default segment register.  DI is assumed to point to the 1st byte or word of destination string and ES is default segment register. In a repeated string operation , the processor automatically increments or decrements SI and DI to obtain subsequent byte or word (with the help of Direction Flag) Ex : MOVSB MOVSW  Addressing modes of 8086….cntd 5. I/O Addressing Mode: i.Direct port addressing (Fixed port): 8-bit port address is specified in the instruction. Allows access to port no. 0 to FF (256 ports only) Ex1 : OUT 4B H ,AL or OUT 4B H , AX EX2: IN AL , 4B H or IN AX , 4B H ii. Indirect Port Addressing (variable ): It is similar to register indirect addressing. The port number (address)is specified in register Dx. The addresses may range from 0000 to FFFF H. EX 1 : OUT DX, AL or OUT DX, AX EX2: IN AL, DX IN AX, DX  Addressing modes of 8086….cntd 6. Implied Addressing Mode In this addressing mode ,the instructions do not have operands EX : CMC (compliment carry flag) STC (Set carry Flag) CLD (Clear direction flag) CBW (Convert Byte to word) Addressing Mnemonic Segment for Symbolic representation mode memory access IMMEDIATE MOV AX,1000 CODE AH