Microprocessors and Microcontrollers.pdf

MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY (Autonomous Institution – UGC, Govt. of India) Recognized under 2(f) and 12 (B) of UGC ACT 1956 (Affiliated to JNTUH, Hyderabad, Approved by AICTE - Accredited by NBA & NAAC – ‘A’ Grade - ISO...

MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY (Autonomous Institution – UGC, Govt. of India) Recognized under 2(f) and 12 (B) of UGC ACT 1956 (Affiliated to JNTUH, Hyderabad, Approved by AICTE - Accredited by NBA & NAAC – ‘A’ Grade - ISO 9001:2015 Certified) Maisammaguda, Dhulapally (Post Via. Kompally), Secunderabad – 500100, Telangana State, India DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING (R18A0415) MICROPROCESSORS AND MICROCONTROLLERS For III Year B.Tech EEE-II SEM Prepared by M.RAMANJANEYULU, Associate Professor Mr. KDK AJAY, Assistant Professor Dr.S.SASIKANTH, Professor  MALLA REDDY COLLEGE OF ENGINEERING AND TECHNOLOGY III Year B.Tech EEE-II SEM L T/P/D C 3 -/ -/- 3 (R18A0415) MICROPROCESSORS AND MICROCONTROLLERS COURSE OBJECTIVES: To understand the basics of microprocessors and microcontrollers architectures and its functionalities. To develop an in-depth understanding of the operation of microprocessors and microcontrollers, machine language programming & interfacing techniques. To design and develop Microprocessor/ microcontroller based systems for real time applications using low level language like ALP. To understand the concepts of ARM processor. UNIT - I 8086 ARCHITECTURE: Architecture of 8086, Register Organization, Programming Model, Memory addresses, Memory Segmentation, Physical Memory Organization, Signal descriptions of 8086- Common Function Signals, Minimum and Maximum mode signals, Timing diagrams. UNIT - II INSTRUCTION SET AND ASSEMBLY LANGUAGE PROGRAMMING OF 8086: Instruction formats, Addressing modes, Instruction Set, Assembler Directives, Procedures, Macros, Simple Programs involving Logical, Branch and Call Instructions, Sorting, Evaluating Arithmetic Expressions, String Manipulations. UNIT - III I/O INTERFACE: 8255 PPI, Various Modes of Operation and Interfacing to 8086, D/A and A/D Converter, Stepper motor, Interfacing of DMA controller 8257 INTERFACING WITH ADVANCED DEVICES: Memory Interfacing to 8086, Interrupt Structure of 8086, Vector Interrupt Table, Interrupt Service Routine, architecture of 8259. COMMUNICATION INTERFACE: Serial Communication Standards, Serial Data Transfer Schemes, 8251 USART Architecture and Interfacing. UNIT - IV INTRODUCTION TO MICROCONTROLLERS: Overview of 8051 Microcontroller, Architecture, I/O Ports, Memory Organization, Addressing Modes and Instruction set of 8051, Simple Programs, memory interfacing to 8051 UNIT - V 8051 REAL TIME CONTROL: Programming Timer Interrupts, Programming External Hardware Interrupts, Programming the Serial Communication Interrupts, Programming 8051 Timers and Counters. ARM PROCESSOR: Fundamentals, Registers, Current program status register, Pipeline, Interrupt and the vector table. TEXT BOOKS: 1. D. V. Hall, Microprocessors and Interfacing, TMGH, 2nd Edition 2006. 2. Kenneth. J. Ayala, The 8051 Microcontroller, 3rd Ed., Cengage Learning. 3. ARM System Developer’s Guide: Designing and Optimizing System Software- Andrew N. Sloss, Dominic Symes, Chris Wright, Elsevier Inc., 2007 REFERENCE BOOKS: 1. Advanced Microprocessors and Peripherals – A. K. Ray and K.M. Bhurchandani, TMH, 2nd Edition 2006. 2. The 8051Microcontrollers, Architecture and Programming and Applications -K.Uma Rao, Andhe Pallavi, Pearson, 2009. 3. Micro Computer System 8086/8088 Family Architecture, Programming and Design - Liu and GA Gibson, PHI, 2nd Ed. 4. Microcontrollers and Application - Ajay. V. Deshmukh, TMGH, 2005. COURSE OUTCOMES: After going through this course the student will 1. Learn the internal organization of popular 8086/8051microprocessors/microcontrollers. 2. Learn hardware and software interaction and integration. 3. Learn the design of microprocessors/microcontrollers-based systems  UNIT -I 8086 Architecture  Architecture of 8086  Register Organization  Programming Model  Memory addresses  Memory Segmentation  Physical Memory Organization  Signal descriptions of 8086- Common Function Signals  Minimum and Maximum mode signals  Timing diagrams  UNIT-I 8086 Architecture Introduction to Microprocessors A microprocessor is a computer processor which incorporates the functions of a computer's central processing unit (CPU) on a single integrated circuit (IC), or at most a few integrated circuits The microprocessor is a multipurpose, clock driven, register based, digital-integrated circuit which accepts binary data as input, processes it according to instructions stored in its memory, and provides results as output. Microprocessors contain both combinational logic and sequential digital logic. Microprocessors operate on numbers and symbols represented in the binary numeral system. Generation of Microprocessors:  INTEL 4004 ( 1971)  4-bit microprocessor  4 KB main memory  45 instructions  PMOS technology  was first programmable device which was used in calculators  INTEL 8008 (1972)  8-bit version of 4004  16 KB main memory  48 instructions  PMOS technology  Slow  Intel 8080 (1973)  8-bit microprocessor  64 KB main memory  2 microseconds clock cycle time  500,000 instructions/sec  10X faster than 8008  NMOS technology  Drawback was that it needed three power supplies.   Small computers (Microcomputers) were designed in mid 1970’s Using 8080 as CPU.  INTEL 8086/8088 Year of introduction 1978 for 8086 and 1979 for 8088  16-bit microprocessors  Data bus width of 8086 is 16 bit and 8 bit for 8088  1 MB main memory  400 nanoseconds clock cycle time  6 byte instruction cache for 8086 and 4 byte for 8088  Other improvements included more registers and additional instructions  In 1981 IBM decided to use 8088 in its personal computer  INTEL 80186 (1982)  16-bit microprocessor-upgraded version of 8086  1 MB main memory  Contained special hardware like programmable counters, interrupt controller etc.  Never used in the PC  But was ideal for systems that required a minimum of hardware.  INTEL 80286 (1983)  16-bit high performance microprocessor with memory management & protection  16 MB main memory  Few additional instructions to handle extra 15 MB  Instruction execution time is as little as 250 ns  Concentrates on the features needed to implement MULTITASKING  Intel 80386 (1986)  Intel 80486 (1989)  Pentium (1993)  Pentium pro(1995)  Pentium ii (1997)  Pentium iii (1999)  Pentium iv (2002)  Latest is Intel i9 processor General Architecture of Microprocessors Buses Register Organization of 8086 8086 has a powerful set of registers containing general purpose and special purpose registers. All the registers of 8086 are 16-bit registers. The general purpose registers, can be used either 8-bit registers or 16-bit registers. The general purpose registers are either used for holding the data, variables and intermediate results temporarily or for other purpose like counter or for storing offset address for some particular addressing modes etc. The special purpose registers are used as segment registers, pointers, index registers or as offset storage registers for particular addressing modes. Fig 1.4 shows register organization of 8086. We will categorize the register set into four groups as follows: General data Registers: The registers AX, BX, CX, and DX are the general 16-bit registers. AX Register: Accumulator register consists of two 8-bit registers AL and AH, which can be combined together and used as a 16- bit register AX. AL in this case contains the low-order byte of the word, and AH contains the high- order byte. Accumulator can be used for I/O operations, rotate and string manipulation. BX Register: This register is mainly used as a base register. It holds the starting base location of a memory region within a data segment. It is used as offset storage for forming physical address in case of certain addressing mode. CX Register: It is used as default counter or count register in case of string and loop instructions. DX Register: Data register can be used as a port number in I/O operations and implicit operand or destination in case of few instructions. In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number. Segment registers: To complete 1Mbyte memory is divided into 16 logical segments. The complete 1Mbyte memory segmentation is as shown in fig 1.5. Each segment contains 64Kbyte of memory. There are four segment registers. Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions. It is used for addressing a memory location in the code segment of the memory, where the executable program is stored. Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register can be changed directly using POP instruction. It is used for addressing stack segment of memory. The stack segment is that segment of memory, which is used to store stack data. Data segment (DS) is a 16-bit register containing address of 64KB segment with program data. By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. DS register can be changed directly using POP and LDS instructions. It points to the data segment memory where the data is resided. Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with program data. By default, the processor assumes that the DI register references the ES segment in string manipulation instructions. ES register can be changed directly using POP and LES instructions. It also refers to segment which essentially is another data segment of the memory. It also contains data. Pointers and index registers. The pointers contain within the particular segments. The pointers IP, BP, SP usually contain offsets within the code, data and stack segments respectively Stack Pointer (SP) is a 16-bit register pointing to program stack in stack segment. Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for based, based indexed or register indirect addressing. Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data addresses in string manipulation instructions. Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions. Flag Register: Flags Register determines the current state of the processor. They are modified automatically by CPU after mathematical operations, this allows to determine the type of the result, and to determine conditions to transfer control to other parts of the program. The 8086 flag register as shown in the fig 1.6. 8086 has 9 active flags and they are divided into two categories: 1. Conditional Flags 2. Control Flags Conditional flags are as follows: Carry Flag (CY): This flag indicates an overflow condition for unsigned integer arithmetic. It is also used in multiple-precision arithmetic. Auxiliary Flag (AC): If an operation performed in ALU generates a carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AC flag is set i.e. carry given by D3 bit to D4 is AC flag. This is not a general-purpose flag, it is used internally by the Processor to perform Binary to BCD conversion. Parity Flag (PF):This flag is used to indicate the parity of result. If lower order 8-bits of the result contains even number of 1’s, the Parity Flag is set and for odd number of 1’s, the Parity flag is reset. Zero Flag (ZF):It is set; if the result of arithmetic or logical operation is zero else it is reset. Sign Flag (SF):In sign magnitude format the sign of number is indicated by MSB bit. If the result of operation is negative, sign flag is set. Control Flags Control flags are set or reset deliberately to control the operations of the execution unit. Control flags are as follows: Trap Flag (TF): It is used for single step control. It allows user to execute one instruction of a program at a time for debugging. When trap flag is set, program can be run in single step mode. Interrupt Flag (IF):It is an interrupt enable/disable flag. If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the interrupt is disabled. It can be set by executing instruction sit and can be cleared by executing CLI instruction. Direction Flag (DF):It is used in string operation. If it is set, string bytes are accessed from higher memory address to lower memory address. When it is reset, the string bytes are accessed from lower memory address to higher memory address.  8086 Architecture The 8086 is mainly divided into mainly two blocks 1. Execution Unit (EU) 2.Bus interface Unit (BIU) Dividing the work between these two will speedup the processing 1) EXECUTION UNIT( EU) The Execution unit tells the BIU where to fetch instructions or data from  decodes instructions and  Executes instructions The Execution unit contains: 1) Control circuitry 2) ALU 3) FLAGS 4) General purpose Registers 5) Pointer and Index Registers Control Circuitry:  It directs internal operations.   A decoder in the EU translates instructions fetched from memory Into series of actions which the EU carries out Arithmetic Logic Unit: 16 bit ALU Used to carry the operations  ADD  SUBTRACT  XOR  INCREMENT  DECREMENT  COMPLEMENT  SHIFT BINARY NUMBERS FLAG REGISTERS:  A flag is a flip flop that indicates some condition produced by execution of an instruction or controls certain operation of the EU.  It is 16 bit  It has nine active flags Divided into two types 1. Conditional flags 2. Control flags Conditional Flags Carry Flag (CY): This flag indicates an overflow condition for unsigned integer arithmetic. It is also used in multiple-precision arithmetic. Auxiliary Flag (AC): If an operation performed in ALU generates a carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AC flag is set i.e. carry given by D3 bit to D4 is AC flag. This is not a general-purpose flag, it is used internally by the Processor to perform Binary to BCD conversion. Parity Flag (PF):This flag is used to indicate the parity of result. If lower order 8-bits of the result contains even number of 1’s, the Parity Flag is set and for odd number of 1’s, the Parity flag is reset. Zero Flag (ZF):It is set; if the result of arithmetic or logical operation is zero else it is reset. Sign Flag (SF):In sign magnitude format the sign of number is indicated by MSB bit. If the result of operation is negative, sign flag is set. Control Flags Control flags are set or reset deliberately to control the operations of the execution unit. Control flags are as follows: Trap Flag (TF): It is used for single step control. It allows user to execute one instruction of a program at a time for debugging. When trap flag is set, program can be run in single step mode. Interrupt Flag (IF):It is an interrupt enable/disable flag. If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the interrupt is disabled. It can be set by executing instruction sit and can be cleared by executing CLI instruction. Direction Flag (DF):It is used in string operation. If it is set, string bytes are accessed from higher memory address to lower memory address. When it is reset, the string bytes are accessed from lower memory address to higher memory address. General Purpose Registers: The 8086 general purpose registers are similar to those of earlier generations 8080 and 8085.It was designed in such a way that many programs written for 8080 and 8085 could easily be translated to run on 8086.The advantage of using internal registers for the temporary storage of data is that since data already in the EU., it can be accessed much more quickly than it could be accessed from external memory. General Purpose Registers The registers AX, BX, CX, and DX are the general 16-bit registers. AX Register: Accumulator register consists of two 8-bit registers AL and AH, which can be combined together and used as a 16- bit register AX. AL in this case contains the low-order byte of the word, and AH contains the high- order byte. Accumulator can be used for I/O operations, rotate and string manipulation. BX Register: This register is mainly used as a base register. It holds the starting base location of a memory region within a data segment. It is used as offset storage for forming physical address in case of certain addressing mode. CX Register: It is used as default counter or count register in case of string and loop instructions. DX Register: Data register can be used as a port number in I/O operations and implicit operand or destination in case of few instructions. In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number. 2) BUS INTERFACE UNIT (BIU) The BIU sends out  Addresses  Fetches instructions from memory  Read data from ports and memory Or The BIU handles all transfer of data and addresses on the buses for the Execution Unit The Bus interface unit contains 1) Instruction Queue 2) Instruction pointer 3) Segment registers 4) Address Generator Instruction Queue: BIU gets upto 6 bytes of next instructions and stores them in the instruction queue. When EU executes instructions and is ready for its next instruction, then it simply reads the instruction from this instruction queue resulting in increased execution speed. Fetching the next instruction while the current instruction executes is called pipelining.( based on FIFO).This is much faster than sending out an addresses to the system memory and waiting for memory to send back the next instruction byte or bytes.Here the Queue will be dumped and then reloaded from the new Address. Segment Register: The 8086 20 bit addresses So it can address upto 220 in memory ( 1 Mbyte) but at any instant it can address upto 4 64 KB segments. This four segments holds the upper 16 bits of the starting address of four memory segments that the 8086 is working with it at particular time.The BIU always inserts zeros for the lowest 4 bits of the 20 bit starting address Example : If the code segment register contains 348AH then the code segment starts at 348A0H.In other words a 64Kbyte segment can be located anywhere within 1MByte address Space but the segment will always starts at an address with zeros in the lowest 4 bits Stack: is a section of memory set aside to store addresses and data while subprogram executes is often called segment base. The stack segment register always holds the upper 16 bit starting address of program stack. The extra segment register and data segment register is used to hold the upper 16 bit starting addresses of two memory segments that are used for data. Instruction Pointer holds the 16 bit address or offset of the next code byte within the code segment. The value contained in the Instruction Pointer called as Offset because the value must be added to the segment base address in CS to produce the required 20 bit address. CS register contains the Upper 16 bit of the starting address of the code segment in the 1 Mbyte address range the instruction pointer contains a 16 bit offset which tells wherein that 64 Kbyte code segment the next instruction byte has to be fetched from. Stack Register and Stack Pointer: Stack: is a section of memory set aside to store addresses and data while subprogram executes is often called segment base. The stack segment register always holds the upper 16 bit starting address of program stack. The Stack pointer (SP) holds the 16 bit offset from the starting of the segment to the memory location where a word was most recently stored.The memory location where the word is stored is called as top of the stack Pointer and Index registers: In addition to stack pointer register EU has Base pointer Register (BP) Source Pointer Register(SP) Destination Pointer Register(DP) These three registers are used to store temporary storage of data like general purpose registers.They hold the 16 bit offset data of the data word in one of the segment Programming model How can a 20-bit address be obtained, if there are only 16-bit registers? However, the largest register is only 16 bits (64k); so physical addresses have to be calculated. These calculations are done in hardware within the microprocessor. The 16-bit contents of segment register gives the starting/ base address of particular segment. To address a specific memory location within a segment we need an offset address. The offset address is also 16-bit wide and it is provided by one of the associated pointer or index register. To be able to program a microprocessor, one does not need to know all of its hardware architectural features. What is important to the programmer is being aware of the various registers within the device and to understand their purpose, functions, operating capabilities, and limitations. The above figure illustrates the software architecture of the 8086 microprocessor. From this diagram, we see that it includes fourteenl6-bit internal registers: the instruction pointer (IP), four data registers (AX, BX, CX, and DX), two pointer registers (BP and SP), two index registers (SI and DI), four segment registers (CS, DS, SS, and ES) and status register (SR), with nine of its bits implemented as status and control flags.  The point to note is that the beginning segment address must begin at an address divisible by 16.Also note that the four segments need not be defined separately. It is allowable for all four segments to completely overlap (CS = DS = ES = SS). Logical and Physical Address Addresses within a segment can range from address 00000h to address 0FFFFh. This corresponds to the 64K-bytelength of the segment. An address within a segment is called an offset or logical address. A logical address gives the displacement from the base address of the segment to the desired location within it, as opposed to its "real" address, which maps directly anywhere into the 1 MByte memory space. This "real" address is called the physical address. What is the difference between the physical and the logical address? The physical address is 20 bits long and corresponds to the actual binary code output by the BIU on the address bus lines. The logical address is an offset from location 0 of a given segment.  You should also be careful when writing addresses on paper to do so clearly. To specify the logical address XXXX in the stack segment, use the convention SS:XXXX, which is equal to [SS] * 16 + XXXX. Logical address is in the form of: Base Address: Offset Offset is the displacement of the memory location from the starting location of the segment. To calculate the physical address of the memory, BIU uses the following formula: Physical Address = Base Address of Segment * 16 + Offset Example: The value of Data Segment Register (DS) is 2222H. To convert this 16-bit address into 20-bit, the BIU appends 0H to the LSB (by multiplying with 16) of the address. After appending, the starting address of the Data Segment becomes 22220H. Data at any location has a logical address specified as:2222H: 0016H Where 0016H is the offset, 2222 H is the value of DS Therefore the physical address:22220H + 0016H : 22236 H The following table describes the default offset values to the corresponding memory segments. Some of the advantages of memory segmentation in the 8086 are as follows:  With the help of memory segmentation a user is able to work with registers having only 16-bits.  The data and the user’s code can be stored separately allowing for more flexibility.  Also due to segmentation the logical address range is from 0000H to FFFFH the code can be loaded at any location in the memory. Physical memory organization: The 8086’s 1Mbyte memory address space is divided in to two independent 512Kbyte banks: the low (even) bank and the high (odd) bank. Data bytes associated with an even address (0000016, 0000216, etc.) reside in the low bank, and those with odd addresses (0000116, 0000316, etc.) reside in the high bank. Address bits A1 through A19 select the storage location that is to be accessed. They are applied to both banks in parallel. A0and bank high enable (BHE) are used as bank-select signals. The four different cases that happen during accessing data: Case 1: When a byte of data at an even address (such as X) is to be accessed:  A0 is set to logic 0 to enable the low bank of memory.  BHE is set to logic 1 to disable the high bank. Case 2: When a byte of data at an odd addresses (such as X+1) is to be accessed:  A0is set to logic 1 to disable the low bank of memory.  BHE is set to logic 0 to enable the high bank. Case 3: When a word of data at an even address (aligned word) is to be accessed:  A0 is set to logic 0 to enable the low bank of memory.  BHE is set to logic 0 to enable the high bank. Case 4: When a word of data at an odd address (misaligned word) is to be accessed, then the 8086 need two bus cycles to access it: a) During the first bus cycle, the odd byte of the word (in the high bank) is addressed  A0 is set to logic 1 to disable the low bank of memory  BHE is set to logic 0 to enable the high bank. b) During the second bus cycle, the odd byte of the word (in the low bank) is addressed  A0is set to logic 0 to enable the low bank of memory.  BHE is set to logic 1 to disable the high bank. Signal Description of 8086 Microprocessor The 8086 Microprocessor is a 16-bit CPU available in 3 clock rates, i.e. 5, 8 and 10MHz, packaged in a 40 pin CERDIP or plastic package. The 8086 Microprocessor operates in single processor or multiprocessor configurations to achieve high performance. The pin configuration is as shown in fig1. Some of the pins serve a particular function in minimum mode (single processor mode) and others function in maximum mode (multiprocessor mode) configuration.  The 8086 signals can be categorized in three groups. The first are the signals having common functions in minimum as well as maximum mode, the second are the signals which have special functions in minimum mode and third are the signals having special functions for maximum mode. The following signal description is common for both the minimum and maximum modes. AD15-AD0: These are the time multiplexed memory I/O address and data lines. Address remains on the lines during T1 state, while the data is available on the data bus during T2, T3, TW and T4. Here T1, T2, T3, T4 and TW are the clock states of a machine cycle. TW is await state. These lines are active high and float to a tristate during interrupt acknowledge and local bus hold acknowledge cycles. A19/S6, A18/S5, A17/S4, A16/S3: These are the time multiplexed address and status lines. During T1, these are the most significant address lines or memory operations. During I/O operations, these lines are low. During memory or I/O operations, status information is available on those lines for T2, T3, TW and T4.The status of the interrupt enable flag bit(displayed on S5) is updated at the beginning of each clock cycle. The S4 and S3 combinedly indicate which segment register is presently being used for memory accesses as shown in Table 1.1. These lines float to tri-state off (tristated) during the local bus hold acknowledge. The status line S6 is always low(logical). The address bits are separated from the status bits using latches controlled by the ALE signal. BHE/S7 (Active Low): The bus high enable signal is used to indicate the transfer of data over the higher order (D15-D8) data bus as shown in Table 1.2. It goes low for the data transfers over D15-D8 and is used to derive chip selects of odd address memory bank or peripherals. is low during T1 for read, write and interrupt acknowledge cycles, when- ever a byte is to be transferred on the higher byte of the data bus. The status information is available during T2, T3 and T4. The signal is active low and is tristated during 'hold'. It is low during T1 for the first pulse of the interrupt acknowledge cycle. Read signal, when low, indicates the peripherals that the processor is performing a memory or I/O read operation. is active low and shows the state for T2, T3, TW of any read cycle. The signal remains tristated during the 'hold acknowledge'. READY: This is the acknowledgement from the slow devices or memory that they have completed the data transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the 8086. The signal is active high. INTR-Interrupt Request: This is a level triggered input. This is sampled during the last clock cycle of each instruction to determine the availability of the request. If any interrupt request is pending, the processor enters the interrupt acknowledge cycle. This can be internally masked by resetting the interrupt enable flag. This signal is active high and internally synchronized. TEST: This input is examined by a 'WAIT' instruction. If the TEST input goes low, execution will continue, else, the processor remains in an idle state. The input is synchronized internally during each clock cycle on leading edge of clock. NMI-Non-maskable Interrupt: This is an edge-triggered input which causes a Type2 interrrupt. The NMI is not maskable internally by software. A transition from low to high initiates the interrupt response at the end of the current instruction. This input is internally synchronized. RESET: This input causes the processor to terminate the current activity and start execution from FFFF0H. The signal is active high and must be active for at least four clock cycles. It restarts execution when the RESET returns low. RESET is also internally synchronized. CLK-Clock Input: The clock input provides the basic timing for processor operation and bus control activity. Its an asymmetric square wave with 33% duty cycle. The range of frequency for different 8086 versions is from 5MHz to 10MHz. VCC : +5V power supply for the operation of the internal circuit. GND ground for the internal circuit. MN/MX : The logic level at this pin decides whether the processor is to operate in either minimum (single processor) or maximum (multiprocessor) mode. The following pin functions are for the minimum mode operation of 8086. M/IO -Memory/IO: This is a status line logically equivalent to S2 in maximum mode. When it is low, it indicates the CPU is having an I/O operation, and when it is high, it indicates that the CPU is having a memory operation. This line becomes active in the previous T4 and remains active till final T4 of the current cycle. It is tristated during local bus "hold acknowledge". -Interrupt Acknowledge: This signal is used as a read strobe for interrupt acknowledge cycles. In other words, when it goes low, it means that the processor has accepted the interrupt. It is active low during T2, T3 and TW of each interrupt acknowledge cycle. ALE-Address latch Enable: This output signal indicates the availability of the valid address on the address/data lines, and is connected to latch enable input of latches. This signal is active high and is never tristated. -Data Transmit/Receive: This output is used to decide the direction of data flow through the transreceivers (bidirectional buffers). When the processor sends out data, this signal is high and when the processor is receiving data, this signal is low. Logically, this is equivalent to S1 in maximum mode. Its timing is the same as M/I/O. This is tristated during 'hold acknowledge'. This signal indicates the availability of valid data over the address/data lines. It is used to enable the transreceivers (bidirectional buffers) to separate the data from the multiplexed address/data signal. It is active from the middle ofT2 until the middle of T4 DEN is tristated during 'hold acknowledge' cycle. HOLD, HLDA-Hold/Hold Acknowledge: When the HOLD line goes high, it indicates to the processor that another master is requesting the bus access. The processor, after receiving the HOLD request, issues the hold acknowledge signal on HLDA pin, in the middle of the next clock cycle after completing the current bus (instruction) cycle. At the same time, the processor floats the local bus and control lines. When the processor detects the HOLD line low, it lowers the HLDA signal. HOLD is an asynchronous input, and it should be externally synchronized. S2, S1, S0 -Status Lines: These are the status lines which reflect the type of operation, being carried out by the processor. These become active during T4 of the previous cycle and remain active during T1 and T2 of the current bus cycle. The status lines return to passive state during T3 of the current bus cycle so that they may again become active for the next bus cycle during T4. Any change in these lines during T3 indicates the starting of a new cycle, and return to passive state indicates end of the bus cycle. These status lines are encoded in table 1.3 This output pin indicates that other system bus masters will be prevented from gaining the system bus, while the signal is low. The signal is activated by the 'LOCK' prefix instruction and remains active until the completion of the next instruction. This floats to tri-state off during "hold acknowledge". When the CPU is executing a critical instruction which requires the system bus, the LOCK prefix instruction ensures that other processors connected in the system will not gain the control of the bus. The 8086, while executing the prefixed instruction, asserts the bus lock signal output, which may be connected to an external bus controller. QS1, QS0-Queue Status: These lines give information about the status of the codeprefetch queue. These are active during the CLK cycle after which the queue operation is performed. These are encoded as shown in Table 1.4.  ReQuest/Grant: These pins are used by other local bus masters, in maximum mode, to force the processor to release the local bus at the end of the processor's current bus cycle. Each of the pins is bidirectional with having higher priority than pins have internal pull-up resistors and may be left unconnected. The request! Grant sequence is as follows: 1. A pulse one clock wide from another bus master requests the bus access to 8086. 2. During T4 (current) or T1 (next) clock cycle, a pulse one clock wide from 8086 to the requesting master, indicates that the 8086 has allowed the local bus to float and that it will enter the "hold acknowledge" state at next clock cycle. The CPU's bus interface unit is likely to be disconnected from the local bus of the system. 3. A one clock wide pulse from the another master indicates to 8086 that the 'hold' request is about to end and the 8086 may regain control of the local bus at the next clock cycle. Minimum Mode 8086 System and Timings In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its MN/MX* pin to logic1. In this mode, all the control signals are given out by the microprocessor chip itself. There is a single microprocessor in the minimum mode system. The remaining components in the system are latches, transreceivers, clock generator, memory and I/O devices. Some type of chip selection logic may be required for selecting memory or I/O devices, depending upon the address map of the system. Latches: The latches are generally buffered output D-type flip-flops, like, 74LS373 or 8282. They are used for separating the valid address from the multiplexed address/data signals and are controlled by the ALE signal generated by 8086. Transreceivers Transreceivers are the bidirectional buffers and some times they are called as data amplifiers. They are required to separate the valid data from the time multiplexed address/data signal. They are controlled by two signals, namely, DEN* and DT/R*. The DEN* signal indicates that the valid data is available on the data bus, while DT/R indicates the direction of data, i.e. from or to the processor. Memory: The system contains memory for the monitor and users program storage. Usually, EPROMS are used for monitor storage, while RAMs for users program storage. IO Devices: A system may contain I/O devices for communication with the processor as well as some special purpose I/O devices. Clock Generator: The clock generator generates the clock from the crystal oscillator and then shapes it and divides to make it more precise so that it can be used as an accurate timing reference for the system. The clock generator also synchronizes some external signals with the system clock.  The general system organization is shown in above fig.Since it has 20 address lines and 16 data lines, the 8086 CPU requires three octal address latches and two octal data buffers for the complete address and data separation. The working of the minimum mode configuration system can be better described in terms of the timing diagrams rather than qualitatively describing the operations. The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized in two parts. 1) Timing diagram for read cycle 2) Timing diagram for write cycle. Timing diagram for Read cycle : The read cycle begins in T1 with the assertion of the address latch enable (ALE) signal and also M/IO* signal. During the negative going edge of this signal, the valid address is latched on the local bus. The BHE* and A0 signals address low, high or both bytes. From Tl to T4, the M/IO* signal indicates a memory or I/O operation. At T2 the address is removed from the local bus and is sent to the output. The bus is then tristated. The read (RD*) control signal is also activated in T2.  The read (RD) signal causes the addressed device to enable its data bus drivers. After RD* goes low, the valid data is available on the data bus. The addressed device will drive the READY line high, when the processor returns the read signal to high level, the addressed device will again tristate its bus drivers. Timing diagram for write cycle: A write cycle also begins with the assertion of ALE and the emission of the address. The M/IO* signal is again asserted to indicate a memory or I/O operation. In T2 after sending the address in Tl the processor sends the data to be written to the addressed location. The data remains on the bus until middle of T4 state. The WR* becomes active at the beginning of T2.  The BHE* and A0 signals are used to select the proper byte or bytes of memory or I/O word to be read or written. The M/IO*, RD* and WR* signals indicate the types of data transfer as specified in Table HOLD Response Sequence The HOLD pin is checked at the end of the each bus cycle. If it is received active by the processor before T4 of the previous cycle or during T1 state of the current cycle, the CPU activities HLDA in the next clock cycle and for the succeeding bus cycles, the bus will be given to another requesting master The control control of the bus is not regained by the processor until the requesting master does not drop the HOLD pin low. When the request is dropped by the requesting master, the HLDA is dropped by the processor at the trailing edge of the next clock as shown in fig  Maximum Mode 8086 System and Timings In the maximum mode, the 8086 is operated by strapping the MN/MX* pin to ground. In this mode, the processor derives the status signals S2*, S1* and S0*. Another chip called bus controller derives the control signals using this status information. In the maximum mode, there may be more than one microprocessor in the system configuration. The other components in the system are the same as in the minimum mode system. The general system organization is as shown in the fig1.1 The basic functions of the bus controller chip IC8288, is to derive control signals like RD* and WR* (for memory and I/O devices), DEN*, DT/R*, ALE, etc. using the information made available by the processor on the status lines. The bus controller chip has input lines S2*, S1* and S0* and CLK. These inputs to 8288 are driven by the CPU. It derives the outputs ALE, DEN*, DT/R*, MWTC*, AMWC*, IORC*, IOWC* and AIOWC*. The AEN*, IOB and CEN pins are specially useful for multiprocessor systems. AEN* and IOB are generally grounded. CEN pin is usually tied to +5V.  INTA* pin is used to issue two interrupt acknowledge pulses to the interrupt controller or to an interrupting device.IORC*, IOWC* are I/O read command and I/O write command signals respectively. These signals enable an IO interface to read or write the data from or to the addressed port. The MRDC*, MWTC* are memory read command and memory write command signals respectively and may be used as memory read and write signals. All these command signals instruct the memory to accept or send data from or to the bus. For both of these write command signals, the advanced signals namely AIOWC* and AMWTC* are available. They also serve the same purpose, but are activated one clock cycle earlier than the IOWC* and MWTC* signals, respectively. The maximum mode system is shown in fig. 1.1. The maximum mode system timing diagrams are also divided in two portions as read (input) and write (output) timing diagrams. The address/data and address/status timings are similar to the minimum mode. ALE is asserted in T1, just like minimum mode. The only difference lies in the status signals used and the available control and advanced command signals. The fig. 1.2 shows the maximum mode timings for the read operation while the fig. 1.3 shows the same for the write operation. Fig. 1.2 Memory Read Timing in Maximum Mode Fig. 1.3 Memory Write Timing in Maximum Mode  UNIT -II  Instruction Set and Assembly Language Programming of 8086  Instruction formats, Addressing modes,  Instruction Set  Assembler Directives,  Procedures, Macros  Simple Programs involving Logical  Branch and Call Instructions  Sorting Evaluating Arithmetic Expressions  String Manipulations  UNIT-II The instruction format contains two fields  operation code / opcode  Operand field OPERATION CODE / OPCODE:  It indicates the type of the operation to be performed by CPU  Example : MOV , ADD … OPERAND:  The CPU executes the instruction using the information resides in these fields. There are six general formats of instructions in 8086 instruction set. The instruction of 8086 vary from 1to 6 bytes length ONE BYTE INSTRUCTION:  It is only one byte long and may have implied data or register operands.  The least three significant 3 bits of the opcode are used for specifying register operand if any otherwise all the 8 bits form an opcode and the operands are implied. REGISTER TO REGISTER  The format is 2 byte long  The first byte of the code specifies the opcode and width  The second byte of the code shows the register operand and R/M field  The Register represented by REG is one of the operands. The R/M field specifies another register or memory location.ie the other operand REGISTER TO/FROM MEMORY WITH NO DISPLACEMENT  The format is 2 byte long  This is similar to the register to register format except for the MOD field is shown.  The MOD field shows the mode of addressing REGISTER TO/FROM MEMORY WITH DISPLACEMENT  The format contains one or two additional bytes for displacement along with 2 bytes Register to/from memory with no displacement. IMMEDIATE OPERAND TO REGISTER  The first byte as well as the 3 bits from the second byte which are used for REG field in case of Register to register format or used for OPCODE.  It also contains one are two bytes of data.  IMMEDIATE OPERAND TO MEMORY WITH 16 BIT DISPLACEMENTS  It requires 5 to 6 bytes for coding  The first two bytes contains the information regarding OPCODE,MOD and R/M fields  The remaining 4 bytes contains 2 bytes of displacement and 2 bytes of data ADDRESSING MODES OF 8086 According two the flow of instructions may be categorized as 1. Sequential Control flow instructions 2. Control transfer instructions Sequential control flow instructions are the instructions which after execution transfer control to the next instruction appearing immediately. The control transfer instructions transfer control to some predefined address or the address somehow specified in the instruction after their execution. What is addressing mode? The different ways in which a source operand is denoted in an instruction are known as addressing mode the addressing modes for sequential control flow instructions are 1. Immediate Addressing Mode 2. Direct Addressing mode 3. Register Addressing mode 4. Register Indirect Addressing mode 5. Indexed Addressing Mode 6. Register Relative addressing mode 7. Based indexed addressing mode 8. Relative based indexed Addressing mode IMMEDIATE ADDRESSING MODE The addressing mode in which the data operand is a part of the instruction itself is known as immediate addressing mode. Example MOV DL, 08H The 8-bit data (08H) given in the instruction is moved to DL (DL)  08H MOV AX, 0A9FH The 16-bit data (0A9FH) given in the instruction is moved to AX register (AX)  0A9FH DIRECT ADDRESSING MODE The addressing mode in which the effective address of the memory location at which the data operand is stored is given in the instruction. The effective address (Offset) is just a 16-bit number written directly in the instruction. Example:MOV BX, [1354H] MOV BL, [0400H] The square brackets around the 1354H denote the contents of the memory location. When executed, this instruction will copy the contents of the memory location into BX register. This addressing mode is called direct because the displacement of the operand from the segment base is specified directly in the instruction. REGISTER ADDRESSING MODE The instruction will specify the name of the register which holds the data to be operated by the instruction. All registers except IP may be used in this mode Example: MOV CL, DH The content of 8-bit register DH is moved to another 8-bit register CL (CL)  (DH) REGISTER INDIRECT ADDRESSING MODE This addressing mode allows data to be addressed at any memory location through an offset address held in any of the following registers: BP, BX, DI & SI. Example MOV AX, [BX]; suppose the register BX contains 4895H, then the contents ; 4895H are moved to AX ADD CX, {BX} INDEXED ADDRESSING MODE In this addressing mode, the operands offset address is found by adding the contents of SI or DI register and 8-bit/16-bit displacements. DS and ES are the default segments for index registers SI and DI respectively. This is the special case of the of register indirect addressing mode. Example MOV BX, [SI+16], ADD AL, [DI+16] REGISTER RELATIVE ADDRESSING MODE In register relative Addressing, BX, BP, SI and DI is used to hold the base value for effective address and a signed 8-bit or unsigned 16-bit displacement will be specified in the instruction. In case of 8-bit displacement, it is sign extended to 16-bit before adding to the base value. When BX holds the base value of EA, 20-bit physical address is calculated from BX and DS.When BP holds the base value of EA, BP and SS is used. Example: MOV AX, [BX + 08H] MOV AX, 08H [BX] BASED INDEXED ADDRESSING MODE In this addressing mode, the offset address of the operand is computed by summing the base register to the contents of an Index register. The default segment registers may be ES or DS Example: MOV DX, [BX + SI] MOV DX, [BX][SI] RELATIVE BASED INDEXED ADDRESSING MODE In this addressing mode, the operands offset is computed by adding the base register contents. An Index registers contents and 8 or 16-bit displacement. Example MOV AX, [BX+DI+08] ADD CX, [BX+SI+16] CONTROL TRANSFER INSTRUCTIONS ADDRESSING MODES /BRANCH ADDRESSING MODE The control transfer instructions transfer control to some predefined address or the address somehow specified in the instruction after their execution Examples : INT , CALL ,RET and JUMP instructions The control transfer instruction the addressing modes depend upon whether destination location is within the same segment or a different one.It also depends on the method of passing the destination address to the processor Basically there are two methods for passing control transfer instructions 1. Intersegment addressing mode 2. Intrasegment addressing mode INTRASEGMENT ADDRESSING MODE If the destination location is within the same segment the mode is called intrasegment addressing mode There are two types 1. Intrasegement direct mode 2. Intrasegment indirect mode INTRASEGMENT DIRECT MODE: In this mode the address to which the control is to be transferred lies within the segment in which the control transfer instruction lies and appears directly in the instruction as an immediate displacement value.The displacement is computed relative to the content of the instruction pointer IP. JMP SHORT LABEL; is a control transfer instruction following intra segment direct mode. Here, SHORT LABEL represents a signed displacement. INTRASEGMENT INDIRECT MODE : In this mode the displacement to which the control is to be transferred is in the same segment in which the control transfer instruction lies but it is passed to the instruction indirectly Here the branch address is found as the content of a register or a memory location. Example JMP [AX] INTERSEGMENT ADDRESSING MODE If the destination location is in the different segment the mode is called intersegment addressing mode There are two types 1. Intersegment direct mode 2. Intersegment indirect mode INTERSEGMENT DIRECT MODE: In this mode the address to which the control is to be transferred is in a different segment this addressing mode provides a means of branching from one code segment to another code segment. Here the CS and IP of the destination address are specified directly in the instruction. Example JMP 2000H: 3000H; INTERSEGMENT INDIRECT MODE : In this the address to which the control is to be transferred lies in a different segment and it is passed to the instruction indirectly.Content of memory block containing four bytes IP(LSB) ,IP(MSB),CS(LSB) and CS(MSB) sequentially The starting address of the memory block may be referred using any of the addressing mode except immediate mode. Example JMP [5000H]; INSTRUCTION SET OF 8086 The 8086 microprocessor supports 8 types of instructions −  Data Transfer Instructions  Arithmetic Instructions  logical Instructions  String Instructions  Program Execution Transfer Instructions (Branch & Loop Instructions)  Processor Control Instructions  Iteration Control Instructions  Interrupt Instructions 1. DATA TRANSFER INSTRUCTIONS These instructions are used to transfer the data from the source operand to the destination operand. Following are the list of instructions under this group − INSTRUCTION TO TRANSFER A WORD  MOV − Used to copy the byte or word from the provided source to the provided destination.  PPUSH − Used to put a word at the top of the stack.  POP − Used to get a word from the top of the stack to the provided location.  PUSHA − Used to put all the registers into the stack.  POPA − Used to get words from the stack to all registers.   XCHG − Used to exchange the data from two locations.  XLAT − Used to translate a byte in AL using a table in the memory. INSTRUCTIONS FOR INPUT AND OUTPUT PORT TRANSFER  IN − Used to read a byte or word from the provided port to the accumulator.  OUT − Used to send out a byte or word from the accumulator to the provided port. INSTRUCTIONS TO TRANSFER THE ADDRESS  LEA − Used to load the address of operand into the provided register.  LDS − Used to load DS register and other provided register from the memory  LES − Used to load ES register and other provided register from the memory. INSTRUCTIONS TO TRANSFER FLAG REGISTERS  LAHF − Used to load AH with the low byte of the flag register.  SAHF − Used to store AH register to low byte of the flag register.  PUSHF − Used to copy the flag register at the top of the stack.  POPF − Used to copy a word at the top of the stack to the flag register. 2. ARITHMETIC INSTRUCTIONS These instructions are used to perform arithmetic operations like addition, subtraction, multiplication, division, etc. Following is the list of instructions under this group − INSTRUCTIONS TO PERFORM ADDITION  ADD − Used to add the provided byte to byte/word to word.  ADC − Used to add with carry.  INC − Used to increment the provided byte/word by 1.  AAA − Used to adjust ASCII after addition.  DAA − Used to adjust the decimal after the addition/subtraction operation. INSTRUCTIONS TO PERFORM SUBTRACTION  SUB − Used to subtract the byte from byte/word from word.  SBB − Used to perform subtraction with borrow.  DEC − Used to decrement the provided byte/word by 1.  NPG − Used to negate each bit of the provided byte/word and add 1/2’s complement.  CMP − Used to compare 2 provided byte/word.  AAS − Used to adjust ASCII codes after subtraction.  DAS − Used to adjust decimal after subtraction. INSTRUCTION TO PERFORM MULTIPLICATION  MUL − Used to multiply unsigned byte by byte/word by word.  IMUL − Used to multiply signed byte by byte/word by word.  AAM − Used to adjust ASCII codes after multiplication. INSTRUCTIONS TO PERFORM DIVISION  DIV − Used to divide the unsigned word by byte or unsigned double word by word.  IDIV − Used to divide the signed word by byte or signed double word by word.  AAD − Used to adjust ASCII codes after division.  CBW − Used to fill the upper byte of the word with the copies of sign bit of the lower byte.  CWD − Used to fill the upper word of the double word with the sign bit of the lower word. 3. LOGICAL INSTRUCTIONS These instructions are used to perform operations where data bits are involved, i.e. operations like logical, shift, etc. Following is the list of instructions under this group − INSTRUCTIONS TO PERFORM LOGICAL OPERATION  NOT − Used to invert each bit of a byte or word.  AND − Used for adding each bit in a byte/word with the corresponding bit in another byte/word.  OR − Used to multiply each bit in a byte/word with the corresponding bit in another byte/word.  XOR − Used to perform Exclusive-OR operation over each bit in a byte/word with the corresponding bit in another byte/word.  TEST − Used to add operands to update flags, without affecting operands. INSTRUCTIONS TO PERFORM SHIFT OPERATIONS  SHL/SAL − Used to shift bits of a byte/word towards left and put zero(S) in LSBs.  SHR − Used to shift bits of a byte/word towards the right and put zero(S) in MSBs.  SAR − Used to shift bits of a byte/word towards the right and copy the old MSB into the new MSB. INSTRUCTIONS TO PERFORM ROTATE OPERATIONS  ROL − Used to rotate bits of byte/word towards the left, i.e. MSB to LSB and to Carry Flag [CF].  ROR − Used to rotate bits of byte/word towards the right, i.e. LSB to MSB and to Carry Flag [CF].   RCR − Used to rotate bits of byte/word towards the right, i.e. LSB to CF and CF to MSB.  RCL − Used to rotate bits of byte/word towards the left, i.e. MSB to CF and CF to LSB. 4. STRING INSTRUCTIONS String is a group of bytes/words and their memory is always allocated in a sequential order. Following is the list of instructions under this group −  REP − Used to repeat the given instruction till CX ≠ 0.  REPE/REPZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.  REPNE/REPNZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.  MOVS/MOVSB/MOVSW − Used to move the byte/word from one string to another.  COMS/COMPSB/COMPSW − Used to compare two string bytes/words.  INS/INSB/INSW − Used as an input string/byte/word from the I/O port to the provided memory location.  OUTS/OUTSB/OUTSW − Used as an output string/byte/word from the provided memory location to the I/O port.  SCAS/SCASB/SCASW − Used to scan a string and compare its byte with a byte in AL or string word with a word in AX.  LODS/LODSB/LODSW − Used to store the string byte into AL or string word into AX. 5. PROGRAM EXECUTION TRANSFER INSTRUCTIONS (BRANCH AND LOOP INSTRUCTIONS) These instructions are used to transfer/branch the instructions during an execution. It includes the following instructions − Instructions to transfer the instruction during an execution without any condition −  CALL − Used to call a procedure and save their return address to the stack.  RET − Used to return from the procedure to the main program.  JMP − Used to jump to the provided address to proceed to the next instruction. Instructions to transfer the instruction during an execution with some conditions −  JA/JNBE − Used to jump if above/not below/equal instruction satisfies.  JAE/JNB − Used to jump if above/not below instruction satisfies.  JBE/JNA − Used to jump if below/equal/ not above instruction satisfies.  JC − Used to jump if carry flag CF = 1  JE/JZ − Used to jump if equal/zero flag ZF = 1  JG/JNLE − Used to jump if greater/not less than/equal instruction satisfies.   JGE/JNL − Used to jump if greater than/equal/not less than instruction satisfies.  JL/JNGE − Used to jump if less than/not greater than/equal instruction satisfies.  JLE/JNG − Used to jump if less than/equal/if not greater than instruction satisfies.  JNC − Used to jump if no carry flag (CF = 0)  JNE/JNZ − Used to jump if not equal/zero flag ZF = 0  JNO − Used to jump if no overflow flag OF = 0  JNP/JPO − Used to jump if not parity/parity odd PF = 0  JNS − Used to jump if not sign SF = 0  JO − Used to jump if overflow flag OF = 1  JP/JPE − Used to jump if parity/parity even PF = 1  JS − Used to jump if sign flag SF = 1 6. PROCESSOR CONTROL INSTRUCTIONS These instructions are used to control the processor action by setting/resetting the flag values. Following are the instructions under this group −  STC − Used to set carry flag CF to 1  CLC − Used to clear/reset carry flag CF to 0  CMC − Used to put complement at the state of carry flag CF.  STD − Used to set the direction flag DF to 1  CLD − Used to clear/reset the direction flag DF to 0  STI − Used to set the interrupt enable flag to 1, i.e., enable INTR input.  CLI − Used to clear the interrupt enable flag to 0, i.e., disable INTR input. 7. ITERATION CONTROL INSTRUCTIONS These instructions are used to execute the given instructions for number of times. Following is the list of instructions under this group −  LOOP − Used to loop a group of instructions until the condition satisfies, i.e., CX =0  LOOPE/LOOPZ − Used to loop a group of instructions till it satisfies ZF = 1 & CX = 0  LOOPNE/LOOPNZ − Used to loop a group of instructions till it satisfies ZF = 0 & CX = 0  JCXZ − Used to jump to the provided address if CX = 0 8. INTERRUPT INSTRUCTIONS These instructions are used to call the interrupt during program execution.   INT − Used to interrupt the program during execution and calling service specified.  INTO − Used to interrupt the program during execution if OF = 1  IRET − Used to return from interrupt service to the main program ASSEMBLER DIRECTIVES Assembler directives are the Instructions to the Assembler, linker and loader regarding the program being executed. also called ‘pseudo instructions. Control the generation of machine codes and organization of the program; but no machine codes are generated for assembler directives. They are used to › specify the start and end of a program › attach value to variables › allocate storage locations to input/ output data › define start and end of segments, procedures, macros etc.. ASSUME Used to tell the assembler the name of the logical segment it should use for a specified segment. You must tell the assembler that what to assume for any segment you use in the program. Example ASSUME: CODE Tells the assembler that the instructions for the program are in segment named CODE. DB – Defined Byte Used to declare a byte type variable or to set aside one or more locations of type byte in memory. Example PRICES DB 49H, 98H, 29H: Declare array of 3 bytes named PRICES and initialize 3 bytes as shown. DD – Define Double Word Used to declare a variable of type doubleword or to reserve a memory location which can be accessed as doubleword. DQ – Define Quadword Used to tell the assembler to declare the variable as 4 words of storage in memory. DT – Define Ten Bytes Used to tell the assembler to declare the variable which is 10 bytes in length or reserve 10 bytes of storage in memory. DW – Define Word Used to tell the assembler to define a variable type as word or reserve word in memory. DUP: used to initialize several locations and to assign values to location END – End the Program To tell the assembler to stop fetching the instruction and end the program execution. ENDP – it is used to end the procedure. ENDS – used to end the segment. EQU – EQUATE Used to give name to some value or symbol. EVEN – Align On Even Memory Address Tells the assembler to increment the location counter to the next even address if it is not already at an even address. EXTRN Used to tell the assembler that the name or labels following the directive are in some other assembly module. GLOBAL – Declares Symbols As Public Or Extrn Used to make the symbol available to other modules.It can be used in place of EXTRN or PUBLIC keyword. GROUP – Group related segment Used to tell the assembler to group the logical segments named after the directive into one logical segment. This allows the content of all the segments to be accessed from the same group. INCLUDE – include source code from file Used to tell the assembler to insert a block of source code from the named file into the current source module. This shortens the source code. LABEL Used to give the name to the current value in the location counter. The LABEL directive must be followed by a term which specifies the type you want associated with that name. LENGTH Used to determine the number of items in some data such as string or array. NAME Used to give a specific name to a module when the programs consisting of several modules. OFFSET It is an operator which tells the assembler to determine the offset or displacement of named data item or procedure from the start of the segment which contains it. ORG – Originate Tells the assembler to set the location counter value. Example, ORG 7000H sets the location counter value to point to 7000H location in memory. $ is often used to symbolically represent the value of the location counter. It is used with ORG to tell the assembler to change the location according to the current value in the location counter. E.g. ORG $+100.  UNIT -III I/O Interface  8255 PPI  Various Modes of Operation and Interfacing to 8086  D/A and A/D Converter  Stepper motor  Interfacing of DMA controller 8257 Interfacing with advanced devices  Memory Interfacing to 8086  Interrupt Structure of 8086  Interrupt Vector Table, Interrupt Service Routine  architecture of 8259. Communication Interface  Serial Communication Standards  Serial Data Transfer Schemes  8251 USART Architecture and Interfacing.  UNIT-3 I/O Interface Introduction: Any application of a microprocessor based system requires the transfer of data between external circuitry to the microprocessor and microprocessor to the external circuitry. User can give information to the microprocessor based system using keyboard and user can see the result or output information from the microprocessor based system with the help of display device. The transfer of data between keyboard and microprocessor, and microprocessor and display device is called input/output data transfer or I/O data transfer. This data transfer is done with the help of I/O ports. Input port: It is used to read data from the input device such as keyboard. The simplest form of input port is a buffer. The input device is connected to the microprocessor through buffer, as shown in the fig.1. This buffer is a tri-state buffer and its output is available only when enable signal is active. When microprocessor wants to read data from the input device (keyboard), the control signals from the microprocessor activates the buffer by asserting enable input of the buffer. Once the buffer is enabled, data from the input device is available on the data bus. Microprocessor reads this data by initiating read command. Output port: It is used to send data to the output device such as display from the microprocessor. The simplest form of output port is a latch. The output device is connected to the microprocessor through latch, as shown in the fig.2. When microprocessor wants to send data to the output device is puts the data on the data bus and activates the clock signal of the latch, latching the data from the data bus at the output of latch. It is then available at the output of latch for the output device. Serial and Parallel Transmission: In telecommunications, serial transmission is the sequential transmission of signal elements of a group representing a character or other entity of data. Digital serial transmissions are bits sent over a single wire, frequency or optical path sequentially. Because it requires less signal processing and less chance for error than parallel transmission, the transfer rate of each individual path may be faster. This can be used over longer distances as a check digit or parity bit can be sent along it easily. In telecommunications, parallel transmission is the simultaneous transmission of the signal elements of a character or other entity of data. In digital communications, parallel transmission is the simultaneous transmission of related signal elements over two or more separate paths. Multiple electrical wires are used which can transmit multiple bits simultaneously, which allows for higher data transfer rates than can be achieved with serial transmission. This method is used internally within the computer, for example the internal buses, and sometimes externally for such things as printers, The major issue with this is "skewing" because the wires in parallel data transmission have slightly different properties (not intentionally) so some bits may arrive before others, which may corrupt the message. A parity bit can help to reduce this. However, electrical wire parallel data transmission is therefore less reliable for long distances because corrupt transmissions are far more likely. Interrupt driven I/O: In this technique, a CPU automatically executes one of a collection of special routines whenever certain condition exists within a program or a processor system. Example CPU gives response to devices such as keyboard, sensor and other components when they request for service. When the CPU is asked to communicate with devices, it services the devices. Example each time you type a character on a keyboard, a keyboard service routine is called. It transfers the character you typed from the keyboard I/O port into the processor and then to a data buffer in memory. The interrupt driven I/O technique allows the CPU to execute its main program and only stop to service I/O device when it is told to do so by the I/O system as shown in fig.3. This method provides an external asynchronous input that would inform the processor that it should complete whatever instruction that is currently being executed and fetch a new routine that will service the requesting device. Once this servicing is completed, the processor would resume exactly where it left off. An analogy to the interrupt concept is in the classroom, where the professor serves as CPU and the students as I/O ports. The classroom scenario for this interrupt analogy will be such that the professor is busy in writing on the blackboard and delivering his lecture. The student raises his finger when he wants to ask a question (student requesting for service). The professor then completes his sentence and acknowledges student‟s request by saying “YES” (professor acknowledges the interrupt request). After acknowledgement from the professor, student asks the question and professor gives answer to the question (professor services the interrupt). After that professor continues its remaining lecture form where it was left. PIO 8255: The parallel input-output port chip 8255 is also called as programmableperipheral input-output port. The Intel‟s 8255 are designed for use with Intel‟s 8-bit, 16-bit and higher capability microprocessors. It has 24 input/output lineswhich may be individually programmed in two groups of twelve lines each, orthree groups of eight lines. The two groups of I/O pins are named as Group A and Group B. Each of thesetwo groups contains a subgroup of eight I/O lines called as 8-bit port and anothersubgroup of four lines or a 4-bit port. Thus Group A contains an 8-bit port Aalong with a 4-bit port C upper. The port A lines are identified by symbols PA0-PA7 while the port C lines are identified as PC4-PC7 similarly. Group B contains an 8-bit port B, containing lines PB0- PB7 and a 4-bit port C with lower bits PC0-PC3. The port C upper and port C lower can be used in combination as an 8-bit port C. Both the port Cs is assigned the same address. Thus one may have either three 8-bit I/O ports or two 8-bit and two 4-bit I/O ports from 8255. All of these ports can function independently either as input or as output ports. This can be achieved by programming the bits of an internal register of 8255 called as control word register (CWR). The internal block diagram and the pin configuration of 8255 are shown in figs. The 8-bit data bus buffer is controlled by the read/write control logic. The read/write control logic manages all of the internal and external transfer of both data and control words. RD, WR, A1, A0 and RESET are the inputs, provided by the microprocessor to READ/WRITE control logic of 8255. The 8-bit, 3-state bidirectional buffer is used to interface the 8255 internal data bus with the external system data bus. This buffer receives or transmits data upon the execution of input or output instructions by the microprocessor. The control words or status information is also transferred through the buffer. Pin Diagram of 8255A The pin configuration of 8255 is shown in fig. The port A lines are identified by symbols PA0-PA7 while the port C lines are Identified as PC4-PC7. Similarly, Group B contains an 8-bit port B, containing lines PB0-PB7 and a 4-bit port C with lower bits PC0- PC3. The port C upper and port C lower can be used in combination as an 8-bit port C. Both the port C is assigned the same address. Thus one may have either three 8-bit I/O ports or two 8-bit and two 4-bit ports from 8255. All of these ports can function independently either as input or as output ports. This can be  achieved by programming the bits of an internal register of 8255 called as control word register (CWR). The 8-bit data bus buffer is controlled by the read/write control logic. The read/write control logic manages all of the internal and external transfers of both data and control words. RD,WR, A1, A0 and RESET are the inputs provided by the microprocessor to the READ/ WRITE control logic of 8255. The 8-bit, 3-state bidirectional buffer is used to interface the 8255 internal data bus with the external system data bus. This buffer receives or transmits data upon the execution of input or output instructions by the microprocessor. The control words or status information is also transferred through the buffer. The signal description of 8255 is briefly presented as follows: PA7-PA0: These are eight port A lines that acts as either latched output or buffered input lines depending upon the control word loaded into the control word register. PC7-PC4: Upper nibble of port C lines. They may act as either output latches or input buffers lines. This port also can be used for generation of handshake lines in mode1 or mode2. PC3-PC0: These are the lower port C lines; other details are the same as PC7-PC4 lines. PB0-PB7: These are the eight port B lines which are used as latched output lines or buffered input lines in the same way as port A. RD: This is the input line driven by the microprocessor and should be low to indicate read operation to 8255. WR: This is an input line driven by the microprocessor. A low on this line indicates write operation. CS: This is a chip select line. If this line goes low, it enables the 8255 to respond to RD and WR signals, otherwise RD and WR signal are neglected. D0-D7: These are the data bus lines those carry data or control word to/from the microprocessor. RESET:Logic high on this line clears the control word register of 8255. All ports are set as input ports by default after reset. A1-A0: These are the address input lines and are driven by the microprocessor. These lines A1-A0 with RD, WR and CS from the following operations for 8255. These address lines are used for addressing any one of the four registers, i.e. three ports and a control word register as given in table below. In case of 8086 systems, if the 8255 is to be interfaced with lower order data bus, the A0 and A1 pins of 8255 are connected with A1 and A2 respectively. Modes of Operation of 8255 These are two basic modes of operation of 8255. I/O mode and Bit Set-Reset mode (BSR). In I/O mode, the 8255 ports work as programmable I/O ports, while in BSR mode only port C (PC0-PC7) can be used to set or reset its individual port bits. Under the I/O mode of operation, further there are three modes of operation of 8255, so as to support different types of applications, mode 0, mode 1 and mode 2. BSR Mode: In this mode any of the 8-bits of port C can be set or reset depending on D0 of the control word. The bit to be set or reset is selected by bit select flags D3, D2 and D1 of the CWR as given in table. I/O Modes: a) Mode 0 (Basic I/O mode): This mode is also called as basic input/output Mode. This mode provides simple input and output capabilities using each of the threeports. Data can be simply read from and written to the input and output portsrespectively, after appropriate initialization. The salient features of this mode are as listed below: 1. Two 8-bit ports (port A and port B) and two 4-bit ports (port C upper and lower) are available. The two 4-bit ports can be combined used as a third 8-bit port. 2. Any port can be used as an input or output port. 3. Output ports are latched. Input ports are not latched. 4. A maximum of four ports are available so that overall 16 I/O configurations arepossible. All these modes can be selected by programming a register internal to 8255known as CWR. The control word register has two formats. The first format is valid for I/O modesof operation, i.e. modes 0, mode 1 and mode 2 while the second format is validfor bit set/reset (BSR) mode of operation. These formats are shown in followingfig. b) Mode 1: ( Strobed input/output mode ) In this mode the handshaking control the input and output action of the specified port. Port C lines PC0-PC2, provide strobe orhandshake lines for port B. This group which includes port B and PC0-PC2 is called asgroup B for Strobed data input/output. Port C lines PC3-PC5 provides strobe lines for portA.This group including port A and PC3-PC5 from group A. Thus port C is utilized forgenerating handshake signals. The salient features of mode 1 are listed as follows: 1. Two groups – group A and group B are available for strobed data transfer. 2. Each group contains one 8-bit data I/O port and one 4-bit control/data port. 3. The 8-bit data port can be either used as input and output port. The inputs andoutputs both are latched. 4. Out of 8-bit port C, PC0-PC2 are used to generate control signals for port B andPC3-PC5 are used to generate control signals for port A. the lines PC6, PC7 may be used as independent data lines. The control signals for both the groups in input and output modes areexplained as follows: Input control signal definitions (mode 1): STB (Strobeinput) – If this lines falls to logic low level, the data available at 8- bit input port is loaded into input latches. IBF (Input buffer full) – If this signal rises to logic 1, it indicates that data hasbeen loaded into latches, i.e. it works as an acknowledgement. IBF is set by a lowon STB and is reset by the rising edge of RD input. INTR (Interruptrequest) – This active high output signal can be used tointerrupt the CPU whenever an input device requests the service. INTR is set by ahigh STBpin and a high at IBF pin. INTE is an internal flag that can be controlledby the bit set/reset mode of either PC4 (INTEA) or PC2 (INTEB) as shown in fig. INTR is reset by a falling edge of RD input. Thus an external input device can berequest the service of the processor by putting the data on the bus and sending thestrobe signal. Output control signal definitions (mode 1): OBF (Output buffer full) – This status signal, whenever falls to low, indicatesthat CPU has written data to the specified output port. The OBF flip- flop will beset by a rising edge of WR signal and reset by a low going edge at the ACKinput. ACK (Acknowledgeinput) – ACK signal acts as an acknowledgement to begiven by an output device. ACK signal, whenever low, informs the CPU that thedata transferred by the CPU to the output device through the port is received bythe output device. INTR (Interruptrequest) – Thus an output signal that can be used to interruptthe CPU when an output device acknowledges the data received from the CPU.INTR is set when ACK, OBF and INTE are 1. It is reset by a fallingedge on WRinput. The INTEA and INTEB flags are controlled by the bit set-reset mode ofPC6 and PC2 respectively. c) Mode 2 (Strobed bidirectional I/O): This mode of operation of 8255 is alsocalled as strobed bidirectional I/O. This mode of operation provides 8255 with additional features for communicating with a peripheral device on an 8-bit databus. Handshaking signals are provided to maintain proper data flow andsynchronization between the data transmitter and receiver. The interruptgeneration and other functions are similar to mode 1. In this mode, 8255 is a bidirectional 8-bit port with handshake signals. The Rdand WR signals decide whether the 8255 is going to operate as an input port oroutput port. The Salient features of Mode 2 of 8255 are listed as follows: 1. The single 8-bit port in group A is available. 2. The 8-bit port is bidirectional and additionally a 5-bit control port is available. 3. Three I/O lines are available at port C.( PC2 – PC0 ) 4. Inputs and outputs are both latched.  5. The 5-bit control port C (PC3-PC7) is used for generating / accepting handshakesignals for the 8-bit data transfer on port A. Control signal definitions in mode 2: INTR – (Interrupt request) As in mode 1, this control signal is active high and isused to interrupt the microprocessor to ask for transfer of the next data byteto/from it. This signal is used for input (read) as well as output (write) operations. Control Signals for Output operations: OBF (Output buffer full) – This signal, when falls to low level, indicates that theCPU has written data to port A. ACK (Acknowledge) This control input, when falls to logic low level, Acknowledges that the previous data byte is received by the destination and nextbyte may be sent by the processor. This signal enables the internal tristate buffersto send the next data byte on port A. INTE1 ( A flag associated with OBF ) This can be controlled by bit set/resetmode with PC6. Control signals for input operations: STB (Strobe input)a low on this line is used to strobe in the data into the inputLatches of 8255. IBF (Input buffer full) when the data is loaded into input buffer, this signal risesto logic „1‟. This can be used as an acknowledge that the data has been receivedby the receiver. The waveforms in fig show the operation in Mode 2 for output as well as inputport. Note: WR must occur before ACK and STB must be activated before RD. The following fig shows a schematic diagram containing an 8-bit bidirectionalport, 5-bit control port and the relation of INTR with the control pins. Port B caneither be set to Mode 0 or 1 with port A( Group A ) is in Mode 2. Mode 2 is not available for port B. The following fig shows the control word. The INTR goes high only if IBF, INTE2, STB and RD go high or OBF, INTE1, ACK and WR go high. The port C can be read to know the status of theperipheral device, in terms of the control signals, using the normal I/Oinstructions. Interfacing Analog to Digital Data Converters:  In most of the cases, the PIO 8255 is used for interfacing the analog to digital converters with microprocessor.  We have already studied 8255 interfacing with 8086 as an I/O port, in previous section. This section we will only emphasize the interfacing techniques of analog to digital converters with 8255.  The analog to digital converters is treated as an input device by the microprocessor that sends an initializing signal to the ADC to start the analogy to digital data conversation process. The start of conversation signal is a pulse of a specific duration.  The process of analog to digital conversion is a slow  Process and the microprocessor have to wait for the digitaldata till the conversion is over. After the conversion isover, the ADC sends end of conversion EOC signal toinform themicroprocessor that the conversion is over andthe result is ready at the output buffer of the ADC. Thesetasks of issuing an SOC pulse to ADC, reading EOC signalfrom the ADC and reading the digital output of the ADCare carried out by the CPU using 8255 I/O ports.  The time taken by the ADC from the active edge of SOCpulse till the active edge of EOC signal is called as theconversion delay of the ADC.  It may range anywhere from a few microseconds in caseof fast ADC to even a few hundred milliseconds in case ofslow ADCs.  The available ADC in the market use different conversiontechniques for conversion of analog signal to digitals.Successive approximation techniques and dual slopeintegration techniques are the most popular techniquesused in the integrated ADC chip.  General algorithm for ADC interfacing contains thefollowing steps:  Ensure the stability of analog input, applied to the ADC.  Issue start of conversion pulse to ADC  Read end of conversion signal to mark the end ofconversion processes.  Read digital data output of the ADC as equivalent digitaloutput.  Analog input voltage must be constant at the input of theADC right from the start of conversion till the end of theconversion to get correct results. This may be ensured by asample and hold circuit which samples the analog signaland holds it constant for specific time duration. Themicroprocessor may issue a hold signal to the sample andhold circuit.  If the applied input changes before the completeconversion process is over, the digital equivalent of theanalog input calculated by the ADC may not be correct.  ADC 0808/0809:  The analog to digital converter chips 0808 and 0809 are 8-bit CMOS, successive approximation converters. This technique is one of the fast techniques for analog to digital conversion. The conversion delay is 100µs at a clock frequency of 640 KHz, which is quite low as compared to other converters. These converters do not need any external zero or full scale adjustments as they are already taken care of by internal circuits.  These converters internally have a 3:8 analog multiplexer so that at a time eight different analog conversion by using address lines - ADD A, ADD B, ADD C, as shown. Using these address inputs, multichannel data acquisition system can be designed using a single ADC. The CPU may drive these lines using output port lines in case of multichannel applications. In case of single input applications, these may be hardwired to select the proper input.  There are unipolar analog to digital converters, i.e. they are able to convert only positive analog input voltage to their digital equivalent. These chips do not contain any internal sample and hold circuit.  If one needs a sample and hold circuit for the conversion of fast signal into equivalent digital quantities, it has to be externally connected at each of the analog inputs. Fig (1) and Fig (2) show the block diagrams and pin diagrams for ADC 0808/0809. Table.1 Address lines Analog I/P selected C B A I/P 0 0 0 0 I/P 1 0 0 1 I/P 2 0 1 0 I/P 3 0 1 1 I/P 4 1 0 0 I/P 5 1 0 1 I/P 6 1 1 0 I/P 7 1 1 1 Fig.1 Block Diagram of ADC 0808/0809 Fig.2 Pin Diagram of ADC 0808/0809 Some Electrical Specifications Of The ADC 0808/0809 Are Given In Table.2. Table.2 The Timing Diagram Of Different Signals Of Adc0808 Is Shown In Fig.3 Fig.3 Timing Diagram Of ADC 0808. Interfacing ADC0808 with 8086 Interfacing Digital To Analog Converters: The digital to analog converters convert binary numbers into their analog equivalent voltages. The DAC find applications in areas like digitally controlled gains, motor speed controls, programmable gain amplifiers, etc. DAC0800 8-bit Digital to Analog Converter The DAC 0800 is a monolithic 8-bit DAC manufactured by National Semiconductor. It has settling time around 100ms and can operate on a range of power supply voltages i.e. from 4.5V to +18V. Usually the supply V+ is 5V or +12V. The V-pin can be kept at a minimum of -12V. Pin Diagram of DAC 0800 Interfacing DAC0800 with 8086 Ad 7523 8-Bit Multiplying DAC: Intersil‟s AD 7523 is a 16 pin DIP, multiplying digital to analog converter, containing R-2R ladder(R=10KΩ) for digital to analog conversion along with single pole double through NMOS switches to connect the digital inputs to the ladder. Pin Diagram of AD7523 The supply range extends from +5V to +15V , while Vref may be anywhere between -10V to +10V. The maximum analog output voltage will be +10V, when all the digital inputs are at logic high state. Usually a Zener is connected between OUT1 and OUT2 to save the DAC from negative transients. An operational amplifier is used as a current to voltage converter at the output of AD 7523 to convert the current output of AD7523 to a proportional output voltage. 111  It also offers additional drive capability to the DAC output. An external feedback resistor acts to control the gain. One may not connect any external feedback resistor, if no gain control is required. Interfacing AD7523 with 8086 Stepper Motor Interfacing: A stepper motor is a device used to obtain an accurate position control of rotating shafts. It employs rotation of its shaft in terms of steps, rather than continuous rotation as in case of AC or DC motors. To rotate the shaft of the stepper motor, a sequence of pulses is needed to be applied to the windings of the stepper motor, in a proper sequence. The number of pulses required for one complete rotation of the shaft of the stepper motor is equal to its number of internal teeth on its rotor. The stator teeth and the rotor teeth lock with each other to fix a position of the shaft. With a pulse applied to the winding input, the rotor rotates by one teeth position or an angle x. The angle x may be calculated as: X=3600/no. of rotor teeth After the rotation of the shaft through angel x, the rotor locks itself with the next tooth in the sequence on the internal surface of stator. The internal schematic of a typical stepper motor with four windings is shown in fig.1. The stepper motors have been designed to work with digital circuits. Binary level pulses of 0-5V are required at its winding inputs to obtain the rotation of shafts. The sequence of the pulses can be decided, depending upon the required motion of the shaft.  Fig.2 shows a typical winding arrangement of the stepper motor. Fig.3 shows conceptual positioning of the rotor teeth on the surface of rotor, for a six teeth rotor. Fig.1 Internal schematic of a four winding stepper motor Fig.2 Winding arrangement of a stepper motor. Fig.3 Stepper motor rotor The circuit for interfacing a winding Wn with an I/O port is given in fig.4. Each of the windings of a stepper motor needs this circuit for its interfacing with the output port. A typical stepper motor may have parameters like torque 3 Kg-cm, operating voltage 12V, current rating 0.2 A and a step angle 1.8 0 i.e. 200 steps/revolution (number of rotor teeth).  A simple schematic for rotating the shaft of a stepper motor is called a wave scheme. In this scheme, the windings Wa, Wb, Wc and Wd are applied with the required voltages pulses, in a cyclic fashion. By reversing the sequence of excitation, the direction of rotation of the stepper motor shaft may be reversed. Table.1 shows the excitation sequences for clockwise and anticlockwise rotations. Another popular scheme for rotation of a stepper motor shaft applies pulses to two successive windings at a time but these are shifted only by one position at a time. This scheme for rotation of stepper motor shaft is shown in table2. Fig.4 interfacing stepper motor winding. Table.1 Excitation sequence of a stepper motor using wave switching scheme. Motion step A B C D 1 1 0 0 0 2 0 1 0 0 Clock wise 3 0 0 1 0 4 0 0 0 1 5 1 0 0 0 1 1 0 0 0 2 0 0 0 1 Anticlock 3 0 0 1 0 wise 4 0 1 0 0 5 1 0 0 0  Table.2 An alternative scheme for rotating stepper motor shaft Motion step A B C D 1 0 0 1 1 2 0 1 1 0 Clock wise 3 1 1 0 0 4 1 0 0 1 5 0 0 1 1 1 0 0 1 1 2 1 0 0 1 Anticlock 3 1 1 0 0 wise 4 0 1 1 0 5 0 0 0 0 Keyboard Interfacing  In most keyboards, the key switches are connected in a matrix of Rows and Columns.  Getting meaningful data from a keyboard requires three major tasks: 1. D e t e c t a k e y p r e s s 2. D e b o u n c e t h e k e y p r e s s. 3. Encode the keypress (produce a standard code for the pressed key). Logic „0‟ is read by the microprocessor when the key is pressed. Key Debounce: Whenever a mechanical push-bottom is pressed or released once,the mechanical components of the key do not change the positionsmoothly; rather it generates a transient response. These may be interpreted as the multiple pressures and responded accordingly. The rows of the matrix are connected to four output Port lines, &columns are connected to four input Port lines. When no keys are pressed, the column lines are held high by the pull-up resistors connected to +5v. Pressing a key connects a row & a column. To detect if any key is pressed is to output 0‟s to all rows & then check columns to see it a pressed key has connected a low (zero) to a column. Once the columns are found to be all high, the program enters another loop, which waits until a low appears on one of the columns i.e indicating a key press. A simple 20/10 msec delay is executed to debounce task. After the debounce time, another check is made to see if the key is still pressed. If the columns are now all high, then no key is pressed & the initial detection was caused by a noise pulse. To avoid this problem, two schemes are suggested: 1. Use of Bistablemultivibrator at the output of the key to debounce it. 2. The microprocessor has to wait for the transient period (at least for 10 ms), so that the transient response settles down and reaches a steady state. If any of the columns are low now, then the assumption is made that it was a valid key press.  The final task is to determine the row & column of the pressed key &convert this information to He