Microprocessors-and-Microcontrollers.pdf

Microprocessor and Microcontroller UNIT I – 8085 MICROPROCESSOR 1.1 Introduction Microcomputer: The term microcomputer is generally synonymous with personal computer, or a computer that depends on a microprocessor.  Microco...

Microprocessor and Microcontroller UNIT I – 8085 MICROPROCESSOR 1.1 Introduction Microcomputer: The term microcomputer is generally synonymous with personal computer, or a computer that depends on a microprocessor.  Microcomputers are designed to be used by individuals, whether in the form of PCs, workstations or notebook computers.  A microcomputer contains a CPU on a microchip (the microprocessor), a memory system (typically ROM and RAM), a bus system and I/O ports, typically housed in a motherboard. Microprocessor: A silicon chip that contains a CPU. In the world of personal computers, the terms microprocessor and CPU are used interchangeably.  A microprocessor (sometimes abbreviated µP) is a digital electronic component with miniaturized transistors on a single semiconductor integrated circuit (IC).  One or more microprocessors typically serve as a central processing unit (CPU) in a computer system or handheld device.  Microprocessors made possible the advent of the microcomputer.  At the heart of all personal computers and most working stations sits a microprocessor.  Microprocessors also control the logic of almost all digital devices, from clock radios to fuel-injection systems for automobiles.  Three basic characteristics differentiate microprocessors:  Instruction set: The set of instructions that the microprocessor can execute.  Bandwidth: The number of bits processed in a single instruction.  Clock speed: Given in megahertz (MHz), the clock speed determines how many instructions per second the processor can execute.  In both cases, the higher the value, the more powerful the CPU. For example, a 32-bit microprocessor that runs at 50MHz is more powerful than a 16-bit microprocessor that runs at 25MHz. 1  Dr. N. Karuppiah & Dr. S. Ravivarman  In addition to bandwidth and clock speed, microprocessors are classified as being either RISC (reduced instruction set computer) or CISC (complex instruction set computer) 1.2 8085 Microprocessor The Intel 8085 is an 8-bit microprocessor introduced by Intel in 1977. It was binary compatible with the more-famous Intel 8080 but required less supporting hardware, thus allowing simpler and less expensive microcomputer systems to be built. The "5" in the model number came from the fact that the 8085 requires only a +5-Volt (V) power supply rather than the +5 V, −5 V and +12 V supplies the 8080 needed. The main features of 8085 μP are:  It is an 8-bit microprocessor.  It is manufactured with N-MOS technology.  It has 16-bit address bus and hence can address up to 216= 65536 bytes (64KB) memory locations through A0–A15.  The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0–AD7  Data bus is a group of 8 lines D0–D7.  It supports external interrupt request.  A 16-bit program counter (PC)  A 16-bit stack pointer (SP)  Six 8-bit general purpose register arranged in pairs: BC, DE, HL.  It requires a signal +5V power supply and operates at 3.2 MHZ single phase clock.  It is enclosed with 40 pins DIP (Dual in line package). 1.3 8085 Architecture 8085 consists of various units as shown in Fig. 1 and each unit performs its own functions. The various units of a microprocessor are listed below  Accumulator  Arithmetic and logic Unit  General purpose register  Program counter  Stack pointer  Temporary register  Flags  Instruction register and Decoder 2  Microprocessor and Microcontroller  Timing and Control unit  Interrupt control  Address buffer and Address-Data buffer  Address bus and Data bus Accumulator Accumulator is nothing but a register which can hold 8-bit data. Accumulator aids in storing two quantities. The data to be processed by arithmetic and logic unit is stored in accumulator. It also stores the result of the operation carried out by the Arithmetic and Logic unit. The accumulator is also called an 8-bit register. The accumulator is connected to Internal Data bus and ALU (arithmetic and logic unit). The accumulator can be used to send or receive data from the Internal Data bus. Arithmetic and Logic Unit There is always a need to perform arithmetic operations like +, -, *, / and to perform logical operations like AND, OR, NOT etc. So, there is a necessity for creating a separate unit which can perform such types of operations. These operations are performed by the Arithmetic and Logic Unit (ALU). ALU performs these operations on 8-bit data. But these operations cannot be performed unless we have an input (or) data on which the desired operation is to be performed. So, from where do these inputs reach the ALU? For this purpose, accumulator is used. ALU gets its Input from accumulator and temporary register. After processing the necessary operations, the result is stored back in accumulator. General Purpose Registers Apart from accumulator 8085 consists of six special types of registers called General Purpose Registers. These general-purpose registers are used to hold data like any other registers. The general-purpose registers in 8085 processors are B, C, D, E, H and L. Each register can hold 8-bit data. Apart from the above function these registers can also be used to work in pairs to hold 16-bit data. They can work in pairs such as B-C, D-E and H-L to store 16-bit data. The H-L pair works as a memory pointer. A memory pointer holds the address of a particular memory location. They can store 16-bit address as they work in pair. 3  Dr. N. Karuppiah & Dr. S. Ravivarman Fig. 1.1 8085 Architecture Program Counter and Stack Pointer Program counter is a special purpose register. Consider that an instruction is being executed by processor. As soon as the ALU finished executing the instruction, the processor looks for the next instruction to be executed. So, there is a necessity for holding the address of the next instruction to be executed in order to save time. This is taken care by the program counter. A program counter stores the address of the next instruction to be executed. In other words, the program counter keeps track of the memory address of the instructions that are being executed by the microprocessor and the memory address of the next instruction that is going to be executed. Microprocessor increments the program whenever an instruction is being executed, so that the program counter points to the memory address of the next instruction that is going to be executed. Program counter is a 16-bit register. Stack pointer is also a 16-bit register which is used as a memory pointer. A stack is nothing but the portion of RAM (Random access memory). So, does that mean the stack pointer points to portion of RAM? 4  Microprocessor and Microcontroller Yes. Stack pointer maintains the address of the last byte that is entered into stack. Each time when the data is loaded into stack, Stack pointer gets decremented. Conversely it is incremented when data is retrieved from stack. Temporary Register As the name suggests this register acts as a temporary memory during the arithmetic and logical operations. Unlike other registers, this temporary register can only be accessed by the microprocessor and it is completely inaccessible to programmers. Temporary register is an 8-bit register. Flags Flags are nothing but a group of individual Flip-flops. The flags are mainly associated with arithmetic and logic operations. The flags will show either a logical (0 or 1) (i.e.) a set or reset depending on the data conditions in accumulator or various other registers. A flag is actually a latch which can hold some bits of information. It alerts the processor that some event has taken place. D7 D6 D5 D4 D3 D2 D1 D0 S Z AC P CY Fig. 1.2 Flag Register Intel processors have a set of 5 flags. 1. Carry flag 2. Parity flag 3. Auxiliary carry flag 4. Zero flag 5. Sign flag Consider two binary numbers. For example 1100 0000 1000 0000 When we add the above two numbers, a carry is generated in the most significant bit. The number in the extreme right is least significant bit, while the number in extreme left is most significant bit. So, a ninth bit is generated due to the carry. So how to accommodate 9th bit in an 8-bit register? For this purpose, the Carry flag is used. The carry flag is set whenever a carry is generated and reset whenever there is no carry. But there is an 5  Dr. N. Karuppiah & Dr. S. Ravivarman auxiliary carry flag? What is the difference between the carry flag and auxiliary carry flag? Let’s discuss with an example. Consider the two numbers given below 0000 1100 0000 1001 When we add both the numbers a carry is generated in the fourth bit from the least significant bit. This sets the auxiliary carry flag. When there is no carry, the auxiliary carry flag is reset. So, whenever there is a carry in the most significant bit Carry flag is set. While an auxiliary carry flag is set only when a carry is generated in bits other than the most significant bit. Parity checks whether it’s even or add parity. This flag returns a 0 if it is odd parity and returns a 1 if it is an even parity. Sometimes they are also called as parity bit which is used to check errors while data transmission is carried out. Zero flag shows whether the output of the operation is 0 or not. If the value of Zero flag is 0 then the result of operation is not zero. If it is zero the flag returns value 1. Sign flag shows whether the output of operation has positive sign or negative sign. A value 0 is returned for positive sign and 1 is returned for negative sign. Instruction Register and Decoder Instruction register is 8-bit register just like every other register of microprocessor. Consider an instruction. The instruction may be anything like adding two data's, moving a data, copying a data etc. When such an instruction is fetched from memory, it is directed to Instruction register. So, the instruction registers are specifically to store the instructions that are fetched from memory. There is an Instruction decoder which decodes the information present in the Instruction register for further processing. Timing and Control Unit Timing and control unit is a very important unit as it synchronizes the registers and flow of data through various registers and other units. This unit consists of an oscillator and controller sequencer which sends control signals needed for internal and external control of data and other units. The oscillator generates two-phase clock signals which aids in synchronizing all the registers of 8085 microprocessor. Signals that are associated with Timing and control unit are: 6  Microprocessor and Microcontroller Control Signals: RD’, WR’, ALE  ALE is used for provide control signal to synchronize the components of microprocessor and timing for instruction to perform the operation.  RD (Active low) and WR (Active low) are used to indicate whether the operation is reading the data from memory or writing the data into memory respectively. Status Signals: S0, S1, IO/M’  IO/M (Active low) is used to indicate whether the operation belongs to the memory or peripherals. Table 1.1 Status signals and the status of data bus IO/M’ (Active Low) S1 S2 Data Bus Status (Output) 0 0 0 Halt 0 0 1 Memory WRITE 0 1 0 Memory READ 1 0 1 IO WRITE 1 1 0 IO READ 0 1 1 Op code fetch 1 1 1 Interrupt acknowledge DMA Signals: HOLD, HLDA, READY  HOLD: Indicates that another master is requesting the use of the address and data buses. The CPU, upon receiving the hold request, will relinquish the use of the bus as soon as the completion of the current bus transfer. Internal processing can continue. The processor can regain the bus only after the HOLD is removed. When the HOLD is acknowledged, the Address, Data RD, WR and IO/M’ lines are tri-stated.  HLDA: Hold Acknowledge: Indicates that the CPU has received the HOLD request and that it will relinquish the bus in the next clock cycle HLDA goes low after the Hold request is removed. The CPU takes the bus one half-clock cycle after HLDA goes low.  READY: This signal synchronizes the fast CPU and the slow memory, peripherals. If READY is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive 7  Dr. N. Karuppiah & Dr. S. Ravivarman data. If READY is low, the CPU will wait an integral number of clock cycle for READY to go high before completing the read or write cycle. READY must conform to specified setup and hold times. Reset Signals: Reset in, Reset Out RESET IN: A low on this pin;  Sets the program counter to zero (0000H)  Resets the interrupt enables and HLDA flip-flops.  Tri-states the data bus, address bus and control bus.  Affects the content of processors internal registers randomly. On Reset, The Program counter sets to 0000h which causes the 8085 to execute; the first instruction from address 0000H.  RESET OUT: This active high signal indicates that the processor; is being reset. This signal is synchronized to the processor clock and it can be used to reset other devices connected in the system. Interrupt control As the name suggests this control interrupts a process. Consider that a microprocessor is executing the main program. Now whenever the interrupt signal is enabled or requested the microprocessor shifts the control from main program to process the incoming request and after the completion of request, the control goes back to the main program. For example, an Input/output device may send an interrupt signal to notify that the data is ready for input. The microprocessor temporarily stops the execution of main program and transfers control to I/O device. After collecting the input data, the control is transferred back to main program. Interrupt signals present in 8085 are:  INTR  RST 7.5  RST 6.5  RST 5.5  TRAP INTR is maskable 8080A compatible interrupt. When the interrupt occurs the processor fetches from the bus one instruction, usually one of these instructions: One of the 8 RST instructions (RST0 - RST7). The processor saves current program counter into stack and branches to memory location N * 8 (where N is a 3 - bit number from 0 to 7 supplied with the RST instruction). 8  Microprocessor and Microcontroller CALL instruction (3-byte instruction). The processor calls the subroutine, address of which is specified in the second and third bytes of the instruction. RST5.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 2CH (hexadecimal) address. RST6.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 34H (hexadecimal) address. RST7.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 3CH (hexadecimal) address. TRAP is a non-maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 24H (hexadecimal) address. All maskable interrupts can be enabled or disabled using EI and DI instructions. RST5.5, RST6.5 and RST7.5 interrupts can be enabled or disabled individually using SIM instruction. Serial Input/output control The input and output of serial data can be carried out using 2 instructions in 8085.  SID-Serial Input Data  SOD-Serial Output Data Two more instructions are used to perform serial-parallel conversion needed for serial I/O devices.  SIM  RIM Address buffer and Address-Data buffer The contents of the stack pointer and program counter are loaded into the address buffer and address-data buffer. These buffers are then used to drive the external address bus and address-data bus. As the memory and I/O chips are connected to these buses, the CPU can exchange desired data to the memory and I/O chips. The address-data buffer is not only connected to the external data bus but also to the internal data bus which consists of 8-bits. The address data buffer can both send and receive data from internal data bus. 9  Dr. N. Karuppiah & Dr. S. Ravivarman Address bus and Data bus We know that 8085 is an 8-bit microprocessor. So, the data bus present in the microprocessor is also 8-bits wide. So, 8-bits of data can be transmitted from or to the microprocessor. But 8085 processor requires 16-bit address bus as the memory addresses are 16-bit wide. The 8 most significant bits of the address are transmitted with the help of address bus and the 8 least significant bits are transmitted with the help of multiplexed address/data bus. The eight- bit data bus is multiplexed with the eight least significant bits of address bus. The address/data bus is time multiplexed. This means for few microseconds, the 8 least significant bits of address are generated, while for next few seconds the same pin generates the data. This is called Time multiplexing. But there are situations where there is a need to transmit both data and address simultaneously. For this purpose, a signal called ALE (address latch enables) is used. ALE signal holds the obtained address in its latch for a long time until the data is obtained and so when the microprocessor sends the data next time the address is also available at the output latch. This technique is called Address/Data demultiplexing. 1.4 Pin Diagram of 8085 The signals can be grouped as follows 1. Power supply and clock signals 2. Address bus 3. Data bus 4. Control and status signals 5. Interrupts and externally initiated signals 6. Serial I/O ports 10  Microprocessor and Microcontroller Fig. 1.3 Pin diagram of 8085 Power supply and Clock frequency signals  Vcc + 5-volt power supply  Vss Ground  X1, X2: Crystal or R/C network or LC network connections to set the frequency of internal clock generator. The frequency is internally divided by two. Since the basic operating timing frequency is 3 MHz, a 6 MHz crystal is connected externally.  CLK (output) – Clock Output is used as the system clock for peripheral and devices interfaced with the microprocessor. Data Bus and Address Bus AD0-AD7:-These are multiplexed address and data bus. So, it can be used to carry the lower order 8-bit address as well as the data. Generally, these lines are demultiplexed using the Latch. During the opcode fetch operation, in the first clock cycle the lines deliver the lower order address bus A0-A7. In the subsequent IO/M read or write it is used as data bus D0-D7. CPU can read or write data through these lines. A8-A15:- These are address bus used to address the memory location. 11  Dr. N. Karuppiah & Dr. S. Ravivarman 1.5 Instruction Set The 8085 instruction set can be classified into the following five functional headings. Data Transfer Instructions: Includes the instructions that moves (copies) data between registers or between memory locations and registers. In all data transfer operations, the content of source register is not altered. Hence the data transfer is copying operation. Arithmetic Instructions: Includes the instructions, which performs the addition, subtraction, increment or decrement operations. The flag conditions are altered after execution of an instruction in this group. Logical Instructions: The instructions which performs the logical operations like AND, OR, EXCLUSIVE-OR, complement, compare and rotate instructions are grouped under this heading. The flag conditions are altered after execution of an instruction in this group. Branching Instructions: The instructions that are used to transfer the program control from one memory location to another memory location are grouped under this heading. Machine Control Instructions: Includes the instructions related to interrupts and the instruction used to halt program execution. 1.6 Data Transfer Instructions  These instructions move data between registers, or between memory and registers.  These instructions copy data from source to destination.  While copying, the contents of source are not modified. Opcode Operand Description MOV Rd, Rs Copy from source to destination. M, Rs Rd, M MVI Rd, Data Move immediate 8-bit M, Data LDA 16-bit address Load Accumulator LDAX B/D Register Pair Load accumulator indirect LXI Reg. pair, 16-bit data Load register pair immediate STA 16-bit address Store accumulator direct STAX Reg. pair Store accumulator indirect XCHG None Exchange H-L with D-E 12  Microprocessor and Microcontroller 1.7 Arithmetic Instructions These instructions perform arithmetic operations such as addition, subtraction, increment, and decrement. Opcode Operand Description R ADD Add register or memory to accumulator M R ADC Add register or memory to accumulator with carry M ADI 8-bit data Add immediate to accumulator ACI 8-bit data Add immediate to accumulator with carry R SUB Subtract register or memory from accumulator M SUI 8-bit data Subtract immediate from accumulator R INR Increment register or memory by 1 M INX R Increment register pair by 1 R DCR Decrement register or memory by 1 M DCX R Decrement register pair by 1 1.8 Logical Instructions These instructions perform various logical operations with the contents of the accumulator. Opcode Operand Description R CMP Compare register or memory with accumulator M R CMP Compare register or memory with accumulator M CPI 8-bit data Compare immediate with accumulator R ANA Logical AND register or memory with accumulator M ANI 8-bit data Logical AND immediate with accumulator R XRA Exclusive OR register or memory with accumulator M R ORA Logical OR register or memory with accumulator M ORI 8-bit data Logical OR immediate with accumulator R XRA Logical XOR register or memory with accumulator M XRI 8-bit data XOR immediate with accumulator 13  Dr. N. Karuppiah & Dr. S. Ravivarman 1.9 Branching Instructions This group of instructions alters the sequence of program execution either conditionally or unconditionally. Opcode Operand Description JMP 16-bit address Jump unconditionally Jx 16-bit address Jump conditionally 1.10 Machine Control Instructions These instructions control machine functions such as Halt, Interrupt, or do nothing. Opcode Operand Description HLT None Halt NOP None No operation The interrupt enable flip-flop is set and all interrupts are EI None enabled. No flags are affected. The interrupt enable flip-flop is reset and all the interrupts DI None except the TRAP are disabled. No flags are affected. This is a multipurpose instruction and used to implement the SIM None 8085 interrupts 7.5, 6.5, 5.5, and serial data output. This is a multipurpose instruction used to read the status of RIM None interrupts 7.5, 6.5, 5.5 and read serial data input bit. Fig. 1.4 SIM Instruction Fig. 1. 5 RIM Instruction 14  Microprocessor and Microcontroller 1.11 Addressing Modes Every instruction of a program has to operate on a data. The method of specifying the data to be operated by the instruction is called Addressing. The 8085 has the following 5 different types of addressing.  Immediate Addressing  Direct Addressing  Register Addressing  Register Indirect Addressing  Implied Addressing Immediate Addressing In immediate addressing mode, the data is specified in the instruction itself. The data will be a part of the program instruction. EX. MVI B, 3EH - Move the data 3EH given in the instruction to B register; LXI SP, 2700H. Direct Addressing In direct addressing mode, the address of the data is specified in the instruction. The data will be in memory. In this addressing mode, the program instructions and data can be stored in different memory. EX. LDA 1050H - Load the data available in memory location 1050H in to accumulator; SHLD 3000H Register Addressing In register addressing mode, the instruction specifies the name of the register in which the data is available. EX. MOV A, B - Move the content of B register to A register; SPHL; ADD C. Register Indirect Addressing In register indirect addressing mode, the instruction specifies the name of the register in which the address of the data is available. Here the data will be in memory and the address will be in the register pair. EX. MOV A, M - The memory data addressed by H L pair is moved to A register. LDAX B. Implied Addressing In implied addressing mode, the instruction itself specifies the data to be operated. EX. CMA - Complement the content of accumulator; RAL 15  Dr. N. Karuppiah & Dr. S. Ravivarman 1.12 Timing Diagrams Timing diagram is the display of initiation of read/write and transfer of data operations under the control of 3-status signals IO/M’, S1 and S0. Each machine cycle is composed of many clock cycles. Since, the data and instructions, both are stored in the memory, the µP performs fetch operation to read the instruction or data and then execute the instruction. The 3-status signals: IO / M’, S1 and S0 are generated at the beginning of each machine cycle. The unique combination of these 3-status signals identifies read or write operation and remain valid for the duration of the cycle. Thus, time taken by any µP to execute one instruction is calculated in terms of the clock period. The execution of instruction always requires read and writes operations to transfer data to or from the µP and memory or I/O devices. Each read/ write operation constitutes one machine cycle. Each machine cycle consists of many clock periods/ cycles, called T-states. Fig. 1.6 Machine cycle showing clock periods Each and every operation inside the microprocessor is under the control of the clock cycle. The clock signal determines the time taken by the microprocessor to execute any instruction. State is defined as the time interval between 2-trailing or leading edges of the clock. Machine cycle is the time required to transfer data to or from memory or I/O devices. The 8085 microprocessor has 5 basic machine cycles. They are  Opcode fetch cycle (4T)  Memory read cycle (3 T)  Memory write cycle (3 T)  I/O read cycle (3 T)  I/O write cycle (3 T) Processor Cycle The function of the microprocessor is divided into fetch and execute cycle of any instruction of a program. The program is nothing but number of instructions stored in the memory in sequence. In the normal process of 16  Microprocessor and Microcontroller operation, the microprocessor fetches (receives or reads) and executes one instruction at a time in the sequence until it executes the halt (HLT) instruction. Thus, an instruction cycle is defined as the time required to fetch and execute an instruction. For executing any program, basically 2-steps are followed sequentially with the help of clocks  Fetch, and  Execute. The time taken by the µP in performing the fetch and execute operations are called fetch and execute cycle. Thus, sum of the fetch and execute cycle is called the instruction cycle as indicated in Fig. Instruction Cycle (IC) = Fetch cycle (FC) + Execute Cycle (EC) Fig. 1.7 Processor cycle The 1st machine cycle of any instruction is always an Opcode fetch cycle in which the processor decides the nature of instruction. It is of at least 4-states. It may go up to 6-states. In the opcode fetch cycle, the processor comes to know the nature of the instruction to be executed. The processor during (M1 cycle) puts the program counter contents on the address bus and reads the opcode of the instruction through read process. The T1, T2, and T3 clock cycles are used for the basic memory read operation and the T4 clock and beyond are used for its interpretation of the opcode. Based on these interpretations, the µP comes to know the type of additional information/data needed for the execution of the instruction and accordingly proceeds further for 1 or 2-machine cycle of memory read and writes. Instruction Fetch (FC)⇒An instruction of 1 or 2 or 3-bytes is extracted from the memory locations during the fetch and stored in the µP’s instruction register. Instruction Execute (EC)⇒The instruction is decoded and translated into specific activities during the execution phase. Opcode Fetch The 1st step in communicating between the microprocessor and memory is reading from the memory. This reading process is called opcode fetch. The 17  Dr. N. Karuppiah & Dr. S. Ravivarman process of opcode fetch operation requires minimum 4-clock cycles T1, T2, T3, and T4and is the 1st machine cycle (M1) of every instruction. In order to differentiate between the data byte pertaining to an opcode or an address, the machine cycle takes help of the status signal IO/ M, S1, and S0. The IO/ M= 0 indicates memory operation and S1 = S0 = 1 indicates Opcode fetch operation. The opcode fetch machine cycle M1 consists of 4-states (T1, T2, T3, and T4). The 1st 3-states are used for fetching (transferring) the byte from the memory and the 4th-state is used to decode it. Example Fetch a byte 41H stored at memory location 2105H. For fetching a byte, the microprocessor must find out the memory location where it is stored. Then provide condition (control) for data flow from memory to the microprocessor. The process of data flow and timing diagram of fetch operation are shown in Figs. 5.3 (a), (b), and (c). The µP fetches opcode of the instruction from the memory as per the sequence below  A low IO/ M’ means microprocessor wants to communicate with memory.  The µP sends a high on status signal S1 and S0 indicating fetch operation.  The µP sends 16-bit address. AD bus has address in 1st clock of the 1st machine cycle, T1.  AD7to AD0 address is latched in the external latch when ALE = 1.  AD bus now can carry data.  In T2, the RD control signal becomes low to enable the memory for read operation.  The memory places opcode on the AD bus  The data is placed in the data register (DR) and then it is transferred to IR.  During T3the RDsignal becomes high and memory is disabled. 18  Microprocessor and Microcontroller Fig. 1.8 Opcode Fetch  During T4 the opcode is sent for decoding and decoded in T4.  The execution is also completed in T4if the instruction is single byte.  More machine cycles are essential for 2- or 3-byte instructions. The 1st machine cycleM1is meant for fetching the opcode. The machine cycles M2and M3are required either to read/ write data or address from the memory or I/O devices. Memory and I/O Read Cycle The memory read machine cycle is executed by the processor to read a data byte from memory. The processor takes 3T states to execute this cycle. The instructions which have more than one-byte word size will use the machine cycle after the opcode fetch machine cycle. 19  Dr. N. Karuppiah & Dr. S. Ravivarman Fig. 1.9 Memory Read Cycle Fig. 1.10 I/O Read Cycle The high order address (A15 ⇔A8) and low order address (AD7 ⇔AD0) are asserted on 1st low going transition of the clock pulse. The timing diagram for IO/M read are shown in Fig. The A15 ⇔A8 remains valid in T1, T2, and T3 i.e. duration of the bus cycle, but AD7⇔AD0 remains valid only in T1. Since it has to remain valid for the whole bus cycle, it must be saved for its use in the T2 and T3. ALE is asserted at the beginning of T1 of each bus cycle and is negated towards the end of T1. ALE is active during T1 only and is used as the clock pulse to latch the address (AD7⇔AD0) during T1. The RD’ is asserted near the beginning of T2. It ends at the end of T3. As soon as the RD’ becomes active, it forces the memory or I/O port to assert data. RD’ becomes inactive towards the end of T3, causing the port or memory to terminate the data. 20  Microprocessor and Microcontroller Memory and I/O Write Cycle Immediately after the termination of the low order address, at the beginning of the T2, data is asserted on the address/data bus by the processor. WR’ control is activated near the start of T2 and becomes inactive at the end of T3. The processor maintains valid data until after WR’ is terminated. This ensures that the memory or port has valid data while WR’ is active. It is clear from figures that for READ bus cycle, the data appears on the bus as a result of activating RD’ and for the WR’ bus cycle, the time the valid data is on the bus overlaps the time that the WR’ is active. Fig. 1.11 Memory Write Cycle Fig. 1.12 I/O Write Cycle 21  Dr. N. Karuppiah & Dr. S. Ravivarman Examples Opcode fetch MOV B, C. T1: The 1st clock of 1st machine cycle (M1) makes ALE high indicating address latch enabled which loads low-order address 00H on AD7⇔AD0 and high-order address 10H simultaneously on A15 ⇔A8. The address 00H is latched in T1. T2: During T2 clock, the microprocessor issues RD control signal to enable the memory and memory places 41H from 1000H location on the data bus. T3: During T3, the 41H is placed in the instruction register and RD= 1 (high) disables signal. It means the memory is disabled in T3 clock cycle. The opcode cycle is completed by end of T3 clock cycle. T4: The opcode is decoded in T4 clock and the action as per 41H is taken accordingly. In other word, the content of C-register is copied in B-register. Fig. 1.13 Opcode Fetch (MOV B, C) Timing diagram for STA 526AH  STA means Store Accumulator -The contents of the accumulator is stored in the specified address (526A).  The opcode of the STA instruction is said to be 32H. It is fetched from the memory 41FFH (see fig). - OF machine cycle  Then the lower order memory address is read (6A). - Memory Read Machine Cycle  Read the higher order memory address (52). -Memory Read Machine Cycle  The combination of both the addresses are considered and the content from accumulator is written in 526A. - Memory Write Machine Cycle 22  Microprocessor and Microcontroller  Assume the memory address for the instruction and let the content of accumulator is C7H. So, C7H from accumulator is now stored in 526A. Fig. 1.14 Timing Diagram for STA 526AH Timing diagram for IN C0H  Fetching the Opcode DBH from the memory 4125H.  Read the port address C0H from 4126H.  Read the content of port C0H and send it to the accumulator.  Let the content of port is 5EH. 23  Dr. N. Karuppiah & Dr. S. Ravivarman Fig. 1.15 Timing Diagram for IN C0H 1.13 Assembly Language Programming An assembly language is a low-level programming language for a computer, or other programmable device, in which there is a very strong (generally one- to-one) correspondence between the language and the architecture's machine code instructions. Each assembly language is specific to a particular computer architecture, in contrast to most high-level programming languages, which are generally portable across multiple architectures, but require interpreting or compiling. Assembly language is converted into executable machine code by a utility program referred to as an assembler; the conversion process is referred to as assembly, or assembling the code. Assembly language uses a mnemonic to represent each low-level machine operation or opcode. Some opcodes require one or more operands as part of the instruction, and most assemblers can take labels and symbols as operands to represent addresses and constants, instead of hard coding them into the program. 24  Microprocessor and Microcontroller What is an Assembler? An assembler is a software tool - a program -- designed to simplify the task of writing computer programs. If you have ever written a computer program directly in a machine-recognizable form such as binary or hexadecimal code, you will appreciate the advantages of programming in a symbolic assembly language. Assembly language operation codes (opcodes) are easily remembered (MOV for move instructions, JMP for jump). You can also symbolically express addresses and values referenced in the operand field of instructions. Since you assign these names, you can make them as meaningful as the mnemonics for the instructions. For example, if your program manipulates a date as data, you can assign it the symbolic name DATE. If your program contains a set of instructions used as a timing loop (a set of instructions executed repeatedly until a specific amount of time has passed), you can name the instruction group TIMER. What the Assembler Does To use the assembler, you first need a source program. The source program consists of programmer written assembly language instructions. These instructions are written using mnemonic opcodes and labels. Assembly language source programs must be in a machine-readable form when passed to the assembler. TheIntellec development system includes a text editor that will help you maintain source programs as paper tape files or diskette files. You can then pass the resulting source program file to the assembler. The assembler program performs the clerical task of translating symbolic code into object code which can be executed by the 8080 and 8085 microprocessors. Assembler output consists of three possible files: the object filecontaining your program translated into object code; the list file printout of your source code, the assemble generated object code, and the symbol table; and the symbol-crass- reference file, a listing of the symbol-cross reference records. 25  Dr. N. Karuppiah & Dr. S. Ravivarman Fig. 1.16 Function of an Assembler Example Programs 1. Statement: Store the data byte 32H into memory location 4000H. Program 1 MVI A, 32H : Store 32H in the accumulator STA 4000H : Copy accumulator contents at address 4000H HLT : Terminate program execution Program 2 LXI H : Load HL with 4000H MVI M : Store 32H in memory location pointed by HL register pair (4000H) HLT : Terminate program execution Statement: Exchange the contents of memory locations 2000H and 4000H Program 1 LDA 2000H : Get the contents of memory location 2000H into accumulator MOV B, A : Save the contents into B register LDA 4000H : Get the contents of memory location 4000H into accumulator STA 2000H : Store the contents of accumulator at address 2000H MOV A, B : Get the saved contents back into A register STA 4000H : Store the contents of accumulator at address 4000H Program 2 LXI H 2000H : Initialize HL register pair as a pointer to memory location 2000H. 26  Microprocessor and Microcontroller LXI D 4000H : Initialize DE register pair as a pointer to memory location 4000H. MOV B, M : Get the contents of memory location 2000H into B register. LDAX D : Get the contents of memory location 4000H into A register. MOV M, A : Store the contents of A register into memory location 2000H. MOV A, B : Copy the contents of B register into accumulator. STAX D : Store the contents of A register into memory location 4000H. HLT : Terminate program execution. Sample problem (4000H) = 14H (4001H) = 89H Result = 14H + 89H = 9DH Source program LXI H 4000H : HL points 4000H MOV A, M : Get first operand INX H : HL points 4001H ADD M : Add second operand INX H : HL points 4002H MOV M, A : Store result at 4002H HLT : Terminate program execution Statement: Subtract the contents of memory location 4001H from the memorylocation 2000H and place the result in memory location 4002H. Program - 4: Subtract two 8-bit numbers Sample problem (4000H) = 51H (4001H) = 19H Result = 51H - 19H = 38H Source program LXI H, 4000H : HL points 4000H 27  Dr. N. Karuppiah & Dr. S. Ravivarman MOV A, M : Get first operand INX H : HL points 4001H SUB M : Subtract second operand INX H : HL points 4002H MOV M, A : Store result at 4002H. HLT : Terminate program execution 1.14 Memory Interfacing The memory is made up of semiconductor material used to store the programs and data. Three types of memory are,  Process memory  Primary or main memory  Secondary memory Typical EPROM and Static RAM  A typical semiconductor memory IC will have ‘n’ address pins, ‘m’ data pins (or output pins).  Having two power supply pins (one for connecting required supply voltage (V and the other for connecting ground).  The control signals needed for static RAM are chip select (chip enable), read control (output enable) and write control (write enable).  The control signals needed for read operation in EPROM are chip select (chip enable) and read control (output enable). 28  Microprocessor and Microcontroller Decoder It is used to select the memory chip of processor during the execution of a program. No of IC's used for decoder is,  2-4 decoder (74LS139)  3-8 decoder (74LS138) Fig 1.17 Block diagram and Truth table of 2-4 decoder 29  Dr. N. Karuppiah & Dr. S. Ravivarman Fig 1.18 Block diagram and Truth table of 3-8 decoder Memory Interfacing The following are the steps involved in interfacing memory with 8085 processor. 1. First decide the size of memory requires to be interfaced. Depending on this we can say how many address lines are required for it. For example, if you want to interface 4KB (212) memory it requires 12 address lines. Remaining address lines can be used in address decoding. 2. Depending on the size of memory required and given address range, construct address decoding circuitry. This address decoding circuitry 30  Microprocessor and Microcontroller can be implemented with NAND gates and/or decoders or using PAL (when board size is a constraint). 3. Connect data bus of memory to processor data bus. 4. Generate the control signals required for memory using IO/M’, WR’, RD’ signals of 8085 processor. Address Decoding  The result of ‘address decoding’ is the identification of a register for a given address.  A large part of the address bus is usually connected directly to the address inputs of the memory chip.  This portion is decoded internally within the chip.  What concerns us is the other part that must be decoded externally to select the chip.  This can be done either using logic gates or a decoder. Example Interface 4KB memory to 8085 with starting address A000H. 1. 4KB memory requires 12 address lines for addressing as already mentioned. But 8085 has 16 address lines. Hence four of address lines are used for address decoding 2. Given that starting address for memory is A000H. So, for 4KB memory ending address becomes A000H+0FFFH (4KB) = AFFFH. A0-A11 address lines are directly connected to address bus of memory chip. A12-A15 are used for generating chip select signal for memory chip. 31  Dr. N. Karuppiah & Dr. S. Ravivarman Address decoding circuit using 3X8 decoder Fig. 1.19Address decoding circuit using 3X8 decoder A15 line is use for enabling 74x138 decoder chip. A12, A13, A14 lines are connected to 74X138 chip as inputs. When these lines are 010 output should be ‘0’. This is provided at O2 pin of 74X138 chip. Address decoding circuit using only NAND gates: Fig. 1.20Address decoding circuit using NAND gates A15, A14, A13, A12 inputs should be 1010, for enabling the chip. So, the circuit for this is as shown above. Types of address decoding There are two types of address decoding mechanism, based on address lines used for generating chip select signal. 1. Absolute decoding 2. Partial decoding 32  Microprocessor and Microcontroller Absolute decoding All the higher order lines of microprocessor, left after using the required signals for memory are completely used for generating chip select signal as shown in above example. This type of decoding is called absolute decoding. Partial decoding Only some of the address lines of microprocessor left after using the required signals for memory are used for generating chip select signal. Because of this multiple address ranges will be formed. If total memory space is not required for the system then, this type of address decoding can be used. The advantage of this technique is fewer components are required for memory interfacing because of this board size reduces and in turn cost reduces. Example Connect 512 bytes of memory to 8085 1. For interfacing 512 bytes 9 address lines are required. So A0-A8 can be used to directly connect to address bus of memory. 2. In the remaining A9-A15 for example only A15-A12 are used for generating chip select signal. A11-A9 are don’t care signals. Because of the don’t care signals the address range can be 0000 to 01FF 0200 to 03FF 0400 to 05FF 0600 to 07FF 0800 to 09FF 0A00 to 0BFF 0C00 to 0DFF 0E00 to 0FFF 33  Dr. N. Karuppiah & Dr. S. Ravivarman Address decoding circuit Fig. 1.21 Address decoding Example Consider a system in which 32kb memory space is implemented using four numbers of 8kb memory. Interface the EPROM and RAM with 8085 processor. The total memory capacity is 32Kb. So, let two number of 8kb n memory be EPROM and the remaining two numbers be RAM. Each 8kb memory requires 13 address lines and so the address lines A0- A12 of the processor are connected to 13 address pins of all the memory. The address lines and A13 - A14 can be decoded using a 2-to-4 decoder to generate four chips select signals. These four chips select signals can be used to select one of the four memory IC at any one time. The address line A15 is used as enable for decoder. The simplified schematic memory organization is shown. Fig.1.22 Interfacing 16KB EPROM and 16KB RAM with 8085 The address allotted to each memory IC is shown in following table. 34  Microprocessor and Microcontroller 1.15 Interfacing I/O Devices  Using I/O devices data can be transferred between the microprocessor and the outside world.  This can be done in groups of 8 bits using the entire data bus. This is called parallel I/O.  The other method is serial I/O where one bit is transferred at a time using the SID and SOD pins on the Microprocessor.  There are two ways to interface 8085 with I/O devices in parallel data transfer mode:  Memory Mapped IO  IO Mapped IO Memory mapped I/O I/O devices are interfaced using address from memory space. That means IO device address are part of addresses given to memory locations.8085 uses 16-bit address to memory interfacing. So, any address between 0000H-FFFFH can be given to each peripheral. But the addresses given to peripheral can’t be used for memory. Memory control signals are used as read and write control signals for peripherals. And all the operations that can be performed on 35  Dr. N. Karuppiah & Dr. S. Ravivarman memory can also be performed on peripherals. No need of using IO instructions such as IN, OUT. IO mapped I/O In this method separate address space is given to IO devices. Each IO device is given an 8-bit address. Hence maximum 256 devices can be interfaced to the processor. The address range for the IO devices is 00H-FFH. IO control signals are used to perform read, write operations. For reading data from IO device or writing data to IO device IN, OUT instructions needs to be used. Arithmetic and logical operations can’t be performed directly on IO devices as in memory mapped IO. IO devices can be interfaced, by using buffers for simple IO i.e. by using address decoding circuit to enable buffer. For handshake IO or to interface more peripherals ICs like 8255 peripheral programmable interface (PPI) can be used. IO mapped IO vs. Memory Mapped IO Memory Mapped IO IO mapped IO IO is treated as memory. IO is treated IO. 16-bit addressing. 8- bit addressing. More Decoder Hardware. Less Decoder Hardware. Can address 216=64k locations. Can address 28=256 locations. Less memory is available. Whole memory address space is available. Memory Instructions are used. Special Instructions are used like IN, OUT. Memory control signals are used. Special control signals are used. Arithmetic and logic operations can Arithmetic and logic operations be performed on data. cannot be performed on data. Data transfer b/w register and IO. Data transfer b/w accumulator and IO. The interfacing of output devices Output devices are usually slow.  Also, the output is usually expected to continue appearing on the output device for a long period of time.  Given that the data will only be present on the data lines for a very short period (microseconds), it has to be latched externally. 36  Microprocessor and Microcontroller  To do this the external latch should be enabled when the port’s address is present on the address bus, the IO/M signal is set high and WR is set low.  The resulting signal would be active when the output device is being accessed by the microprocessor.  Decoding the address bus (for memory-mapped devices) follows the same techniques discussed in interfacing memory. Interfacing of Input Devices  The basic concepts are similar to interfacing of output devices.  The address lines are decoded to generate a signal that is active when the particular port is being accessed.  An IORD signal is generated by combining the IO/M and the RD signals from the microprocessor.  A tri-state buffer is used to connect the input device to the data bus.  The control (Enable) for these buffers is connected to the result of combining the address signal and the signal IORD. 1.16 Applications of Microprocessor in General Life There are a lot of applications of Microprocessor in general life. Some of the applications are given below  Mobile Phones  Digital Watches  Washing Machine  Computer  Lighting Control  Traffic Control  LAPTOP  Modems  Power Stations  Television  CD Player  Multimeter  CRO  Wave generator  More applications in medical 37  Dr. N. Karuppiah & Dr. S. Ravivarman UNIT II – PERIPHERALS INTERFACING 2.1 Introduction Peripheral Interfacing is considered to be a main part of Microprocessor, as it is the only way to interact with the external world. The interfacing happens with the ports of the Microprocessor. The main IC's which are to be interfaced with 8085 are:  8255 PPI  8259 PIC  8251 USART  8279 Key board display controller  8253 Timer/ Counter  A/D and D/A converter interfacing. 2.2 Programmable Peripheral Interface 8255 The 8255 is a widely used, programmable, parallel I/O device. It can be programmed to transfer data under various conditions, from simple I/O to interrupt I/O. It is flexible, versatile and economical and complex. Features  Three 8-bit IO ports PA, PB, PC  PA can be set for Modes 0, 1, 2. PB for 0,1 and PC for mode 0 and for BSR. Modes 1 and 2 are interrupt driven.  PC has 2 4-bit parts: PC upper (PCU) and PC lower (PCL), each can be set independently for I or O. Each PC bit can be set/reset individually in BSR mode.  PA and PCU are Group A (GA) and PB and PCL are Group B (GB)  Address/data bus must be externally demultiplexed.  TTL compatible.  Improved dc driving capability. 38  Microprocessor and Microcontroller Pin diagram Fig. 2.1 8255 Pin Diagram Block Diagram Fig. 2.2 8255 Block Diagram Data Bus Buffer: This three-state bi-directional 8-bit buffer is used to interface the 8255 to the system data bus. Data is transmitted or received by 39  Dr. N. Karuppiah & Dr. S. Ravivarman the buffer upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer. Read/Write and Control Logic: The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups. (CS) Chip Select. A "low" on this input pin enables the communication between the 8255 and the CPU. (RD) Read: A "low" on this input pin enables 8255 to send the data or status information to the CPU on the data bus. In essence, it allows the CPU to "read from" the 8255. (WR) Write: A "low" on this input pin enables the CPU to write data or control words into the 8255. (A0 and A1) Port Select 0 and Port Select 1: These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word register. They are normally connected to the least significant bits of the address bus (A0 and A1). (RESET) Reset. A "high" on this input initializes the control register to 9Bh and all ports (A, B, C) are set to the input mode. A1 A0 Selection 0 0 Port A 0 1 Port B 1 0 Port C 1 1 Control Group A and Group B Controls The functional configuration of each port is programmed by the systems software. In essence, the CPU "outputs" a control word to the 8255. The control word contains information such as "mode", "bit set", "bit reset", etc., that initializes the functional configuration of the 8255. Each of the Control blocks (Group A and Group B) accepts "commands" from the Read/Write Control logic, receives "control words" from the internal data bus and issues the proper commands to its associated ports. Ports A, B, and C The 8255 contains three 8-bit ports (A, B, and C). All can be configured to a wide variety of functional characteristics by the system software but each has 40  Microprocessor and Microcontroller its own special features or "personality" to further enhance the power and flexibility of the 8255. Port A One 8-bit data output latch/buffer and one 8-bit data input latch. Both "pull-up" and "pull-down" bus-hold devices are present on Port A. Port B One 8-bit data input/output latch/buffer and one 8-bit data input buffer. Port C One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the control signal output and status signal inputs in conjunction with ports A and B. Operational modes of 8255 There are two basic operational modes of 8255:  Bit set/reset Mode (BSR Mode).  Input/output Mode (I/O Mode). The two modes are selected on the basis of the value present at the D7 bit of the Control Word Register. When D7 = 1, 8255 operates in I/O mode and when D7 = 0, it operates in the BSR mode. Bit set/reset (BSR) mode The Bit Set/Reset (BSR) mode is applicable to port C only. Each line of port C (PC0 - PC7) can be set/reset by suitably loading the control word register. BSR mode and I/O mode are independent and selection of BSR mode does not affect the operation of other ports in I/O mode. Fig. 2.3 control word BSR mode 41  Dr. N. Karuppiah & Dr. S. Ravivarman  D7 bit is always 0 for BSR mode.  Bits D6, D5 and D4 are don't care bits.  Bits D3, D2 and D1 are used to select the pin of Port C.  Bit D0 is used to set/reset the selected pin of Port C. Selection of port C pin is determined as follows B3 B2 B1 Bit/pin of port C selected 0 0 0 PC0 0 0 1 PC1 0 1 0 PC2 0 1 1 PC3 1 0 0 PC4 1 0 1 PC5 1 1 0 PC6 1 1 1 PC7 Input/Output mode This mode is selected when D7 bit of the Control Word Register is 1. There are three I/O modes:  Mode 0 - Simple I/O  Mode 1 - Strobed I/O  Mode 2 - Strobed Bi-directional I/O D0, D1, D3, D4 are assigned for lower port C, port B, upper port C and port A respectively. When these bits are 1, the corresponding port acts as an input port. For e.g., if D0 = D4 = 1, then lower port C and port A act as input ports. If these bits are 0, then the corresponding port acts as an output port. For e.g., if D1 = D3 = 0, then port B and upper port C act as output ports. D2 is used for mode selection of Group B (port B and lower port C). When D2 = 0, mode 0 is selected and when D2 = 1, mode 1 is selected. 42  Microprocessor and Microcontroller Fig. 2.4 Control word I/O mode D5 & D6 are used for mode selection of Group A (port A and upper port C). The selection is done as follows: D6 D5 Mode 0 0 0 0 1 1 1 X 2 As it is I/O mode, D7 = 1. Mode 0 - Simple I/O In this mode, the ports can be used for simple I/O operations without handshaking signals. Port A, port B provide simple I/O operation. The two halves of port C can be either used together as an additional 8-bit port, or they can be used as individual 4-bit ports. Since the two halves of port C are independent, they may be used such that one-half is initialized as an input port while the other half is initialized as an output port.  The input/output features in mode 0 are as follows:  Output ports are latched.  Input ports are buffered, not latched.  Ports do not have handshake or interrupt capability.  With 4 ports, 16 different combinations of I/O are possible. 43  Dr. N. Karuppiah & Dr. S. Ravivarman Mode 0 – input mode  In the input mode, the 8255 gets data from the external peripheral ports and the CPU reads the received data via its data bus.  The CPU first selects the 8255 chip by making CS’ low. It then selects the desired port using A0 and A1 lines.  The CPU then issues an RD’ signal to read the data from the external peripheral device via the system data bus. Mode 0 - Output mode  In the output mode, the CPU sends data to 8255 via system data bus and then the external peripheral ports receive this data via 8255 port.  CPU first selects the 8255 chip by making CS’ low. It then selects the desired port using A0 and A1 lines.  CPU then issues a WR’ signal to write data to the selected port via the system data bus. This data is then received by the external peripheral device connected to the selected port. Mode 1 When we wish to use port A or port B for handshake (strobed) input or output operation, we initialise that port in mode 1 (port A and port B can be initialised to operate in different modes, i.e., for e.g., port A can operate in mode 0 and port B in mode 1). Some of the pins of port C function as handshake lines. For port B in this mode (irrespective of whether is acting as an input port or output port), PC0, PC1 and PC2 pins function as handshake lines. If port A is initialised as mode 1 input port, then, PC3, PC4 and PC5 function as handshake signals. Pins PC6 and PC7 are available for use as input/output lines. The mode 1 which supports handshaking has following features:  Two ports i.e. port A and B can be used as 8-bit i/o ports.  Each port uses three lines of port c as handshake signal and remaining two signals can be used as i/o ports.  Interrupt logic is supported.  Input and Output data are latched. Input Handshaking signals 1. IBF(Input Buffer Full)-It is an output indicating that the input latch contains information. 44  Microprocessor and Microcontroller 2. STB(Strobed Input)-The strobe input loads data into the port latch, which holds the information until it is input to the microprocessor via the IN instruction. 3. INTR(Interrupt request)-It is an output that requests an interrupt. The INTR pin becomes a logic 1 when the STB input returns to a logic 1, and is cleared when the data are input from the port by the microprocessor. 4. INTE(Interrupt enable)-It is neither an input nor an output; it is an internal bit programmed via the port PC4(port A) or PC2(port B) bit position. Output Handshaking signals 1. OBF(Output Buffer Full)-It is an output that goes low whenever data are output(OUT) to the port A or port B latch. This signal is set to a logic 1 whenever the ACK pulse returns from the external device. 2. ACK(Acknowledge)-It causes the OBF pin to return to a logic 1 level. The ACK signal is a response from an external device, indicating that it has received the data from the 82C55 port. 3. INTR(Interrupt request)-It is a signal that often interrupts the microprocessor when the external device receives the data via the signal. this pin is qualified by the internal INTE(interrupt enable) bit. 4. INTE(Interrupt enable)-It is neither an input nor an output; it is an internal bit programmed to enable or disable the INTR pin. The INTE A bit is programmed using the PC6 bit and INTE B is programmed using the PC2 bit. PC bits in input mode: D7 D6 D5 D4 D3 D2 D1 D0 INTE-A / INTE-B / IBF- INTR- INTR- PC7 PC6 STB-A- STB-B- IBF-B A A B bar bar PC bits in output mode: D7 D6 D5 D4 D3 D2 D1 D0 INTE-A / INTE-B / OBF- INTR- OBF-B- INTR- ACK-A- PC5 PC4 ACK-B- A-bar A bar B bar bar 45  Dr. N. Karuppiah & Dr. S. Ravivarman Mode 2 Only group A can be initialised in this mode. Port A can be used for bidirectional handshake data transfer. This means that data can be input or output on the same eight lines (PA0 - PA7). Pins PC4 - PC7 are used as handshake lines for port A. The remaining pins of port C (PC0 - PC3) can be used as input/output lines if group B is initialised in mode 0 or as handshaking for port b if group B is initialised in mode 1. In this mode, the 8255 may be used to extend the system bus to a slave microprocessor or to transfer data bytes to and from a floppy disk controller. D7 D6 D5 D4 D3 D2 D1 D0 INTE1(O/P) / INTE2(I/P) / OBF-A-bar IBF-A INTR-A X X X ACK-A-BAR STB-A-bAR 2.3 Programmable Interval Timer - 8253 The 8253 solves one of most common problem in any microcomputer system, the generation of accurate time delays under software control. Instead of setting up timing loops in system software, the programmer configures the 8253 to match his requirements, initializes one of the counters of the 8253 with the desired quantity, then upon command the 8253 will count out the delay and interrupt the CPU when it has completed its tasks. It is easy to see that the software overhead is minimum and that multiple delays can be easily be maintained by assignment of priority levels. The 8253 includes three identical 16-bit counters that can operate independently. To operate a counter, a 16-bit count is loaded in its register and, on command, it begins to decrement the count until it reaches 0. At the end of the count, it generates a pulse that can be used to interrupt the CPU. The counter can count either in binary or BCD. In addition, a count can be read by the CPU while the counter is decrementing. Features 1. Three independent 16-bit down counters. 2. 8253 can operate from DC up to 2.6 MHz 3. Three counters are identical presettable, and can be programmed for either binary or BCD count. 4. Counter can be programmed in six different modes. 5. Compatible with all Intel and most other microprocessors. 46  Microprocessor and Microcontroller Pin Diagram Fig. 2.5 8254 Pin Diagram Block Diagram Fig. 2.6 8254 Block Diagram It includes three counters, a data bus buffer, Read/Write control logic, and a control register. Each counter has two input signals CLOCK and GATE and one output signal OUT. Data Bus Buffer: This tri-state, bi-directional, 8-bit buffer is used to interface the 8253 to the system data bus. The Data bus buffer has three basic functions. 1. Programming the modes of 8253. 2. Loading the count registers. 3. Reading the count values. 47  Dr. N. Karuppiah & Dr. S. Ravivarman Read/Write Logic: The Read/Write logic has five signals: RD, WR, CS and the address lines A0 and A1. In the peripheral I/O mode, the RD, and WR signals are connected to IOR and IOW, respectively. In memory-mapped I/O, these are connected to MEMR and MEMW. Address lines A0 and A1 of the CPU are usually connected to lines A0 and A1 of the 8253, and CS is tied to a decoded address. The control word register and counters are selected according to the signals on lines A0 and A1. It includes three counters, a data bus buffer, Read/Write control logic, and a control register. Each counter has two input signals CLOCK and GATE and one output signal OUT. Control Word Register: This register is accessed when lines A0 and A1 are at logic 1. It is used to write a command word which specifies the counter to be used (binary or BCD), its mode, and either a read or write operation. Counters: These three functional blocks are identical in operation. Each counter consists of a single, 16-bit, pre-settable, down counter. The counter can operate in either binary or BCD and its input, gate and output are configured by the selection of modes stored in the control word register. The counters are fully independent. The programmer can read the contents of any of the three counters without disturbing the actual count in process. Operation Description The complete functional definition of the 8253 is programmed by the system software. Once programmed, the 8253 is ready to perform whatever timing tasks it is assigned to accomplish. 48  Microprocessor and Microcontroller Mode 0: Interrupt on terminal count 1. The output will be initially low after the mode set operation. 2. After the count is loaded into the selected count Register the output will remain low and the counter will count. 3. When the terminal count is reached the output will go high and remain high until the selected count is reloaded. Mode 1: Hardware Retriggerable One-shot 1. The output will be initially high 2. The output will go low on the CLK pulse following the rising edge at the gate input. 3. The output will go high on the terminal count and remain high until the next rising edge at the gate input. Mode 2: Rate generator This mode functions like a divide by-N counter. 1. The output will be initially high. 2. The output will go low for one clock pulse before the terminal count. 3. The output then goes high, the counter reloads the initial count and the process is repeated. 4. The period from one output pulse to the next equals the number of input counts in the count register. 49  Dr. N. Karuppiah & Dr. S. Ravivarman Mode 3: Square wave mode 1. Initially output is high. 2. For even count, counter is decremented by 2 on the falling edge of each clock pulse. When the counter reaches terminal count, the state of the output is changed and the counter is reloaded with the full count and the whole process is repeated. 3. If the count is odd and the output is high the first clock pulse (after the count is loaded) decrements the count by 1. Subsequent clock pulses decrement the clock by 2. After timeout, the output goes low and the full count is reloaded. The first clock pulse decrements the count by 3 and subsequent clock pulse decrement the count by two. Then the whole process is repeated. In this way, if the count is odd, the output will be high for (n+1)/2 counts and low for (n-1)/2 counts. Mode 4: Software Triggered Strobe 1. The output will be initially high 2. The output will go low for one CLK pulse after the terminal count (TC). Mode 5: Hardware triggered strobe (Retriggerable) 1. The output will be initially high. 2. The counting is triggered by the rising edge of the Gate. 3. The output will go low for one CLK pulse after the terminal count (TC). Programming the 8253 Each counter of the 8253 is individually programmed by writing a control word into the control word register (A0 - A1 = 11). The above figure shows the control word format. Bits SC1 and SC0 select the counter, bits RW1 and RW0 select the read, write or latch command, bits M2, M1 and M0 select the mode of operation and bit BCD decides whether it is a BCD counter or binary counter. WRITE Operation 1. Write a control word into control register. 2. Load the low-order byte of a count in the counter register. 3. Load the high-order byte of count in the counter register. 50  Microprocessor and Microcontroller READ Operation In some applications, especially in event counters, it is necessary to read the value of the count in process. This can be done by following possible methods: Simple Read: It involves reading a count after inhibiting the counter by controlling the gate input or the clock input of the selected counter, and two I/O read operations are performed by the CPU. The first I/O operation reads the low-order byte, and the second I/O operation reads the high order byte. Counter Latch Command: In the second method, an appropriate control word is written into the control register to latch a count in the output latch, and two I/O read operations are performed by the CPU. The first I/O operation reads the low-order byte, and the second I/O operation reads the high order byte. 2.4 Programmable Interrupt Controller-8259 The Intel 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for the CPU. It is cascadable for up to 64 vectored priority interrupts without additional circuitry. It is packaged in a 28-pin DIP, uses NMOS technology and requires a single a 5V supply. Circuitry is static, requiring no clock input. The 8259A is designed to minimize the software and real time overhead in handling multi-level priority interrupts. It has several modes, permitting optimization for a variety of system requirements. The PIC receives an interrupt request from an I/O device and tells the microprocessor. The CPU completes whatever instruction it is currently executing and then fetches a new routine that will service the requesting device. Once this peripheral service is completed, the CPU resumes doing exactly what it was doing when the interrupt request occurred. The PIC functions as an overall manager of hardware interrupt requests in an interrupt driven system environment. Features  8 levels of interrupts.  Can be cascaded in master-slave configuration to handle 64 levels of interrupts.  Internal priority resolver, Fixed priority mode and rotating priority mode.  Individually maskable interrupts.  Modes and masks can be changed dynamically. 51  Dr. N. Karuppiah & Dr. S. Ravivarman  Accepts IRQ, determines priority, checks whether incoming priority > current level being serviced, issues interrupt signal.  In 8085 mode, provides 3-byte CALL instruction. In 8086 mode, provides 8-bit vector number.  Polled and vectored mode.  Starting address of ISR or vector number is programmable.  No clock required. Pin Diagram Fig. 2.7 8259 Pin Diagram Bi-directional, tristate, buffered data lines. Connected to data D0-D7 bus directly or through buffers RD-bar Active low read control WR-bar Active low write control A0 Address input line, used to select control register CS-bar Active low chip select Bi-directional, 3-bit cascade lines. In master mode, PIC places slave ID no. on these lines. In slave mode, the PIC reads slave ID CAS0-2 no. from master on these lines. It may be regarded as slave- select. SP-bar Slave program / enable. In non-buffered mode, it is SP-bar / EN- input, used to distinguish master/slave PIC. In buffered mode, it bar is output line used to enable buffers 52  Microprocessor and Microcontroller INT Interrupt line, connected to INTR of microprocessor INTA- Interrupt ack, received active low from microprocessor bar IR0-7 Asynchronous IRQ input lines, generated by peripherals. Block Diagram Interrupt Request Register (IRR): The interrupts at IRQ input lines are handled by Interrupt Request Register internally. IRR stores all the interrupt requests in it in order to serve them one by one on the priority basis. In-Service Register (ISR): This register stores all the interrupt requests those are being served, i.e. ISR keeps a track of the requests being served. Priority Resolver: This unit determines the priorities of the interrupt requests appearing simultaneously. The highest priority is selected and stored into the corresponding bit of ISR during INTA pulse. The IR0 has the highest priority while the IR7 has the lowest one, normally in fixed priority mode.The priorities however may be altered by programming the 8259A in rotating priority mode. Interrupt Mask Register (IMR): This register stores the bits required to mask the interrupt puts. IMR operates on IRR at the direction of the Priority Resolver. Fig. 2.8 8259 Block Diagram Interrupt Control Logic: This block manages the interrupt and interrupt acknowledge signals to be sent to the CPU for serving one of the eight interrupt 53  Dr. N. Karuppiah & Dr. S. Ravivarman requests. This also accepts interrupt acknowledge (INTA) signal from CPU that causes the 8259A to release vector address on to the data bus. Data Bus Buffer: This tristate bidirectional buffer interfaces internal 8259A bus to the microprocessor system data bus. Control words, status and vector information pass through buffer during read or write operations. Read write Control Logic: This circuit accepts and decodes commands from the CPU. This also allows the status of the 8259A to be transferred on to the data bus. Cascade Buffer/Comparator: This block stores and compares the ID's of all the 8259As used in the system. The three I/O pins CAS0-2 are outputs, when the 8259A is used as a master. The same pins act as inputs when the 8259A is in slave mode. The 8259A in master mode sends the ID of the interrupting slave device on these lines. The slave thus selected, will send its pre-programmed vector address on the data bus during the next INTA pulse. Interrupt Sequence The powerful features of the 8259A in a microcomputer system are its programmability and the interrupt routine addressing capability. The latter allows direct or indirect jumping to the specific interrupt routine requested without any polling of the interrupting devices. The normal sequence of events during an interrupt depends on the type of CPU being used. The events occur as follows in an 8085 system: 1. One or more of the INTERRUPT REQUEST lines (IR7–0) are raised high, setting the corresponding IRR bit(s). 2. The 8259A evaluates these requests, and sends an INT to the CPU, if appropriate. 3. The CPU acknowledges the INT and responds with an INTA pulse. 4. Upon receiving an INTA from the CPU group, the highest priority ISR bit is set, and the corresponding IRR bit is reset. The 8259A will also release a CALL instruction code (11001101) onto the 8-bit Data Bus through its D7–0 pins. 5. This CALL instruction will initiate two more INTA pulses to be sent to the 8259A from the CPU group. 6. These two INTA pulses allow the 8259A to release its preprogrammed subroutine address onto the Data Bus. The lower 8-bit address is released at the first INTA pulse and the higher 8-bit address is released at the second INTA pulse. 54  Microprocessor and Microcontroller 7. This completes the 3-byte CALL instruction released by the 8259A. In the AEOI mode the ISR bit is reset at the end of the third INTA pulse. 8. Otherwise, the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt sequence. When the 8259A PIC receives an interrupt, INT becomes active and an interrupt acknowledge cycle is started. If a higher priority interrupt occurs between the two INTA pulses, the INT line goes inactive immediately after the second INTA pulse. After an unspecified amount of time the INT line is activated again to signify the higher priority interrupt waiting for service. This inactive time is not specified and can vary between parts. Programming the 8259A The 8259A accepts two types of command words generated by the CPU: Initialization Command Words (ICWs) Before normal operation can begin, each 8259A in the system must be brought to a starting pointed by a sequence of 2 to 4 bytes timed by WR pulses. Operation Command Words (OCWs) These are the command words which command the 8259A to operate in various interrupt modes. These modes are: a. Fully nested mode b. Rotating priority mode c. Special mask mode d. Polled mode The OCWs can be written into the 8259A any time after initialization. Initialization Command Words (ICWS) Whenever a command is issued with A0 = 0 and D4 = 1, this is interpreted as Initialization Command Word 1 (ICW1). ICW1 starts the initialization sequence during which the following automatically occur. a. The edge sense circuit is reset, which means that following initialization, an interrupt request (IR) input must make a low-to- high transition to generate an interrupt. b. The Interrupt Mask Register is cleared. c. IR7 input is assigned priority 7. d. The slave mode address is set to 7. 55  Dr. N. Karuppiah & Dr. S. Ravivarman e. Special Mask Mode is cleared and Status Read is set to IRR. f. If IC4 e 0, then all functions selected in ICW4 are set to zero. ICW 1 This is the primary control word used to initialize the PIC. this is a 7-bit value that must be put in the primary PIC command register. This is the format: Initialization Control Word (ICW) 1 Bit Value Description 0 IC4 If set(1), the PIC expects to receive IC4 during initialization. If set(1), only one PIC in system. If cleared, PIC is cascaded with 1 SNGL slave PICs, and ICW3 must be sent to controller. If set (1), CALL address interval is 4, else 8. This is usually ignored 2 ADI by x86, and is default to 0 If set (1), Operate in Level Triggered Mode. If Not set (0), Operate in 3 LTIM Edge Triggered Mode 4 1 Initialization bit. Set 1 if PIC is to be initialized 5 0 MCS-80/85: Interrupt Vector Address. x86 Architecture: Must be 0 6 0 MCS-80/85: Interrupt Vector Address. x86 Architecture: Must be 0 7 0 MCS-80/85: Interrupt Vector Address. x86 Architecture: Must be 0 As you can see, there is a lot going on here. We have seen some of these before. This is not as hard as it seems, as most of these bits are not used on the x86 platform. To initialize the primary PIC, all we need to do is create the initial ICW and set the appropriate bits. ICW 2 This control word is used to map the base address of the IVT of which the PIC is to use. Initialization Control Word (ICW) 2 Bit Value Description 0-2 A8/A9/A10 Address bits A8-A10 for IVT when in MCS-80/85 mode. A11(T3)/A12(T4)/ Address bits A11-A15 for IVT when in MCS-80/85 mode. In 80x86 mode, spec 3-7 A13(T5)/A14(T6)/ the interrupt vector address. May be set to 0 in x86 mode. A15(T7) During initialization, we need to send ICW 2 to the PICs to tell them where the base address of the IRQ's to use. If an ICW1 was sent to the PICs (With the initialization bit set), you must send ICW2 next. Not doing so can result in undefined results. Most likely the incorrect interrupt handler will be executed. Unlike ICW 1, which is placed into the PIC's data registers, ICW 2 is sent to the 56  Microprocessor and Microcontroller data Registers, as software ports 0x21 for the primary PIC, and port 0xA1 for the secondary PIC. ICW 3 This is an important command word. It is used to let the PICs know what IRQ lines to use when communicating with each other. ICW 3 Command Word for Primary PIC Initialization Control Word (ICW) 3 - Primary PIC Bit Value Description 0-7 S0-S7 Specifies what Interrupt Request (IRQ) is connected to slave PIC ICW 3 Command Word for Secondary PIC Initialization Control Word (ICW) 3 - Secondary PIC Bit Value Description 0- IRQ number the master PIC uses to connect to (In binary ID0 2 notation) 3- 0 Reserved, must be 0 7 We must send an ICW 3 whenever we enable cascading within ICW 1. This allows us to set which IRQ to use to communicate with each other. Remember that the 8259A Microcontroller relies on the IR0-IR7 pins to connect to other PIC devices. With this, it uses the CAS0-CAS2 pins to communicate with each other. We need to let each PIC know about each other and how they are connected. We do this by sending the ICW 3 to both PICs containing which IRQ line to use for both the master and associated PICs. IRQ Lines for ICW 2 (Primary PIC) Binary IRQ Line 000 IR0 001 IR1 010 IR2 011 IR3 100 IR4 101 IR5 110 IR6 111 IR7 57  Dr. N. Karuppiah & Dr. S. Ravivarman IRQ Lines for ICW 2 (Secondary PIC) Binary IRQ Line 000 IR0 001 IR1 010 IR2 011 IR3 100 IR4 101 IR5 110 IR6 111 IR7 ICW 4 This is the final initialization control word. This controls how everything is to operate. Initialization Control Word (ICW) 4 Bit Value Description 0 uPM If set (1), it is in 80x86 mode. Cleared if MCS-80/86 mode If set, on the last interrupt acknowledge pulse, controller automatically 1 AEOI performs End of Interrupt (EOI) operation Only use if BUF is set. If set (1), selects buffer master. Cleared if buffer 2 M/S slave. 3 BUF If set, controller operates in buffered mode 4 SFNM Special Fully Nested Mode. Used in systems with cascaded controllers. 5-7 0 Reserved, must be 0 58  Microprocessor and Microcontroller Fig. 2.9 8259 Flow chart of command Words Operation Command Words (OCWs) After the Initialization Command Words (ICWs) are programmed into the 8259A, the chip is ready to accept interrupt requests at its input lines. However, during the 8259A operation, a selection of algorithms can command the 8259A to operate in various modes through the Operation Command Words (OCWs). OCW 1 OCW1 sets and clears the mask bits in the interrupt Mask Register (IMR). M7–M0 represent the eight mask bits. M = 1 indicates the channel is masked (inhibited), M = 0 indicates the channel is enabled. OCW 2 R, SL, EOI – These three bits control the Rotate and End of Interrupt modes and combinations of the two. A chart of these combinations can be found on the Operation Command Word Format. L2, L1, L0 – These bits determine the interrupt level acted upon when the SL bit is active. 59  Dr. N. Karuppiah & Dr. S. Ravivarman Operation Command Word (OCW) 2 Bit Value Description 0-2 L0/L1/L2 Interrupt level upon which the controller must react 3-4 0 Reserved, must be 0 5 EOI End of Interrupt (EOI) request 6 SL Selection 7 R Rotation option Bits 0-2 represents the interrupt level for the current interrupt. Bits 3-4 are reserved. Bits 5-7 are the interesting bits. Let’s take a look at each combination for these bits. OCW2 Commands R Bit SL Bit EOI Bit Description 0 0 0 Rotate in Automatic EOI mode (CLEAR) 0 0 1 Non-specific EOI command 0 1 0 No operation 0 1 1 Specific EOI command 1 0 0 Rotate in Automatic EOI mode (SET) 1 0 1 Rotate on non-specific EOI 1 1 0 Set priority command 1 1 1 Rotate on specific EOI OCW3 ESMM – Enable Special Mask Mode. When this bit is set to 1 it enables the SMM bit to set or reset the Special Mask Mode. When ESMM = 0 the SMM bit becomes a ‘‘don’t care’’. SMM – Special Mask Mode. If ESMM = 1 and SMM = 1 the 8259A will enter Special Mask Mode. If ESMM = 1 and SMM = 0 the 8259A will revert to normal mask mode. When ESMM = 0, SMM has no effect. D7 D6 D5 D4 D3 D2 D1 D0 D7 ESMM SMM 0 1 MODE RIR RIS ESMM SMM Effect 0 X No effect 1 0 Reset special mask 1 1 Set special mask 60  Microprocessor and Microcontroller 2.5 Keyboard and Display Controller (8279) 8279 is a general-purpose Keyboard Display controller that simultaneously drives the display of a system and interfaces a Keyboard with the CPU. The Keyboard Display interface scans the Keyboard to identify if any key has been pressed and sends the code of the pressed key to the CPU. It also transmits the data received from the CPU, to the display device. Both of these functions are performed by the controller in repetitive fashion without involving the CPU. The Keyboard is interfaced either in the interrupt or the polled mode. In the interrupt mode, the processor is requested service only if any key is pressed, otherwise the CPU can proceed with its main task. In the polled mode, the CPU periodically reads an internal flag of 8279 to check for a key pressure. Pin Diagram Fig. 2.10 8279 Pin Diagram DB0 - DB7:These are bidirectional data bus lines. The data an