Questions and Answers
What does the OBF signal indicate when it falls to a low level?
Which control signal must occur before the ACK signal?
What does the IBF signal indicate when it rises to logic '1'?
In which mode can Port B be set when Port A is in Mode 2?
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What must be activated before the RD signal?
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Which condition must be met for the INTR signal to go high?
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What is the primary function of the PIO 8255?
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What happens to the control signals during output operations in Mode 2?
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Which of the following control signals is associated with the input operations?
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What is the status of Port C used for?
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Study Notes
8086 Microprocessor
- In 32-bit multiply and divide instructions, the DX register contains the high-order word of the initial or resulting number.
Bus Interface Unit (BIU)
- The BIU sends out addresses, fetches instructions from memory, and reads data from ports and memory.
- The BIU handles all data and address transfers on the buses for the Execution Unit.
- The BIU contains:
- Instruction Queue
- Instruction Pointer
- Segment Registers
- Address Generator
Instruction Queue
- The BIU gets up to 6 bytes of the next instructions and stores them in the instruction queue.
- When the EU executes instructions and is ready for its next instruction, it reads the instruction from the instruction queue, resulting in increased execution speed.
- Fetching the next instruction while the current instruction executes is called pipelining (based on FIFO).
Segment Register
- The 8086 has 20-bit addresses, so it can address up to 1MB in memory.
- At any instant, it can address up to 4 64KB segments.
- The BIU always inserts zeros for the lowest 4 bits of the 20-bit starting address.
Addressing Modes of 8086
- Addressing modes are classified into two categories:
- Sequential Control Flow Instructions
- Control Transfer Instructions
- Addressing modes for sequential control flow instructions are:
- Immediate Addressing Mode
- Direct Addressing Mode
- Register Addressing Mode
- Register Indirect Addressing Mode
- Indexed Addressing Mode
- Register Relative Addressing Mode
- Based Indexed Addressing Mode
- Relative Based Indexed Addressing Mode
Immediate Addressing Mode
- The data operand is a part of the instruction itself.
- Example: MOV DL, 08H (the 8-bit data 08H given in the instruction is moved to DL)
Direct Addressing Mode
- The effective address of the memory location at which the data operand is stored is given in the instruction.
Parallel Transmission
- The simultaneous transmission of signal elements of a character or other entity of data.
- Multiple electrical wires are used, which can transmit multiple bits simultaneously, allowing for higher data transfer rates than serial transmission.
Interrupt Driven I/O
- A technique where the CPU automatically executes one of a collection of special routines whenever certain conditions exist within a program or processor system.
- Example: The CPU services devices such as keyboards, sensors, and other components when they request service.
Mode 1 of 8255
- Two groups, Group A and Group B, are available for strobed data transfer.
- Each group contains one 8-bit data I/O port and one 4-bit control/data port.
- The 8-bit data port can be used as either an input or output port.
- Inputs and outputs are latched.
- Out of 8-bit port C, PC0-PC2 are used to generate control signals for Port B, and PC3-PC5 are used to generate control signals for Port A.
Control Signals for Input Operations
- STB (Strobe Input): If this line falls to logic low level, the data available at the 8-bit input port is loaded into input latches.
- IBF (Input Buffer Full): If this signal rises to logic 1, it indicates that data has been loaded into latches.
- INTR (Interrupt Request): This active high output signal can be used to interrupt the CPU whenever an input device requests service.
Control Signals for Output Operations
- OBF (Output Buffer Full): This status signal, whenever it falls to low, indicates that the CPU has written data to the specified output port.
- ACK (Acknowledge): This control input, when it falls to logic low level, acknowledges that the previous data byte is received by the destination and the next byte may be sent by the processor.
Interfacing Analog to Digital Data Converters
- The PIO 8255 is used for interfacing analog to digital converters with a microprocessor.
- Interfacing techniques of analog to digital converters with 8255 are emphasized.
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Description
This quiz covers the microprocessor architecture, focusing on the DX register, BUS INTERFACE UNIT (BIU) and its components.
