Bsc. Computer Science and Engineering Microprocessors & Microcontrollers PDF

[Type text] University of Mines & Technology Computer Science & Engineering Department Bsc. Computer Science and Engineering Microprocessors & Microcontrollers 18 Unive...

[Type text] University of Mines & Technology Computer Science & Engineering Department Bsc. Computer Science and Engineering Microprocessors & Microcontrollers 18 University of Mines & Technology Computer Science & Engineering Department  Bsc. Computer Science and Engineering Microprocessors & Microcontrollers Course Outline................................................................................................... 4 Course Objectives.............................................................................................. 4 Course Presentation.......................................................................................... 4 References and Recommended Textbooks........................................................ 4 Course assessment............................................................................................ 5 Attendance........................................................................................................ 6 CHAPTER ONE.................................................................................................... 7 1 Overview of Microprocessor Systems and their basic structure................ 7 1.2 General Architecture of a Microcomputer System..................................................................... 7 1.3 Classification of Microprocessors and Microcontrollers.......................................................... 12 1.4 Types of Microprocessors /Microcontrollers............................................................................ 14 1.5 Microprocessor and Microcontroller Data sheet descriptions................................................. 15 CHAPTER TWO................................................................................................. 16 2 Intel 8085 Microprocessor Architecture and Its Operational Features.... 16 Chapter objectives and expected results.......................................................................................... 16 3.1 Intel 8085 Internal Architecture................................................................................................ 16 3.1.1 Functional Units of Intel 8085 Microprocessor...................................................................... 16 3.1.2 Pin Diagram of 8085 Microprocessor...................................................................................... 19 3.1.3 Intel 8085 Addressing modes................................................................................................... 21 3.1.4 Interrupts on 8085.............................................................................................................. 22 3.1.5 8085 Instruction Sets................................................................................................................. 24 3.1.6 Instruction Format.................................................................................................................... 41 CHAPTER THREE.............................................................................................. 44 3. Intel 8086 Microprocessor Architecture................................................... 44 Chapter objectives and expected results.......................................................................................... 44 3.1 Intel 8086 Microprocessor Architecture and Operational Functions....................................... 44 3.2 Features of Intel 8086................................................................................................................ 45 3.3 Architecture of Intel 8086.......................................................................................................... 46 3.4 Intel 8086 Pin Diagram and Functions....................................................................................... 54 Prepared by Mr. Thomas Kwantwi – Computer Science and Engineering Department (UMaT) – Tarkwa, Page 2  Bsc. Computer Science and Engineering Microprocessors & Microcontrollers 3.5 Intel 8086 Instruction Set........................................................................................................... 58 3. 6 Intel 8086 Interrupts................................................................................................................. 64 3.7 Intel 8086 Addressing Modes.................................................................................................... 67 3.8 Memory address space and data organization......................................................................... 69 CHAPTER FOUR................................................................................................ 74 4. Multiprocessor Architecture..................................................................... 74 4.1 Multiprocessor Configuration Overview................................................................................... 74 4.2 8087 Numeric Data Processor.................................................................................................... 77 4.2.1 8087 Architecture...................................................................................................................... 78 4.2.2 8087 Pin Description.................................................................................................................. 79 CHAPTER FIVE.................................................................................................. 82 5. Interfacing Input and Output devices to the Microprocessor.................. 82 5.1 Input and Output Interfaces...................................................................................................... 82 5.2 8279 - Programmable Keyboard................................................................................................ 84 5.2.1 8279 Pin Description.......................................................................................................... 86 5.2.2 Operational Modes of 8279...................................................................................................... 88 5.3 8257 DMA Controller................................................................................................................. 89 5.3.1 8257 Architecture...................................................................................................................... 90 Figure 5.4 Architecture of 8257........................................................................................................... 90 5.3.2 8257 Pin Description................................................................................................................... 91 Figure 5.5 Pin Diagram 8257 Controller.............................................................................................. 91 CHAPTER SIX.................................................................................................... 94 6. Microcontrollers........................................................................................ 94 Chapter objectives and expected results.......................................................................................... 94 6.1 Overview of Microcontrollers.................................................................................................... 94 6.2 Intel 8051 Architecture.............................................................................................................. 97 6.2.1 Intel 8051 Pin Description........................................................................................................ 97 6.2.2 Microcontrollers 8051 Input Output Ports............................................................................. 99 6.2.3 Microcontrollers - 8051 Interrupts........................................................................................ 101 END OF SECOND SEMESTER EXAMINATION................................................................................... 104 Prepared by Mr. Thomas Kwantwi – Computer Science and Engineering Department (UMaT) – Tarkwa, Page 3  Bsc. Computer Science and Engineering Microprocessors & Microcontrollers END OF SECOND SEMESTER EXAMINATION................................................................................... 112 Course Outline Microprocessor and Microcontroller Systems is an undergraduate Computer Science and Engineering course. The course is design to look at: o The introduction and evolution of some Microprocessors and Microcontrollers; o Overview Intel 8080/8085 and Intel 8086/8088 hardware and instruction sets; o Overview of the 8051 and AVR hardware and instruction sets; o Assembly Language Programming. Course Objectives At the end of this course students are expected to: o Be able to differentiate between microprocessors and microcontrollers with examples; o Be able to describe the architecture and organization of specific microprocessors /microcontrollers and its instruction set; o Be able to write structured, well-commented, understandable programs in assembly language that can run on specific microprocessors / microcontrollers; o Understand techniques for interfacing I/O devices to the microprocessor /microcontroller, including several specific standard I/O devices. Course Presentation The course is presented through lectures supported with handouts and tutorials. The tutorial will be in the form of problem solving and discussions and will constitute an integral part of each lecture. The student can best understand and appreciate the subject by attending all lectures and laboratory work, by practicing, reading references and handouts and by completing all assignments and course work on schedule. References and Recommended Textbooks a. Muhammad Mazidi and Janice Mazidi, Prentice Hall, 4th Edition, 2003. The 80x86 IBM PC and Compatible Computers (Volume I and II): Assembly Language, Design and Interfacing Prepared by Mr. Thomas Kwantwi – Computer Science and Engineering Department (UMaT) – Tarkwa, Page 4  Bsc. Computer Science and Engineering Microprocessors & Microcontrollers b. Walter A. Triebel and Avtar Singh, Prentice Hall, 4th Edition, 2003. The 8088 and 8086 Microprocessors: Programming, Interfacing, Software, Hardware and Applications c. Kip R. Irvine, Prentice Hall, 4th Edition, 2003, Assembly Language for Intel-Based Computers d. John Crisp, 2nd Edition, Introduction to Microprocessors and microcontrollers e. http://www.emu8086.com f. www.cs.sfu.ca g. www.wikipedia.com h. www.microsoft.com i. www.cs.ucf.edu Course assessment Factor Weight Location Date Time Exercises 10 % In class Grading Course 5% Assignment 4 Weeks System Work Attendance 10 % In class Random Quizzes 15 % DTBA Date to be Announced 2 Hrs Final Exam 60 % (TBA) To Be Announced 3 Hrs (TBA) Prepared by Mr. Thomas Kwantwi – Computer Science and Engineering Department (UMaT) – Tarkwa, Page 5 Attendance UMaT rules and regulations say that, attendance is MANDANTORY for every student. A total of FIVE (5) attendances shall be taken at random to the 10%. The only acceptable excuse for absence is the one authorized by the Dean of Student on their prescribed form. However, a student can also ask permission from me to be absent from a particular class with a tangible reason. A student who misses all the five random attendances marked WOULD not be allowed to take the final exams Office Hours I will be available in my office every Tuesday to answering students’ questions and provide guidance on any issues related to the course. Please Note the Following:  Students must feel free to ask questions in class. Students should not hesitate to email me with any questions whatsoever.  Students must endeavour to attend all lectures, lab works and do all their assignments and coursework.  Students must be seated and fully prepared for lectures at least 5 minutes before scheduled time.  Under no circumstance a student should be late more than 15 minutes after scheduled time  NO student shall be admitted into the lecture room more than 15 minutes after the start of lectures unless pre-approved by me.  All cell phones, IPods, MP3/MP4s, PDAs etc MUST remain switched off throughout the lecture period.  There shall be no eating or gum chewing in class  Plagiarism shall NOT be accepted in this course so be sure to do your referencing properly Thank You 6 CHAPTER ONE 1 Overview of Microprocessor Systems and their basic structure Chapter One Objectives and expected results Chapter objectives are: ▪ Overview of the Microprocessors; ▪ Examples of microprocessors and hardware and their applications; ▪ Understanding and discussion of the microprocessor basic structure and design. At the end of the chapter, students are expected to: o Understand what the microprocessor looks like; o Describe the basic functions of the microprocessor; o Know the various examples of microprocessor trends on the market; o List and describe the functions of the various components of the microprocessor. 1.2 General Architecture of a Microcomputer System The hardware of a microcomputer system can be divided into four functional sections: the Input device; Microprocessing device; Memory Unit; and Output device. Figure 1.1 Block Diagram of a Basic Microcomputer At the heart of every microcomputer is processing unit called a microprocessor or a microcontroller. 7 Microprocessor is a controlling unit of a micro-computer, fabricated on a small chip capable of performing ALU (Arithmetic Logical Unit) operations and communicating with the other devices connected to it. Microprocessor consists of an ALU, register array, and a control unit. ALU performs arithmetical and logical operations on the data received from the memory or an input device. The microprocessor follows a sequence: Fetch, Decode, and then Execute. Initially, the instructions are stored in the memory in a sequential order. The microprocessor fetches those instructions from the memory, then decodes it and executes those instructions till STOP instruction is reached. Later, it sends the result in binary to the output port. Between these processes, the register stores the temporarily data and ALU performs the computing functions. Typically, a microprocessor does not have any RAM, ROM, and I/O on the CPU chip itself. A typical computer is built around this CPU having the architecture below in figure 1.2. Figure 1.2 General-purpose microprocessor systems A microcontroller on the order hand (sometimes abbreviated µC, uC or MCU) is a small computer on a single integrated circuit containing a processor core, memory, and programmable input/output peripherals. Basically, a micro-controller is a device which integrates a number of the components of a microprocessor system onto a single microchip. A micro-controller combines onto the same microchip: The CPU core; Memory (both RAM & ROM); Some peripheral digital I/O and more. 8 Some characteristic of microcontrollers are as follows: 1. Microcontrollers are "embedded" inside some other device (often a consumer product) so that they can control the features or actions of the product. Another name for a microcontroller, therefore, is "embedded controller." 2. Microcontrollers are dedicated to one task and run one specific program. The program is stored in ROM (read-only memory) and generally does not change. 3. Microcontrollers are often low-power devices. A desktop computer is almost always plugged into a wall socket and might consume 50 watts of electricity. A battery-operated microcontroller might consume 50 milli-watts. 4. A microcontroller has a dedicated input device and often (but not always) has a small LED or LCD display for output. A microcontroller also takes input from the device it is controlling and controls the device by sending signals to different components in the device. For example, the microcontroller inside a TV takes input from the remote control and displays output on the TV screen. The controller controls the channel selector, the speaker system and certain adjustments on the picture tube electronics such as tint and brightness. The engine controller in a car takes input from sensors such as the oxygen and knock sensors and controls things like fuel mix and spark plug timing. A microwave oven controller takes input from a keypad, displays output on an LCD display and controls a relay that turns the microwave generator on and off. 5. A microcontroller is often small and low cost. The components are chosen to minimize size and to be as inexpensive as possible. 6. A microcontroller is often, but not always, ruggedized in some way. The microcontroller controlling a car's engine, for example, has to work in temperature extremes that a normal computer generally cannot handle. 9 Figure 1.3 illustrates the basic diagram of micro-controller. Figure 1.3 basic diagram of a microcontroller. From the figure 1.3, we have got the CPU, Memory (RAM & ROM) and I/O devices all connected via a bus system. All these things are integrated onto the same silicon real estate so they are of the same chip itself. Apart from the CPU, Memory and I/O devices mention above there are other components of microcontrollers as well and these are: Timer module: A timer module allows the micro-controller to perform tasks for certain time periods. A timer in a typical general-purpose computer is programmed to work for a certain time period with respect to the system clock and after that typically a timer can generate an interrupt to the processor so that there can be switching from one task to another. Serial I/O ports: The serial I/O ports allow data flow between the micro-controller and devices which support serial interfaces. Analog to Digital Controllers (ADC): The Analog to Digital Controllers allow the micro-controller to convert external input which may come in Analog form to the Digital form for subsequent processing by the microcontroller. Digital to Analog Controllers (DAC): This converts the digital signal from the micro- controller to Analog form to the external world. 10 Figure 1.4 shows a detailed block diagram of a microcontrollers. Figure 1.4 detailed block diagram of a microcontroller. A microprocessor and a microcontroller are both essentially processors that are designed to run computers. The type of the computer machinery that the two run is different, though essentially the main task of both the microprocessor and the microcontroller is the same. Both are generally termed as the core of any machinery that has a computerized form. One is a specialized form of processor whereas the other is found in all computers. The major differences between a microprocessor and a microcontroller are as follows: Microprocessor Micro-controller 1. CPU on a microprocessor is a stand- 1. CPU, RAM, ROM, I/O and Timer are alone, with RAM, ROM, I/O and timer all on a single chip. been separate. 2. Designer can decide on the amount of 2. Has fix amount of on chip ROM, RAM ROM, RAM and I/O ports and I/O ports 3. Very expensive 3. Low cost, small packaging 4. A microprocessor has more 4. A microcontroller is more specific to generalized functions its task. 5. A microprocessor may not also be 5. Micro-controllers can be programmed to handle real-time tasks programmed and reprogrammed 6. Limited I/O capabilities 6. Lots of I/O capabilities 7. Used for general-purpose computers 7. Use for applications in which cost, power and space are critical 8. High power consumption 8. Low power consumption 11 Input and Output units are the means by which the MPU communicates with the outside world. Input unit: keyboard, mouse, scanner, etc. Output unit: monitor, printer, etc. Memory unit: o Primary: is normally smaller in size and is used for temporary storage of active information. Typically, ROM and RAM. o Secondary: is normally larger in size and used for long-term storage of information. Like Hard disk, Floppy, CD, etc. 1.3 Classification of Microprocessors and Microcontrollers The microprocessor and microcontrollers are characterized regarding bus-width, instruction set, and memory structure. For the same family, there may be different forms with different sources. Over time, five standard bus widths have evolved: 4-bit, 8-bit, 16- bit, 32-bit, 64-bit. Classification According to Number of Bits The bits in microprocessor and microcontroller are 8-bits, 16-bits and 32-bits microcontroller. In an 8-bit microprocessor or microcontroller, the point when the internal bus is 8-bit then the ALU is performs the arithmetic and logic operations. The 16-bit microprocessor and microcontroller perform greater precision and performance as compared to 8-bit. For example, 8-bit microcontrollers can only use 8 bits, resulting in a final range of 0×00 – 0xFF (0-255) for every cycle. In contrast, 16-bit microcontrollers with its 16- bit data width has a range of 0×0000 – 0xFFFF (0-65535) for every cycle. A longer timer most extreme worth can likely prove to be useful in certain applications and circuits. It can automatically operate on two 16-bit numbers. The 32-bit microprocessor and microcontroller use the 32-bit instructions to perform the arithmetic and logic operations. These are used in automatically controlled devices including implantable medical devices, engine control systems, office machines, appliances and other types of embedded systems. 12 Classification According to Memory Devices The memory devices are divided into two types, they are: Embedded memory; External memory. Embedded memory microcontroller: When an embedded system has a microcontroller unit that has all the functional blocks available on a chip is called an embedded microcontroller. For example, 8051 having program & data memory, I/O ports, serial communication, counters and timers and interrupts on the chip is an embedded microcontroller. External Memory Microcontroller: When an embedded system has a microcontroller unit that has not all the functional blocks available on a chip is called an external memory microcontroller. For example, 8031 has no program memory on the chip is an external memory microcontroller. Classification According to Instruction Set CISC: CISC is a Complex Instruction Set Computer. It allows the programmer to use one instruction in place of many simpler instructions. RISC: The RISC is stands for Reduced Instruction set Computer, this type of instruction sets reduces the design of microprocessor for industry standards. It allows each instruction to operate on any register or use any addressing mode and simultaneous access of program and data. Classification According to Memory Architecture Memory architecture of microcontroller are two types, they are namely: Harvard memory architecture microcontroller; Princeton memory architecture microcontroller. Harvard Memory Architecture Microcontroller: The point when a microprocessor or microcontroller unit has a dissimilar memory address space for the program and data memory, the microprocessor or microcontroller has Harvard memory architecture in the processor. 13 Princeton Memory Architecture Microcontroller: The point when a microprocessor or microcontroller has a common memory address for the program memory and data memory, the microcontroller has Princeton memory architecture in the processor. 1.4 Types of Microprocessors /Microcontrollers There are so many manufacturers of Microprocessors, but only two companies have been produces popular microprocessors: Intel and Motorola. Table 1.1 lists some of types that belong to these companies (families) of microprocessors. Table 1.1 Types of microprocessors 14 Note that the 8086 has data bus width of 16-bit, and it is able to address 1Megabyte of memory. It is important to note that 80286, 80386, 80486, and Pentium-Pentium4 microprocessors are upward compatible with the 8086 Architecture. This mean that 8086/8088 code will run on the 80286, 80386, 80486, and Pentium Processors, but the reverse in not true if any of the new instructions are in use. Beside these general-purpose microprocessors, there are special-purpose microprocessors that are used in embedded control applications. This type of embedded microprocessors is called microcontroller. The 8080, 8051, 8048, 80186, 80C186XL, AVR, PIC are some examples of microcontrollers. 1.5 Microprocessor and Microcontroller Data sheet descriptions A typical data sheet of a microprocessor or microcontroller is a literature containing information on IC packaging, pin diagram, and the function of each IC pin. The architecture of the CPU is diagrammed, along with a description of the major features. Timing diagrams appear in the literature along with the processor’s instruction set. The data sheet also diagrams typical systems using the microprocessor or microcontroller. The microprocessor is typically housed in a 40-pin dual-in-line package integrated circuit (40-pin DIP IC). Examples of such packages are illustrated below in figure 1.5. Figure 1.5a plastic 40-pin DIP microprocessor Figure 1.5b Ceramic 40-pin DIP microprocessor A pin diagram, such as the one shown in figure 1.6, is included on microprocessor data sheets. The manufacturer then details the name and use of each pin on the microprocessor. 15 CHAPTER TWO 2 Intel 8085 Microprocessor Architecture and Its Operational Features Chapter objectives and expected results The objectives of this chapter are: o To introduce the Intel 8085 microprocessor; o To learn about the internal organization and operations of the Intel 8085 microprocessor; o To know the instruction set and program on the Intel 8085 microprocessor. At the end of the chapter, students are expected to: o Understand the operations of the Intel 8085 microprocessor; o Know the internal organization of the 8085 processor; o Know how to programme the Intel 8085 microprocessor. 3.1 Intel 8085 Internal Architecture The Intel 8085 microprocessor is an 8-bit microprocessor designed by Intel in 1977 using NMOS technology. It has the following configurations: 1. 8-bit data bus; 2. 16-bit address bus, which can address up to 64KB; 3. A 16-bit program counter; 4. A 16-bit stack pointer; 5. Six 8-bit registers arranged in pairs: BC, DE, HL; 6. Requires +5V supply to operate at 3.2 MHZ single phase clock. It is used in washing machines, microwave ovens, mobile phones, etc. 3.1.1 Functional Units of Intel 8085 Microprocessor The Intel 8085 microprocessor consists of the following functional units: Accumulator: It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE operations. It is connected to internal data bus & ALU. 16 Arithmetic and Logic Unit (ALU): As the name suggests, it performs arithmetic and logical operations like Addition, Subtraction, AND, OR, etc. on 8-bit data. General Purpose Register: There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each register can hold 8-bit data. These registers can work in pair to hold 16-bit data and their pairing combination is like B-C, D-E & H-L. Program Counter (PC): It is a 16-bit register used to store the memory address location of the next instruction to be executed. Microprocessor increments the program whenever an instruction is being executed, so that the program counter points to the memory address of the next instruction that is going to be executed. Stack Pointer: It is also a 16-bit register works like stack, which is always incremented/decremented by 2 during push & pop operations. Temporary Register: It is an 8-bit register, which holds the temporary data of arithmetic and logical operations. Flag Register or Status Register: It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending upon the result stored in the accumulator. These are the set of 5 flip-flops: 1. Sign (S) 2. Zero (Z) 3. Auxiliary Carry (AC) 4. Parity (P) 5. Carry (C) Its bit position is shown in the following table 1.1 Table 1.1 Flag bit positions Instruction register and decoder: It is an 8-bit register. When an instruction is fetched from memory then it is stored in the Instruction register. Instruction decoder decodes the information present in the Instruction register. 17 Timing and control unit: It provides timing and control signal to the microprocessor to perform operations. Following are the timing and control signals, which control external and internal circuits − 1. Control Signals: READY, RD’, WR’, ALE 2. Status Signals: S0, S1, IO/M’ 3. DMA Signals: HOLD, HLDA 4. RESET Signals: RESET IN, RESET OUT Interrupt control: As the name suggests it controls the interrupts during a process. When a microprocessor is executing a main program and whenever an interrupt occurs, the microprocessor shifts the control from the main program to process the incoming request. After the request is completed, the control goes back to the main program. There are 5 interrupt signals in 8085 microprocessors: INTR, RST 7.5, RST 6.5, RST 5.5, TRAP. Serial Input/output control: It controls the serial data communication by using these two instructions: SID (Serial input data) and SOD (Serial output data). Address buffer and address-data buffer: The content stored in the stack pointer and program counter is loaded into the address buffer and address-data buffer to communicate with the CPU. The memory and I/O chips are connected to these buses; the CPU can exchange the desired data with the memory and I/O chips. Address bus and Data bus: Data bus carries the data to be stored. It is bidirectional, whereas address bus carries the location to where it should be stored and it is unidirectional. It is used to transfer the data & Address I/O devices. 18 The architecture of 8085 is depicted in figure 2.1: Figure 2.1 8085 Architecture 3.1.2 Pin Diagram of 8085 Microprocessor The following image depicts the pin diagram of 8085 Microprocessor. Figure: Pin Diagram 8085 Architecture 19 The pins of an 8085 microprocessor can be classified into seven groups and they are as follows: Address bus: A15-A8, it carries the most significant 8-bits of memory/IO address. Data bus: AD7-AD0, it carries the least significant 8-bit address and data bus. Control and status signals: These signals are used to identify the nature of operation. There are 3 control signal and 3 status signals. Three control signals are RD, WR & ALE. 1. RD − This signal indicates that the selected IO or memory device is to be read and is ready for accepting data available on the data bus. 2. WR − This signal indicates that the data on the data bus is to be written into a selected memory or IO location. 3. ALE − It is a positive going pulse generated when a new operation is started by the microprocessor. When the pulse goes high, it indicates address. When the pulse goes down it indicates data. Three status signals are IO/M, S0 & S1. IO/M: This signal is used to differentiate between IO and Memory operations, i.e. when it is high indicates IO operation and when it is low then it indicates memory operation. S1 & S0: These signals are used to identify the type of current operation. Power supply: There are 2 power supply signals − VCC & VSS. VCC indicates +5v power supply and VSS indicates ground signal. Clock signals: There are 3 clock signals, i.e. X1, X2, CLK OUT. X1, X2 − A crystal (RC, LC N/W) is connected at these two pins and is used to set frequency of the internal clock generator. This frequency is internally divided by 2. CLK OUT − This signal is used as the system clock for devices connected with the microprocessor. Interrupts & externally initiated signals: Interrupts are the signals generated by external devices to request the microprocessor to perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. 20  INTA − It is an interrupt acknowledgment signal. RESET IN − This signal is used to reset the microprocessor by setting the program counter to zero. RESET OUT − This signal is used to reset all the connected devices when the microprocessor is reset. READY − This signal indicates that the device is ready to send or receive data. If READY is low, then the CPU has to wait for READY to go high. HOLD − This signal indicates that another master is requesting the use of the address and data buses. HLDA (HOLD Acknowledge) − It indicates that the CPU has received the HOLD request and it will relinquish the bus in the next clock cycle. HLDA is set to low after the HOLD signal is removed. 3.1.3 Intel 8085 Addressing modes Addressing modes are the manner of specifying effective address. These are the instructions used to transfer the data from one register to another register, from the memory to the register, and from the register to the memory without any alteration in the content. Addressing modes in 8085 is classified into 5 groups: 1. Immediate addressing mode: In this mode, the 8/16-bit data is specified in the instruction itself as one of its operands. For example: MVI K, 20F: means 20F is copied into register K. 2. Register addressing mode: In this mode, the data is copied from one register to another. For example: MOV K, B: means data in register B is copied to register K. 3. Direct addressing mode: In this mode, the data is directly copied from the given address to the register. For example: LDB 5000K: means the data at address 5000K is copied to register B. 4. Indirect addressing mode: In this mode, the data is transferred from one register to another by using the address pointed by the register. For example: MOV K, B: means data is transferred from the memory address pointed by the register to the register K. 5. Implied addressing mode: This mode doesn’t require any operand; the data is specified by the opcode itself. For example: CMP. 21 3.1.4 Interrupts on 8085 Interrupts are the signals generated by the external devices to request the microprocessor to perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. Interrupt are classified into following groups based on their parameter: Vector interrupt − In this type of interrupt, the interrupt address is known to the processor. For example: RST7.5, RST6.5, RST5.5, TRAP. Non-Vector interrupt − In this type of interrupt, the interrupt address is not known to the processor so, the interrupt address needs to be sent externally by the device to perform interrupts. For example: INTR. Maskable interrupt − In this type of interrupt, we can disable the interrupt by writing some instructions into the program. For example: RST7.5, RST6.5, RST5.5. Non-Maskable interrupt − In this type of interrupt, we cannot disable the interrupt by writing some instructions into the program. For example: TRAP. Software interrupt − In this type of interrupt, the programmer has to add the instructions into the program to execute the interrupt. There are 8 software interrupts in 8085, i.e. RST0, RST1, RST2, RST3, RST4, RST5, RST6, and RST7. Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware interrupts, i.e. TRAP, RST7.5, RST6.5, RST5.5, INTA. Note − NTA is not an interrupt, it is used by the microprocessor for sending acknowledgement. TRAP has the highest priority, then RST7.5 and so on. Interrupt Service Routine (ISR): A small program or a routine that when executed, services the corresponding interrupting source is called an ISR. TRAP: It is a non-maskable interrupt, having the highest priority among all interrupts. By default, it is enabled until it gets acknowledged. In case of failure, it executes as ISR and sends the data to backup memory. This interrupt transfers the control to the location 0024H. RST7.5: It is a maskable interrupt, having the second highest priority among all interrupts. When this interrupt is executed, the processor saves the content of the PC register into the stack and branches to 003CH address. 22  RST 6.5: It is a maskable interrupt, having the third highest priority among all interrupts. When this interrupt is executed, the processor saves the content of the PC register into the stack and branches to 0034H address. RST 5.5: It is a maskable interrupt. When this interrupt is executed, the processor saves the content of the PC register into the stack and branches to 002CH address. INTR: It is a maskable interrupt, having the lowest priority among all interrupts. It can be disabled by resetting the microprocessor. When INTR signal goes high, the following events can occur: 1. The microprocessor checks the status of INTR signal during the execution of each instruction. 2. When the INTR signal is high, then the microprocessor completes its current instruction and sends active low interrupt acknowledge signal. 3. When instructions are received, then the microprocessor saves the address of the next instruction on stack and executes the received instruction. The Intel 8085 Non-Vectored Interrupt Process: 1. The interrupt process should be enabled using the EI instruction. 2. The 8085 checks for an interrupt during the execution of every instruction. 3. If INTR is high, MP completes current instruction, disables the interrupt and sends INTA (Interrupt acknowledge) signal to the device that interrupted 4. INTA allows the I/O device to send a RST instruction through data bus. 5. Upon receiving the INTA signal, MP saves the memory location of the next instruction on the stack and the program is transferred to ‘call’ location (ISR Call) specified by the RST instruction 6. Microprocessor Performs the ISR. 7. ISR must include the ‘EI’ instruction to enable the further interrupt within the program. 8. RET instruction at the end of the ISR allows the MP to retrieve the return address from the stack and the program is transferred back to where the program was interrupted. 23 3.1.5 8085 Instruction Sets An instruction is a binary pattern designed inside a microprocessor to perform a specific function. The entire group of instructions, called the instruction set, determines what functions the microprocessor can perform. These instructions can be classified into the following five functional categories: data transfer (copy) operations, arithmetic operations, logical operations, branching operations, and machine-control operations. Data Transfer (Copy) Operations: The instructions copy data from a location called a source to another location called a destination, without modifying the contents of the source. In technical manuals, the term data transfer is used for this copying function. However, the term transfer is misleading; it creates the impression that the contents of the source are destroyed when, in fact, the contents are retained without any modification. Following is the table 1.1 showing the list of Data-transfer instructions with their meanings. Table 1.1 List Data Transfer Instructions Opcode Operand Meaning Explanation This instruction copies the Copy from the contents of the source Rd, Sc source (Sc) to register into the destination MOV M, Sc the destination register without any Dt, M (Dt) alteration. Example − MOV K, L The 8-bit data is stored in Rd, data Move the destination register or MVI immediate 8-bit memory. M, data Example − MVI K, 55L Load the The contents of a memory LDA 16-bit address accumulator location, specified by a 16- 24  bit address in the operand, are copied to the accumulator. Example − LDA 2034K The contents of the designated register pair point to a memory location. Load the This instruction copies the LDAX B/D Reg. pair accumulator contents of that memory indirect location into the accumulator. Example − LDAX K The instruction loads 16-bit Load the data in the register pair LXI Reg. pair, 16-bit data register pair designated in the register immediate or the memory. Example − LXI K, 3225L The instruction copies the contents of the memory location pointed out by the Load H and L address into register L and LHLD 16-bit address registers direct copies the contents of the next memory location into register H. Example − LHLD 3225K The contents of the accumulator are copied into the memory location STA 16-bit address 16-bit address specified by the operand. This is a 3-byte instruction, the second byte specifies 25  the low-order address and the third byte specifies the high-order address. Example − STA 325K The contents of the accumulator are copied into Store the the memory location STAX 16-bit address accumulator specified by the contents of indirect the operand. Example − STAX K The contents of register L are stored in the memory location specified by the 16-bit address in the operand and the contents of H register are stored into the next memory location Store H and L by incrementing the SHLD 16-bit address registers direct operand. This is a 3-byte instruction, the second byte specifies the low-order address and the third byte specifies the high-order address. Example − SHLD 3225K The contents of register H are exchanged with the Exchange H contents of register D, and XCHG None and L with D the contents of register L and E are exchanged with the contents of register E. 26  Example − XCHG The instruction loads the contents of the H and L registers into the stack pointer register. The Copy H and L contents of the H register SPHL None registers to the provide the high-order stack pointer address and the contents of the L register provide the low-order address. Example − SPHL The contents of the L register are exchanged with the stack location pointed out by the contents of the stack pointer Exchange H register. XTHL None and L with top of stack The contents of the H register are exchanged with the next stack location (SP+1). Example − XTHL The contents of the register pair designated in the operand are copied onto the stack in the following Push the sequence. PUSH Reg. pair register pair The stack pointer register onto the stack is decremented and the contents of the high order register (B, D, H, A) are copied into that location. 27  The stack pointer register is decremented again and the contents of the low- order register (C, E, L, flags) are copied to that location. Example − PUSH K The contents of the memory location pointed out by the stack pointer register are copied to the low-order register (C, E, L, status flags) of the operand. Pop off stack to The stack pointer is POP Reg. pair the register pair incremented by 1 and the contents of that memory location are copied to the high-order register (B, D, H, A) of the operand. The stack pointer register is again incremented by 1. Example – POP K Output the data The contents of the from the accumulator are copied into OUT 8-bit port address accumulator to the I/O port specified by a port with 8bit the operand. address Example − OUT K9L Input data to The contents of the input accumulator port designated in the IN 8-bit port address from a port operand are read and with 8-bit loaded into the 28  address accumulator. Example – IN 5KL Arithmetic Operations: These instructions perform arithmetic operations such as addition, subtraction, increment, and decrement. Addition - Any 8-bit number, or the contents of a register or the contents of a memory location can be added to the contents of the accumulator and the sum is stored in the accumulator. No two other 8-bit registers can be added directly (e.g., the contents of register B cannot be added directly to the contents of the register C). The instruction DAD is an exception; it adds 16-bit data directly in register pairs. Subtraction - Any 8-bit number, or the contents of a register, or the contents of a memory location can be subtracted from the contents of the accumulator and the results stored in the accumulator. The subtraction is performed in 2's compliment, and the results if negative, are expressed in 2's complement. No two other registers can be subtracted directly. Increment/Decrement - The 8-bit contents of a register or a memory location can be incremented or decrement by 1. Similarly, the 16-bit contents of a register pair (such as BC) can be incremented or decrement by 1. These increment and decrement operations differ from addition and subtraction in an important way; i.e., they can be performed in any one of the registers or in a memory location. Following is the table 1.2 showing the list of Arithmetic instructions with their meanings. Table 1.2 List Arithmetic Instructions Opcode Operand Meaning Explanation The contents of the register Add register or R or memory are added to ADD memory, to the M the contents of the accumulator accumulator and the result 29  is stored in the accumulator. Example − ADD K. The contents of the register or memory & M the Carry flag are added to the Add register to R contents of the ADC the accumulator accumulator and the result M with carry is stored in the accumulator. Example − ADC K The 8-bit data is added to the contents of the Add the accumulator and the result ADI 8-bit data immediate to is stored in the the accumulator accumulator. Example − ADI 55K The 8-bit data and the Carry flag are added to the Add the contents of the immediate to ACI 8-bit data accumulator and the result the accumulator is stored in the with carry accumulator. Example − ACI 55K The instruction stores 16- Load the bit data into the register LXI Reg. pair, 16bit data register pair pair designated in the immediate operand. Example − LXI K, 3025M 30  The 16-bit data of the Add the register specified register pair are DAD Reg. pair pair to H and L added to the contents of registers the HL register. Example − DAD K The contents of the register or the memory are Subtract the subtracted from the R register or the contents of the SUB memory from accumulator, and the result M the accumulator is stored in the accumulator. Example − SUB K The contents of the register or the memory & M the Subtract the Borrow flag are subtracted R source and from the contents of the SBB borrow from the accumulator and the result M accumulator is placed in the accumulator. Example − SBB K The 8-bit data is subtracted Subtract the from the contents of the SUI 8-bit data immediate from accumulator & the result is the accumulator stored in the accumulator. Example − SUI 55K The contents of register H Subtract the are exchanged with the immediate from SBI 8-bit data contents of register D, and the accumulator the contents of register L with borrow are exchanged with the 31  contents of register E. Example − XCHG The contents of the designated register or the Increment the R memory are incremented INR register or the by 1 and their result is M memory by 1 stored at the same place. Example − INR K The contents of the designated register pair are Increment incremented by 1 and their INX R register pair by result is stored at the same 1 place. Example − INX K The contents of the designated register or Decrement the R memory are decremented DCR register or the by 1 and their result is M memory by 1 stored at the same place. Example − DCR K The contents of the designated register pair are Decrement the decremented by 1 and their DCX R register pair by result is stored at the same 1 place. Example − DCX K The contents of the Decimal adjust DAA None accumulator are changed accumulator from a binary value to two 32  4-bit BCD digits. If the value of the low- order 4-bits in the accumulator is greater than 9 or if AC flag is set, the instruction adds 6 to the low-order four bits. If the value of the high- order 4-bits in the accumulator is greater than 9 or if the Carry flag is set, the instruction adds 6 to the high-order four bits. Example − DAA Logical Operations: These instructions perform various logical operations with the contents of the accumulator. AND, OR Exclusive-OR - Any 8-bit number, or the contents of a register, or of a memory location can be logically ANDed, Ored, or Exclusive-ORed with the contents of the accumulator. The results are stored in the accumulator. Rotate- Each bit in the accumulator can be shifted either left or right to the next position. Compare- Any 8-bit number or the contents of a register, or a memory location can be compared for equality, greater than, or less than, with the contents of the accumulator. Complement - The contents of the accumulator can be complemented. All 0s are replaced by 1s and all 1s are replaced by 0s. The following table 1. 3 shows the list of Logical instructions with their meanings. 33 Table 1.3 List of Logical Instructions Opcode Operand Meaning Explanation Compare the R The contents of the operand (register CMP register or or memory) are M compared with the M memory with the contents of the accumulator. accumulator Compare The second byte data is compared with CPI 8-bit data immediate with the contents of the accumulator. the accumulator Logical AND The contents of the accumulator are R register or logically AND with M the contents of the ANA M memory with the register or memory, and the result is accumulator placed in the accumulator. Logical AND The contents of the accumulator are ANI 8-bit data immediate with logically AND with the 8-bit data and the accumulator the result is placed in the accumulator. Exclusive OR The contents of the accumulator are R register or Exclusive OR with M the contents of the XRA memory with the register or memory, and the result is M accumulator placed in the accumulator. Exclusive OR The contents of the accumulator are XRI 8-bit data immediate with Exclusive OR with the 8-bit data and the accumulator the result is placed in the accumulator. Logical OR The contents of the accumulator are R register or logically OR with M the contents of the ORA M memory with the register or memory, and result is accumulator placed in the accumulator. Logical OR The contents of the accumulator are ORI 8-bit data immediate with logically OR with the 8-bit data and the the accumulator result is placed in the accumulator. Each binary bit of the accumulator is rotated left by one position. Bit D7 is Rotate the RLC None placed in the position of D0 as well as accumulator left in the Carry flag. CY is modified according to bit D7. Each binary bit of the accumulator is rotated right by one position. Bit D0 is Rotate the RRC None placed in the position of D7 as well as accumulator right in the Carry flag. CY is modified according to bit D0. 34  Each binary bit of the accumulator is rotated left by one position through the Rotate the Carry flag. Bit D7 is placed in the Carry RAL None accumulator left flag, and the Carry flag is placed in the through carry least significant position D0. CY is modified according to bit D7. Each binary bit of the accumulator is rotated right by one position through Rotate the the Carry flag. Bit D0 is placed in the RAR None accumulator right Carry flag, and the Carry flag is placed through carry in the most significant position D7. CY is modified according to bit D0. Complement The contents of the accumulator are CMA None accumulator complemented. No flags are affected. Complement The Carry flag is complemented. No CMC None carry other flags are affected. STC None Set Carry Set Carry Branching Operations: This group of instructions alters the sequence of program execution either conditionally or unconditionally. Jump - Conditional jumps are an important aspect of the decision-making process in the programming. These instructions test for a certain condition (e.g., Zero or Carry flag) and alter the program sequence when the condition is met. In addition, the instruction set includes an instruction called unconditional jump. Call, Return, and Restart - These instructions change the sequence of a program either by calling a subroutine or returning from a subroutine. The conditional Call and Return instructions also can test condition flags. The following table 1.4 shows the list of Branching instructions with their meanings. Table 1.4 List of Branch Instructions Opcode Operand Meaning Explanation JMP The program sequence 16-bit Jump is transferred to the 35  address unconditionally memory address given in the operand. Opcode Description Flag Status Jump on JC CY=1 Carry Jump on no JNC CY=0 Carry Jump on JP S=0 positive The program sequence is transferred to the Jump on 16-bit Jump memory address given JM S=1 address conditionally in the operand based on minus the specified flag of the PSW. Jump on JZ Z=1 zero Jump on no JNZ Z=0 zero Jump on JPE P=1 parity even Jump on JPO P=0 parity odd The program sequence Opcode Description Flag is transferred to the Status memory address given 16-bit Unconditional in the operand. Before address subroutine call transferring, the address Call on of the next instruction CC CY=1 after CALL is pushed Carry onto the stack. 36  Call on no CNC CY=0 Carry Call on CP S=0 positive Call on CM S=1 minus Call on CZ Z=1 zero Call on no CNZ Z=0 zero Call on CPE P=1 parity even Call on CPO P=0 parity odd The program sequence Return from is transferred from the RET None subroutine subroutine to the calling unconditionally program. Opcode Description Flag Status The program sequence is transferred from the subroutine to the calling Return from Return on program based on the RC CY=1 None subroutine Carry specified flag of the PSW conditionally and the program execution begins at the new address. Return on RNC CY=0 no Carry 37  Return on RP S=0 positive Return on RM S=1 minus Return on RZ Z=1 zero Return on RNZ Z=0 no zero Return on RPE P=1 parity even Return on RPO P=0 parity odd The contents of registers H & L are copied into the Load the program counter. The program PCHL None contents of H are placed counter with as the high-order byte HL contents and the contents of L as the low order byte. The RST instruction is used as software instructions in a program to transfer the program execution to one of the following eight locations. RST 0-7 Restart Instruction Restart Address RST 0 0000H 38  RST 1 0008H RST 2 0010H RST 3 0018H RST 4 0020H RST 5 0028H RST 6 0030H RST 7 0038H The 8085 has additionally 4 interrupts, which can generate RST instructions internally and doesn’t require any external hardware. Following are those instructions and their Restart addresses − Interrupt Restart Address TRAP 0024H RST 5.5 002CH RST 6.5 0034H RST 7.5 003CH 39 Machine Control Operations: These instructions control machine functions such as Halt, Interrupt, or do nothing. The microprocessor operations related to data manipulation can be summarized in four functions: 2. copying data 3. performing arithmetic operations 4. performing logical operations 5. testing for a given condition and alerting the program sequence Some important aspects of the instruction set are noted below: 1. In data transfer, the contents of the source are not destroyed; only the contents of the destination are changed. The data copy instructions do not affect the flags. 2. Arithmetic and Logical operations are performed with the contents of the accumulator, and the results are stored in the accumulator (with some expectations). The flags are affected according to the results. 3. Any register including the memory can be used for increment and decrement. 4. A program sequence can be changed either conditionally or by testing for a given data condition. Following is the table 1.5 showing the list of Control instructions with their meanings. Table 1.5 Control Instructions Opcode Operand Meaning Explanation NOP None No operation No operation is performed, i.e., the instruction is fetched and decoded. HLT None Halt and enter wait The CPU finishes state executing the current instruction and stops further execution. An interrupt or reset is necessary to exit from the halt state. DI None Disable interrupts The interrupt enable flip-flop is reset and all the interrupts are disabled except TRAP. EI None Enable interrupts The interrupt enable 40  flip-flop is set and all the interrupts are enabled. RIM None Read interrupt mask This instruction is used to read the status of interrupts 7.5, 6.5, 5.5 and read serial data input bit. SIM None Set interrupt mask This instruction is used to implement the interrupts 7.5, 6.5, 5.5, and serial data output. 3.1.6 Instruction Format An instruction has two parts: one is task to be performed, called the operation code (Opcode), and the second is the data to be operated on, called the operand. The operand (or data) can be specified in various ways. It may include 8-bit (or 16-bit) data, an internal register, a memory location, or 8-bit (or 16-bit) address. In some instructions, the operand is implicit. Instruction word size The 8085-instruction set is classified into the following three groups according to word size: 1. One-word or 1-byte instructions; 2. Two-word or 2-byte instructions; 3. Three-word or 3-byte instructions. One-Byte Instructions A 1-byte instruction includes the Opcode and operand in the same byte. Operand(s) are internal register and are coded into the instruction. For example: Task Opcode Operand Binary Hex code code Copy the contents of the accumulator MOV C, A 0100 1111 4FH in the register C. 41 Add the contents of register B to the ADD B 1000 0000 80H contents of the accumulator. Invert (compliment) each bit in the CMA 0010 1111 2FH accumulator. These instructions are stored in 8- bit binary format in memory; each requires one memory location. MOV Rd, Rs; Rd