Lecture 8.pdf

Logic Circuits II – Lecture 8 Cascaded Counters  2 Cascaded Counters Counters can be connected in cascade to achieve higher-modulus operation. Cascading means that...

Logic Circuits II – Lecture 8 Cascaded Counters  2 Cascaded Counters Counters can be connected in cascade to achieve higher-modulus operation. Cascading means that the last-stage output of one counter drives the input of the next counter. Asynchronous Cascading An example of two asynchronous counters connected in cascade is shown in the the figure below for a 2-bit and a 3-bit ripple counter Lecture 8- Logic cct II  3 Timing diagram for the cascaded counter configuration Lecture 8- Logic cct II  4 Synchronous Cascading When operating synchronous counters in a cascaded configuration, it is necessary to use the count enable and the terminal count functions to achieve higher-modulus operation. On some devices the count enable is labeled simply CTEN (or some other designation such as G), and terminal count (TC) is analogous to ripple clock output (RCO) on some IC counters. The figure shows a modulus-100 counter using two cascaded decade counters. Lecture 8- Logic cct II  5 The terminal count (TC) output of counter 1 is connected to the count enable (CTEN) input of counter 2. Counter 2 is inhibited by the LOW on its CTEN input until counter 1 reaches its last, or terminal, state and its terminal count output goes HIGH. This HIGH now enables counter 2, so that when the first clock pulse after counter 1 reaches its terminal count (CLK10), counter 2 goes from its initial state to its second state. Upon completion of the entire second cycle of counter 1 (when counter 1 reaches terminal count the second time), counter 2 is again enabled and advances to its next state. This sequence continues. Since these are decade counters, counter 1 must go through ten complete cycles before counter 2 completes its first cycle. In other words, for every ten cycles of counter 1, counter 2 goes through one cycle. Thus, counter 2 will complete one cycle after one hundred clock pulses. The overall modulus of these two cascaded counters is 10 * 10 = 100. When viewed as a frequency divider, the circuit in the previous slide divides the input clock frequency by 100. Cascaded counters are often used to divide a high-frequency clock signal to obtain highly accurate pulse frequencies. Cascaded counter configurations used for such purposes are sometimes called countdown chains. Lecture 8- Logic cct II  6 Example – Frequency Divider Suppose that you have a basic clock frequency of 1 MHz and you wish to obtain 100 kHz, 10 kHz, and 1 kHz; a series of cascaded decade counters can be used. If the 1 MHz signal is divided by 10, the output is 100 kHz. Then if the 100 kHz signal is divided by 10, the output is 10 kHz. Another division by 10 produces the 1 kHz frequency. The general implementation of this countdown chain is shown in the figure below, which represents a three cascaded decade counters forming a divide-by-1000 frequency divider with intermediate divide-by-10 and divide-by-100 outputs Lecture 8- Logic cct II  7 Counter Decoding In many applications, it is necessary that some or all of the counter states be decoded. The decoding of a counter involves using decoders or logic gates to determine when the counter is in a certain binary state in its sequence. Example Suppose that you wish to decode binary state 6 (110) of a 3-bit binary counter. When Q2 = 1, Q1 = 1, and Q0 = 0, a HIGH appears on the output of the decoding gate, indicating that the counter is at state 6. This can be done as shown in the figure below. This is called active-HIGH decoding. Note: Replacing the AND gate with a NAND gate provides active-LOW decoding. Lecture 8- Logic cct II  8 Implementing the Decoding of state 6 (110) Lecture 8- Logic cct II  9 Counter Applications A Digital Clock A common example of a counter application is in timekeeping systems. The figure in the next slide shows a simplified logic diagram of a digital clock that displays seconds, minutes, and hours. First, a 60 Hz sinusoidal ac voltage is converted to a 60 Hz pulse waveform and divided down to a 1 Hz pulse waveform by a divide-by-60 counter formed by a divide-by-10 counter followed by a divide-by-6 counter. Both the seconds and minutes counts are also produced by divide-by-60 counters, the details of which are shown in Figure 9–49. These counters count from 0 to 59 and then recycle to 0; synchronous decade counters are used in this particular implementation. Notice that the divide-by-6 portion is formed with a decade counter with a truncated sequence achieved by using the decoder count 6 to asynchronously clear the counter. The terminal count, 59, is also decoded to enable the next counter in the chain. Lecture 8- Logic cct II  A Digital Clock 10 Simplified logic diagram for a 12-hour digital clock Lecture 8- Logic cct II  11 Logic diagram of typical divide-by-60 counter using synchronous decade counters Note: the outputs are in binary order (the right-most bit is the LSB) Lecture 8- Logic cct II  12 Logic diagram for hours counter and decoders Lecture 8- Logic cct II