Logic Circuits (5.5) PDF

Logic Circuits (5.5) Learning Objectives 5.5.1.1 Identification of common logic gate symbols, tables and equivalent circuits (Level 2). 5.5.1.2 Describe the applications of logic circuits used in aircraft systems and schematic diagrams (Level 2). 5.5.1.3 Interpret and understand...

Logic Circuits (5.5) Learning Objectives 5.5.1.1 Identification of common logic gate symbols, tables and equivalent circuits (Level 2). 5.5.1.2 Describe the applications of logic circuits used in aircraft systems and schematic diagrams (Level 2). 5.5.1.3 Interpret and understand logic diagrams (S). 5.5.1.4 Describe the operation and use of latches and clocked flip-flop logic circuitry (S). 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 98 of 285 CASA Part 66 - Training Materials Only  Boolean Logic Representing Binary Quantities In digital systems, the information that is being processed is usually present in binary form. Binary quantities can be represented by any device that has only two operating states or possible conditions. For example, a switch has only two states: open or closed. We can arbitrarily let an open switch represent binary 0 and a closed switch represent binary 1. With this assignment, we can now represent any binary number as shown in the illustration on the left, where the states of the various switches represent 100102. Aviation Australia Binary quantities Another example is shown in the diagram on the right, where holes punched in paper are used to represent binary numbers. A punched hole is a binary 1, and absence of a hole is a binary 0. Numerous other devices have only two operating states or can be operated in two extreme conditions. Among these are a light bulb (bright or dark), diode (conducting or non-conducting), relay (energised or de-energised), transistor (cut off or saturated), photocell (illuminated or dark), thermostat (open or closed), mechanical clutch (engaged or disengaged) and spot on a magnetic disc (magnetised or demagnetised). In electronic digital systems, binary information is represented by voltages (or currents) that are present at the inputs and outputs of the various circuits. Typically, the binary 0 and 1 are represented by two nominal voltage levels. For example, 0 V might represent binary 0, and +5 V might represent binary 1. In actuality, because of circuit variations, the 0 and 1 would be represented by voltage ranges. This is illustrated below, where any voltage between 0 and 0.8 V represents a 0 and any voltage between 2 and 5 V represents a 1. All input and output signals normally fall within one of these ranges, except during transitions from one level to another. 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 99 of 285 CASA Part 66 - Training Materials Only  Aviation Australia TTL voltage levels We can now see another significant difference between digital and analogue systems. In digital systems, the exact value of a voltage is not important; for example, for the voltage assignments in the diagram, a voltage of 3.6 V means the same as a voltage of 4.3 V. In analogue systems, the exact value of a voltage is important. For instance, if the analogue voltage is proportional to the temperature measured by a transducer, the 3.6 V represents a different temperature than does 4.3 V. In other words, the voltage value carries significant information. This characteristic means the design of accurate analogue circuitry is generally more difficult than that of digital circuitry because of the way exact voltage values are affected by variations in component values, temperature and noise (random voltage fluctuations). 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 100 of 285 CASA Part 66 - Training Materials Only  Digital Signals and Timing Diagrams The diagram below shows a typical digital signal and its variation over time. It is a graph of voltage versus time (t) and is called a timing diagram. The horizontal time scale is marked off at regular intervals, beginning at t0 and proceeding to t1, t2 and so on. For the example timing diagram shown here, the signal starts at 0 V (a binary 0) at time t0 and remains there until time t1. At t1, the signal makes a rapid transition (jump) up to 4 V (a binary 1). At t2, it jumps back down to 0 V. Similar transitions occur at t3 and t5. Aviation Australia Timing diagram Note that the signal does not change at t4 but stays at 4 V from t3 to t5. The transitions on this timing diagram are drawn as vertical lines, so they appear to be instantaneous when they are not. In many situations, however, the transition times are so short compared to the times between transitions that we can show them on the diagram as vertical lines. We will encounter situations later where it will be necessary to show the transitions more accurately on an expanded time scale. Timing diagrams are used extensively to show how digital signals change with time, and especially to show the relationship between two or more digital signals in the same circuit or system. By displaying one or more digital signals on an oscilloscope or logic analyser, we can compare the signals to their expected timing diagrams. This is an essential part of the testing and troubleshooting procedures used in digital systems. 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 101 of 285 CASA Part 66 - Training Materials Only  Boolean Constants and Variables Boolean algebra differs significantly from ordinary algebra in that Boolean constants and variables are allowed to have only two possible values: 0 or 1. A Boolean variable is a quantity that may, at different times, be equal to either 0 or 1. Boolean variables are often used to represent the voltage level present on a wire or at the I/O terminals of a circuit. For example, in a certain digital system, the Boolean value of 0 might be assigned to any voltage in the range from 0 to 0.8 V, while the Boolean value of 1 might be assigned to any voltage in the range 2 to 5 V. Thus, Boolean 0 and 1 do not represent actual numbers but the state of a voltage variable, or what is called its logic level. A voltage in a digital circuit is said to be at the logic 0 level or the logic 1 level, depending on its actual numerical value. In digital logic, several other terms are used synonymously with 0 and 1. Some of the more common ones are shown in the table. We will use the 0/1 and LOW/HIGH designations most of the time. Logic 0 Logic 1 False True Off On Low High No Yes Open switch Closed Switch Boolean Values As we said in the introduction, boolean algebra is a means of expressing the relationship between a logic circuit's inputs and outputs. The inputs are considered logic variables whose logic levels at any time determine the output levels. In all our work to follow, we will use letter symbols to represent logic variables. For example, the letter A might represent a certain digital circuit input or output, and at any time we must have either A = 0 or A = 1; if not one, then the other. Because only two values are possible, Boolean algebra is relatively easy to work with as compared to ordinary algebra. In Boolean algebra there are no fractions, decimals, negative numbers, square roots, cube roots, logarithms, imaginary numbers and so on. In fact, in Boolean algebra there are only three basic operations: AND OR NOT 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 102 of 285 CASA Part 66 - Training Materials Only  AND, OR and NOT These basic operations are called logic operations. Digital circuits called logic gates can be constructed from diodes, transistors and resistors connected in such a way that the circuit output is the result of a basic logic operation (OR, AND, NOT) performed on the inputs. We will be using Boolean algebra first to describe and analyse these basic logic gates, then later to analyse and design combinations of logic gates connected as logic circuits. Aviation Australia Boolean logic 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 103 of 285 CASA Part 66 - Training Materials Only  Truth Tables A truth table is a means of describing how a logic circuit's output depends on the logic levels present at the circuit's inputs. The illustration depicts a truth table for one type of two-input logic circuit. The table lists all possible combinations of logic levels present at inputs A and B along with the corresponding output level X. The first entry in the table shows that when A and B are both at the 0 level, the output x is at the 0 level. The second entry shows that when input B is changed to the 1 state, so that A = 0 and B = 1, the output X becomes a 1. In a similar way, the table shows what happens to the output state for any set of input conditions. © Aviation Australia Truth table The next table shows samples of truth tables for three- and four-input logic circuits. Again, each table lists all possible combinations of input logic levels on the left, with the resultant logic level for output x on the right. Of course, the actual values for x will depend on the type of logic circuit. Note that there are four table entries for the two-input truth table, eight entries for the three-input truth table and 16 entries for the four-input truth table. The number of input combinations will equal 2N for an N input truth table. Also note that the list of all possible input combinations follows the binary counting sequence, so it is an easy matter to write down all the combinations without missing any. 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 104 of 285 CASA Part 66 - Training Materials Only  © Aviation Australia Three and four input truth tables 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 105 of 285 CASA Part 66 - Training Materials Only  Simple Logic Gates Logic Gates A logic gate is an ideal representation of a physical electronic device that implements boolean logic. A combination of logic gates creates a logic circuit. Logic circuits are used in electronic devices, creating integrated circuits and microprocessors. Logic circuits are formed by combining many logic gates. More complex logic circuits are assembled from simpler ones, which in turn are assembled from gates. The building block of all logic circuits is the logic gate. All logic actions, however complicated, can be analyzed and simplified into basic actions that are called OR gates, AND gates and NOT gates. Aviation Australia An integrated circuit is an example of a complex combination of logic circuits 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 106 of 285 CASA Part 66 - Training Materials Only  OR Gates The OR operation is the first of the three basic Boolean operations to be learned. The truth table below shows what happens when two logic inputs, A and B, are combined using the OR operation to produce an output, X. The table shows that the output is a logic 1 for every combination of input levels where one or more inputs are 1. The only case where X is a 0 is when both inputs are 0. © Aviation Australia OR gate (2 input) with truth table The boolean expression for the OR operation is: X = A + B In this expression, the + sign does not stand for ordinary addition; it stands for the OR operation. The OR operation is like ordinary addition except for the case where A and B are both 1; the OR operation produces 1 + 1 = 1, not 1 + 1 = 2. In boolean algebra, 1 is as high as we go, so we can never have a result greater than 1. The same holds true for combining three inputs using the OR operation. Here we have X = A + B + C. If we consider the case where all three inputs are 1, we have X = 1 + 1 + 1 = 1. The expression x = A + B is read as ‘X equals A OR B’, which means X will be 1 when A or B or both are 1. Likewise, the expression X = A + B + C is read as ‘X equals A OR B OR C’, which means X will be 1 when A or B or C or any combination of them are 1. 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 107 of 285 CASA Part 66 - Training Materials Only  © Aviation Australia OR gate (three input) with truth table The following illustration shows alternate equivalent OR logic gates and circuits. Aviation Australia OR Gate equivalents 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 108 of 285 CASA Part 66 - Training Materials Only  AND Gates The AND operation is the second basic boolean operation. The truth table below shows what happens when two logic inputs, A and B, are combined using the AND operation to produce output X. The table shows that X is a logic 1 only when both A and B are at the logic 1 level. For any case when one of the inputs is 0, the output is 0. The boolean expression for the AND operation is: X = A. B In this expression the "." sign stands for the boolean AND operation and not the multiplication operation. However, the AND operation on boolean variables operates the same as in ordinary multiplication, as examination of the truth table shows, so we can think of them as being the same. This characteristic can be helpful when evaluating logic expressions that contain AND operations. The expression X = A. B is read as ‘X equals A AND B’, which means that X will be 1 only when A and B are both 1. The sign is usually omitted so that the expression simply becomes X = AB. © Aviation Australia AND gate (two input) with truth table For the case when there are three AND inputs, we have X = A. B. C = ABC This is read as "X equals A AND B AND C", which means X will be 1 only when A, B and C are all 1. 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 109 of 285 CASA Part 66 - Training Materials Only  © Aviation Australia AND gate (three input) with truth table The following illustration shows alternate equivalent AND logic gates and circuits. Aviation Australia AND gate equivalents 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 110 of 285 CASA Part 66 - Training Materials Only  NOT Gate (Inverter) The NOT operation is unlike the OR and AND operations in that it can be performed on a single input variable. For example, if the variable A is subjected to the NOT operation, the result X can be expressed as follows. x = Ā It is often referred to as an inverter and throughout this lesson the terms 'NOT gate' and 'inverter' are used interchangeably. © Aviation Australia NOT Gate (Inverter) Where the over-bar represents the NOT operation. This expression is read as ‘X equals NOT A’ or ‘X equals the inverse of A’ or ‘x equals the complement of A’. Each of these is in common usage, and all indicate that the logic value of X = A is opposite to the logic value of A. The truth table clarifies this for the two cases A = 0 and A = 1. 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 111 of 285 CASA Part 66 - Training Materials Only  © Aviation Australia Not truth table Combining Gates Multiple input gates can be constructed by placing gates in special configurations. A three-input AND gate may be constructed using two AND gates connected as shown. A three-input OR gate may be constructed using two OR gates connected as shown. Aviation Australia Combining gates 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 112 of 285 CASA Part 66 - Training Materials Only  Logic Circuits Simple AND and OR Circuits Any logic circuit, no matter how complex, can be completely described using the three basic boolean operations because the OR gate, AND gate and NOT circuit are the basic building blocks of digital systems. For example, consider the circuit in the illustration. This circuit has three inputs, A, B and C, and a single output, X. Using the boolean expression for each gate, we can easily determine the expression for the output. Aviation Australia Simple AND and OR combined logic circuit The expression for the AND gate output is written A.B. This AND output is connected as an input to the OR gate along with C, another input. The OR gate operates on its inputs so that its output is the OR sum of the inputs. Thus, we can express the OR output as: X = A ⋅ B + C This final expression could also be written as X = C + A.B since it does not matter which term of the OR sum is written first. Aviation Australia Simple AND and OR combined logic circuit 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 113 of 285 CASA Part 66 - Training Materials Only  Occasionally, there may be confusion as to which operation in an expression is performed first. Thus, the expression A.B + C can be interpreted in two different ways: 1. A.B is ORed with C, or 2. A is ANDed with the term B + C. To avoid this confusion, it will be understood that if an expression contains both AND and OR operations, the AND operations are performed first unless there are parentheses in the expression, in which case the operation inside the parentheses is to be performed first. This is the same rule used in ordinary algebra to determine the order of operations. In the previous circuit, the output X = 1 when the following conditions are met: C is 1 C is 0 and A and B are both 1 When C is 1, A and B don't matter to the output due to the OR gate. However, if C is 0, then A and B produce a 1 from the AND gate and therefore a 1 from the OR gate. Any other conditions result in X = 0. Alternate AND OR Circuit To illustrate further, consider the circuit shown below. The expression for the OR gate output is simply A + B. This output serves as an input to the AND gate along with another input, C. Thus, we express the output of the AND gate as X = (A + B).C. Note the use of parentheses here to indicate that A and B are ORed first, before their OR sum is ANDed with C. Without the parentheses, it would be interpreted incorrectly since A + B.C means A is ORed with the product B.C. Aviation Australia Alternate AND and OR combined logic circuit 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 114 of 285 CASA Part 66 - Training Materials Only  Inverters in Circuits Whenever an inverter is present in a logic-circuit diagram (NOT gate), its output expression is simply equal to the input expression with a bar over it. In the case where an inverted value needs to be expressed in plain text, if the variable is A, it will be referred to as 'A_bar'. Where possible however, a physical bar will be drawn over the variable. The following diagram below shows two examples of circuits using inverters. Aviation Australia Gates with inverters On the left, input A is fed through an inverter, whose output is therefore A_bar. The inverter output is then fed to an OR gate together with B. The equation (for the circuit on the left) is A_bar + B. Note that the bar is over the A alone, indicating that A is first inverted and then ORed with B. On the right, the output of the OR gate is equal to A + B and is fed through an inverter. The inverter output is therefore equal to the complete input expression negated. X equals the inverse of (A OR B). – (lef t) → X = A + B – (right) → X = A + B Note that in the right circuit, the bar covers the entire expression (A + B). This is important because, as will be shown later, the following expressions are NOT equal. – ¯ A + B̄ not equal to A + B e. g. A = 1, B = 0 – – ¯ ¯ ⟹ A + B = 1 + 0 = 1 – – ⟹ A + B = 1 + 0 = 0 The first expression indicates that A is inverted and B is inverted, and the results are then ORed, whereas the second expression indicates that A is ORed with B and then their OR sum is inverted. 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 115 of 285 CASA Part 66 - Training Materials Only  Logic Circuit Worked Examples Example 1 Find the outputs of each logic gate and the total output of the logic circuit below. Write each answer using the correct logic syntax. Aviation Australia Logic circuit example 1 Example 2 Find the outputs of each logic gate and the total output of the logic circuit below. Write each answer using the correct logic syntax. Aviation Australia Logic circuit example 2 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 116 of 285 CASA Part 66 - Training Materials Only  Compound Logic Gates NOR Gate The symbol for a two-input NOR gate is shown below. It is the same as the OR gate symbol except that it has a small circle on the output. The small circle represents the inversion operation. Thus, the NOR gate operates like an OR gate followed by an inverter. © Aviation Australia NOR gate (two input) and truth table The truth table shows that the NOR gate output is the exact inverse of the OR gate output for all possible input conditions. An OR gate output goes HIGH when any input is HIGH, and the NOR gate output goes LOW when any input is HIGH. This same operation can be extended to NOR gates with more than two inputs. 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 117 of 285 CASA Part 66 - Training Materials Only  Aviation Australia NOR gate and NOR gate timing diagram Aviation Australia NOR gate circuit equivalents 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 118 of 285 CASA Part 66 - Training Materials Only  NAND Gate The symbol for a two-input NAND gate is shown in the diagram. It is the same as the AND gate symbol except for the small circle on its output. Once again, this small circle denotes the inversion operation. The output is the same as an AND gate with a bar over all the inputs (shown below). © Aviation Australia NAND gate (two input) with truth table The NAND operates like an AND gate followed by an inverter (NOT), thus the circuits in the diagram below are equivalent. Aviation Australia NAND gate is the equivalent to an AND followed by a NOT The truth table in the diagram shows that the NAND gate output is the exact inverse of the AND gate for all possible input conditions. The AND output goes HIGH only when all inputs are HIGH, while the NAND output goes LOW only when all inputs are HIGH. This same characteristic is true of NAND gates having more than two inputs. 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 119 of 285 CASA Part 66 - Training Materials Only  Aviation Australia NAND timing diagram Exclusive-OR (XOR) An exclusive-OR (XOR), in the case of a two input circuit, means that if the input is either A or B it returns 1. If the input is both A and B it returns 0, and if the input is neither A or B it returns 0. Consider the logic circuit in the diagram below. Aviation Australia XOR gate and truth table To reiterate the explanation above, the accompanying truth table shows that X = 1 for only the following two cases: A = 0 and B =1 A = 1 and B = 0 Thus, the output of an XOR produces a HIGH whenever the two inputs are at opposite levels. This exclusive-OR circuit will hereafter be abbreviated to XOR. ¯ ¯ X = AB + AB or alternatively ¯ (A. B) + (A. B̄) = 1 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 120 of 285 CASA Part 66 - Training Materials Only  This combination of logic gates occurs quite often and is very useful in certain applications. In fact, the XOR circuit has been given a simplified symbol of its own, shown in the diagram below. This symbol is assumed to contain all the logic contained in the XOR circuit and therefore has the same logic expression and truth table. This XOR circuit is commonly referred to as an XOR gate, and we consider it another type of logic gate. © Aviation Australia XOR gate (two input) and truth table The IEEE/ANSI symbol for an XOR gate is shown below as well as the shorthand logic equation for an XOR. The dependency notation (= 1) inside the block indicates that the output will be active-HIGH only when a single input is HIGH. © Aviation Australia XOR gate shorthand and IEEE/ANSI symbol (alternate) 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 121 of 285 CASA Part 66 - Training Materials Only  The ⊕ symbol represents XOR. Exclusive-NOR (XNOR) The exclusive-NOR circuit (abbreviated XNOR) operates completely opposite to the XOR circuit. The following diagram shows an XNOR circuit and its accompanying truth table. Aviation Australia XNOR gate and truth table The output expression of an XNOR circuit is as follows. – X = AB + AB This indicates along with the truth table that X will be 1 for two cases: A = B = 1 (the AB term) A = B = 0 (the not AB term). The XNOR produces a HIGH output whenever the two inputs are at the same level. It should be apparent that the output of the XNOR circuit is the exact inverse of the output of the XOR circuit. The traditional symbol for an XNOR gate is obtained by simply adding a small circle at the output of the XOR symbol. 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 122 of 285 CASA Part 66 - Training Materials Only  © Aviation Australia XNOR gate (two input) and IEEE / ANSI alternative symbol The IEEE/ANSI symbol adds the small triangle on the output of the XOR symbol. Both symbols indicate an output that goes to its active-LOW state when only one input is HIGH. The Universal Gates The NOR gate and the NAND gate can be said to be universal gates since combinations of them can be used to accomplish any of the basic operations and can thus produce an inverter, an OR gate or an AND gate. The non-inverting gates do not have this versatility since they cannot produce an invert. Aviation Australia Universal gate 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 123 of 285 CASA Part 66 - Training Materials Only  Buffers If two inverter gates were to be connected together so that the output of one fed into the input of the other, the inverters would cancel each other out. This is a buffer. While this may seem like a pointless thing to do in a theoretical logic circuit, in a real electric logic circuit, it has many practical benefits. It is useful as an impedance-matching device (and operates slightly different depending on the type - voltage buffer or current buffer). In logic circuits, the buffer is a single-input device which has a gain of 1, mirroring the input at the output. The basic emitter follower can be used as a buffer for a voltage source. The common collector amplifier (BJT) is often called an emitter follower since its output is taken from an emitter resistor. Aviation Australia Buffer An op-amp voltage follower can also serve as a voltage buffer. The voltage buffer, also known as a unity gain amplifier (an amplifier with a gain of 1) is one of the simplest possible op-amp circuits with closed-loop feedback. The voltage follower with an ideal op-amp gives simply Vout = Vin, but this turns out to be a very useful service because the input impedance of the op-amp is very high, giving effective isolation of the output from the signal source. You draw very little power from the signal source, thus avoiding ‘loading’ effects. The voltage follower is often used to construct buffers for logic circuits. Aviation Australia OpAmp Buffer #1 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 124 of 285 CASA Part 66 - Training Materials Only  Inverting Buffers (Inverter) The inverting buffer is a single-input device which produces the state opposite the input. If the input is high, the output is low, and vice versa. This device is commonly referred to as just an inverter. A transistor switch with a collector resistor can serve as an inverting buffer. When the switch is open, no current flows in the base, so the collector current is cut off. The resistor RC must be small enough to drive the transistor to saturation so that most of the voltage VCC appears across the load. The output is taken below the load resistor and can function as an inverting buffer in digital circuits. Aviation Australia Inverting buffers Aviation Australia Op-amp buffer An op-amp inverting amplifier with a gain of 1 serves as an inverting buffer. For an ideal op-amp, the inverting amplifier gain is given simply by: Vout −Rf = Vin R1 For equal resistors, it has a gain of -1 and is used in digital circuits as an inverting buffer. 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 125 of 285 CASA Part 66 - Training Materials Only  Alternate Inverter Symbol The inverter symbol is utilised as required, but a more common method of indicating a signal is inverted is simply using an inversion symbol, O, on the leg of the device. Aviation Australia Inverter Symbol IEEE Gate Symbols Together with the American National Standards Institute (ANSI), the Institute of ANSI Electrical and Electronic Engineers (IEEE) has developed a standard set of logic IEEE symbols. The most recent revision of the standard is ANSI/IEEE Std 91-1984, IEEE Standard Graphic Symbols for Logic Functions. It is compatible with standard 617 of the International Electrotechnical Commission (IEC) and must be used in all logic diagrams drawn for the U.S. Department of Defense. These symbols are being used more and more as time progresses. Aviation Australia IEEE Symbols 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 126 of 285 CASA Part 66 - Training Materials Only  Fabrication of Gates Gates are fabricated as IC packs in dual, triple or quadruple circuit arrangements. The diagram illustrates a typical presentation of manufacturer's operating data, which in this example relates to a quadruple two-input NAND circuit arrangement contained within a Dual-In-Line (DIL) pack monolithic IC. The numbered squares represent the connecting pins. Aviation Australia Quad two input NAND gates 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 127 of 285 CASA Part 66 - Training Materials Only  Worked Logic Circuit Examples Logic Circuit Example Problems The following section provides some examples that may be worked through to demonstrate and understanding of logic gates, logic circuits and timing diagrams. The following section contains the answers for each example, however it is recommended that the questions are attempted prior to viewing the solutions. Determine the logic operation performed by the following circuits. Each circuit can be simplified into a single logic operation (a single logic gate). © Aviation Australia Write the truth tables and simplify the logic circuits above 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 128 of 285 CASA Part 66 - Training Materials Only  Logic Circuit Example Solutions The truth table and single combined gate solutions for the previous section. © Aviation Australia Simplified logic circuits (solutions) 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 129 of 285 CASA Part 66 - Training Materials Only  Logic Waveform Example Problems The logic waveforms below are applied to the inputs of both an OR and a XOR gate. Drawn below are the output waveforms you would expect for each. Note that logic level 1 (HIGH) is represented by +5 V, and similarly logic level 0 (LOW) is represented by 0 V. Aviation Australia Logic waveform 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 130 of 285 CASA Part 66 - Training Materials Only  Logic Waveform Example Solutions When the inputs A and B exit the gates below, these are the expected waveforms. Aviation Australia When the inputs A and B exit the gates above, these are the expected waveforms Electrical Circuit Logic Examples Aviation Australia Switch representations - many circuits in aircraft may be schematically represented by logic circuits for ease Many circuits in aircraft may be schematically represented by logic circuits for ease. 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 131 of 285 CASA Part 66 - Training Materials Only  Flip-Flops and Latches Flip-Flops The Application of Flip-Flops One of the more interesting things you can do with logic gates is store binary data. Flip-flop circuits are an arrangement of logic gates that will remember an input value. It maintains a state (1 or 0), until it is directed to change its state. Historically, transistor versions of these circuits were common in computers, even after the introduction of integrated circuits, though flip-flops made from logic gates are very common now. The first flip-flop circuit was known differently as multivibrators or trigger circuits. This lesson focuses on flip-flops as they relate to logic circuits and as prerequisite knowledge to further topics in this module. Some of the most common applications of flip-flops are: Counters Registers Frequency Divider circuits Data transfer Flip-Flops In electronics, a flip-flop (or latch) is a circuit that has two stable states and can be used to store state information, it is known as a bistable multivibrator. As discussed, the basic function of a flip-flop is to store a single bit of binary data. The application of a pulse at one input, causes it to 'flip' into one of its two stable states and remain latched in that state. A pulse at the other input causes it to 'flop' into the other state. The two output terminals are usually designated Q and Q bar (a bar above the Q), remembering that the bar means to invert in logic circuits, so it can also be understood as 'Not Q'. The in-text descriptions of 'Not Q' will be referenced using Q' to denote the inversion. © Aviation Australia SR Flip-flop block diagram 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 132 of 285 CASA Part 66 - Training Materials Only  A flip-flop is made up of a latch circuit. For example, the S-R flip-flop makes use of the S-R latch logic circuit. An S-R flip-flop typically has a clock to complete the flip-flop device, however initially, our explanations of the S-R flip-flop will ignore the clock. The types of flip-flops circuits we are going to discuss are the: Set-Reset (SR) flip-flop Master-Slave (JK) flip-flop Data (D) flip-flop Toggle (T) flip-flop. NAND Gate S-R Flip-Flops A simple type of flip-flop is the S-R (Set-Reset) Flip-Flop (or S-R Latch). It can be constructed using two NAND gates. Aviation Australia SR flip-flop with two NAND gates The fundamental operation of flip-flops may be understood using the S-R flip-flop diagram above. Where S is Set, R is Reset, Q is output gate 1 and Q' is output gate 2. This circuit is also known as an S-R latch. Where the outputs "latch" to either 1 or 0 based on a pulsed input. Keep in mind this is a NAND gate version, other gates can be used to create latch circuits that operate the same way. Invalid State The term invalid (or indeterminate) noted in some cases means that for the inputs shown, the flip- flops may switch to reverse the output states or they may remain in an existing condition; in other words, they get into a state of ‘limbo’ and so produce undesirable operation. S-R Latch Operation (NAND) Before any values are applied to the inputs, the latch is in an invalid state. The latch is not made to operate in this state. Referring to the truth table above, it can be seen that this S-R latch is at rest when both inputs are high. When both inputs are high, the latch remains in the last state it was told to switch to. 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 133 of 285 CASA Part 66 - Training Materials Only  Assume that power is applied and the following initial values are met: S and R inputs are connected (and current flows through the logic gate) and they are logic 0 and logic 1, respectively (a high is provided to the R input). The outputs of gates 1 and 2 (Q and Q') are initially logic 0 and logic 1 respectively. What will happen inside this latch is, it will cause the outputs to flip, so Q will become 1 and Q' will become 0. How the 'flip' happens: 1. In this case, before the flip-flop has a chance to change, the S and R inputs are connected so that S is a logic 0 (low) and R is a logic 1 (high). Remembering that the outputs at this point in time are Q = 0 and Q' = 1. 2. Firstly (looking from top to bottom), the 0 and 1 entering the upper NAND gate produce a logic 1 at the output. 3. The 1 at the output of the upper NAND gate applies a 1 to the upper input of the lower NAND gate. Since R is already 1 and this new input becomes 1, the two high values on the lower NAND gate produces a 0 at the output. 4. The logic 0 value from the output of the lower NAND gate when applied to the input of the upper NAND gate does not affect the upper gates output and it therefore remains at 1. 5. This now leaves the gates output both flipped, the Q output is logic 1 and Q' is logic 0. Aviation Australia The flip (step-by-step) 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 134 of 285 CASA Part 66 - Training Materials Only  Under normal conditions, the outputs will be the inverse of each other. If S and R inputs are now reversed, flip-flop output will cycle. It is worth noting however, that this flip started in an invalid state - therefore the output was subject to 'race conditions' and is unpredictable. Once the latch is in a known state (either set or reset), the flip-flop can function as intended. Shown below is a diagram with the inputs changed to both 1s. Referencing the truth table, this has no effect on the latch as expected. Now the S and R inputs are reversed, S at 1 and R at 0. The 'flop' occurs (shown in the bottom part of the diagram below). 1. The 1 and the 0 on the lower NAND gate produce a 1 at the Q' output. 2. The 1 at the output of the lower NAND gate is applied to input of upper NAND gate. 3. These two 1s now on the upper NAND gate produce a 0 at the Q output. 4. The 0 at the output of the upper NAND gate is applied to the input of the lower NAND gate, but the output unaffected and remains at 1. Aviation Australia The flop (step-by-step) 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 135 of 285 CASA Part 66 - Training Materials Only  Regular Operation You may have noticed that the set and reset inputs when high, actually do the opposite of their named role. This is because the S-R flip-flop is at rest in the high position, and when the set input is pulsed low, the latch is set. When the reset input is pulsed low, the latch is reset. Therefore, the Set (S) and Reset (R) inputs are normally resting in the HIGH (1) state. Then an input is pulsed low whenever we want to change the latch outputs. Summary A flip-flop has a basic function of storing a single bit of binary data. It is so called because the application of a suitable pulse at one input causes it to ‘flip’ into one of its two stable states and remain latched in that state until a pulse at a second input causes it to ‘flop' into the other state (as shown previously). The device has two output terminals Q and Q', and the logic states of these terminals are referred to respectively as the normal and the complement. When the normal state is logic 1 and the complement is logic 0, the device is said to be set, and conversely it is said to be reset when the normal state is logic 0 and the complement is logic 1. The latching characteristic has some very important uses (computer memory). Aviation Australia S-R Flip-Flop (NAND gate) switching 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 136 of 285 CASA Part 66 - Training Materials Only  NOR Gate S-R Flip-Flops The most basic flip-flop circuit can be constructed from either two NAND gates, as described in previous slides, or two NOR gates. This latch regular operation is reversed. Aviation Australia NOR gate flip-flop Aviation Australia S-R flip-flop (NOR gate) operation 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 137 of 285 CASA Part 66 - Training Materials Only  Setting the S-R Latch (NOR) When the Set input is momentarily pulsed low and Clear is kept high, Q will latch to a high or 1 – high on Q keeps Q' at 0. When ‘Set’ returns to high – Q' unaffected: remains at 0 – latch remains ‘set’. If ‘Set’ selected low again – Q' output is still unaffected – latch state remains ‘set’. Low pulse on ‘Set’ input will always cause latch to end up in Q = 1 state – setting the latch or flip-flop. Clearing the S-R Latch (NOR) To clear the latch, 'Reset' is pulsed 'high' while 'Set' remains 'low'. When 'Reset' is pulsed high, Q goes low and the two lows on lower gate latches Q' at 1. When 'Reset' returns to low, Q is held at 0 due to 1 applied to the upper gate input from Q' output and the latch remains in 'Reset' state. If 'Reset' is selected high again, Q output is unaffected – latch remains in 'reset' state. High pulse on 'Reset' input will always cause latch to end up in Q = 0 state and reset the latch or flip- flop. Alternate Representations NAND gate flip-flops typically have S and R held high and will trigger the flip-flop when pulsed low – the inputs are active-low. When Set is pulsed low, Q = 1, and when Reset is pulsed low, Q = 0. NOR gate flip-flops typically have S and R held low and will trigger the flip-flop when pulsed high – the inputs are active-high. When Set is pulsed high, Q = 1, and when Reset is pulsed high, Q = 0. Thus, the Set and Reset (or Clear) inputs are reversed between the NAND gate and NOR gate configurations. 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 138 of 285 CASA Part 66 - Training Materials Only  Flip-Flop Invalid and Initial States As introduced previously, the flip-flop can enter an invalid state. This is when the inputs cause the outputs to be either all high or all low. This occurs during either simultaneous setting or resetting and on start-up of the flip-flop device. Simultaneous Setting and Resetting The last case to consider is the case in which the Set and Reset inputs are simultaneously pulsed low. This will produce high levels at both NAND outputs, which is an undesired condition as the two outputs are supposed to be inverses of each other. Furthermore, when the Set and Reset inputs return high, the resulting output state will depend on which input returns high first. Simultaneous transitions back to the 1 state will produce unpredictable results. For these reasons, the Set = Reset = 0 condition is not used. The term indeterminate (or invalid) noted in some cases means that for the inputs shown, the flip- flops may switch to reverse the output states or they may remain in an existing condition; in other words, they get into a state of ‘limbo’ and so produce undesirable operation, where both outputs are high or both outputs are low. If the inputs are returned from the invalid state to 0 or 1 (depending on which type of gate we are referring to) simultaneously, the resulting output state is unpredictable. This input condition should not be used. Flip-Flop State on Power-Up When power is applied to a circuit, it is not possible to predict the starting state of a flip-flop’s output if its Set and Reset inputs are in their inactive state (e.g. S = R = 1 for a NAND latch, S = R = 0 for a NOR latch). There is just as much chance that the starting state will be Q = 0 as Q = 1. It will depend on factors such as internal propagation delays, parasitic capacitance and external loading. If a latch or flip-flop must start off in a state to ensure the proper operation of a circuit, then it must be placed in that state by momentarily activating the Set or Reset input at the start of the circuit’s operation. This is often achieved by applying a pulse to the appropriate input. 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 139 of 285 CASA Part 66 - Training Materials Only  S-R Flip-Flop Practical Usage It is virtually impossible to obtain a ‘clean’ voltage transition from a mechanical switch because of the phenomenon of contact bounce. The action of moving the switch from contact position 1 to 2 produces several output voltage transitions as the switch bounces (makes and breaks contact with contact 2 several times) before coming to rest on contact 2. Aviation Australia S-R flip-flops as a de-bounce circuits The multiple transitions on the output signal generally last no longer than a few milliseconds, but they are unacceptable in many applications. A NAND latch can be used to prevent the presence of switch bounce from affecting the output. For such applications as counters and shift registers, flip-flops are operated synchronously with a clocked or strobed pulse train derived from an astable or free-running multivibrator, or a crystal oscillator, and applied to a third input. They consist of NAND or NOR gates and are fabricated as digital ICs. 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 140 of 285 CASA Part 66 - Training Materials Only  Application of Logic Circuits in Aircraft Systems Emergency Electrical Power Logic (A-320; Example ONLY) A-320 emergency generator operation Automatic Operation If AC BUS 1 and 2 are lost above a given airspeed (100 kt), the Ram Air Turbine (RAT) will extend automatically. The RAT is an air-driven turbine that drives a hydraulic pump. As the AC generator is not yet available, the AC ESSENTIAL BUS and DC ESS BUS are respectively supplied by the STATIC INVERTER and BATTERY 2. The activation of the emergency generator via the blue hydraulic system takes place only if the landing gear is not compressed. When the emergency generator is available, it supplies the AC ESS BUS via Essential Transformer Rectifier (ESS TR), the DC ESS BUS. As the nose landing gear is compressed, the AC ESS BUS and DC ESS BUS are respectively supplied by the STATIC INVERTER and BATTERY 2. 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 141 of 285 CASA Part 66 - Training Materials Only  Operation in Flight If AC BUS 1 and 2 are lost and the RAT does not extend, the FAULT light comes on red on the EMERGENCY ELECTRICAL POWER panel. The RAT must be manually extended to power the emergency generator. This is done by pressing the guarded MANUAL ON on the EMER ELEC PWR panel. WARNING: If the MAN ON is pressed in, the RAT extends, even in cold aircraft configuration. Emergency Generator Test The emergency generator operational test is carried out to check the emergency generator parameters and the corresponding network supply. For test purposes, the blue hydraulic system must be pressurised thanks to the BLUE PUMP OVERRIDE, and the EMER GEN TEST must be held pressed in. As the emergency generator is connected, the generator parameters must be checked on the ECAM display. Overview (747 Scavenge Pump Control and Operation – Centre Wing) A scavenge pump (fuel) is a pump that sits in the lowest point of the fuel tank and pumps out the last of the fuel in the tank. Normal fuel pumps are fuel cooled and lubricated, whereas a scavenge pump must be rated to run dry for a time. The Centre Wing Tank (CWT) Scavenge Pump is automatic and removes residual fuel remaining in the CWT that cannot be pumped out by the Override/Jettison (O/J) pumps. Aviation Australia 747 fuel tank arrangement 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 142 of 285 CASA Part 66 - Training Materials Only  Control The pump is controlled by either of the Fuel System Management Cards (FSMC). The diagram shows FSMC (A). Aviation Australia Scavenge pump control schematic The Centre Wing Tank Left and Right (CWT L&R O/J) pumps will not fully empty the CWT. The left O/J pump inlet is uncovered at 2700 kg and the right O/J pump inlet at 1300 kg. The pump may be manually operated using the CWT Scavenge Pump Defuel Switch. Manual control is used during ground defueling operations. 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 143 of 285 CASA Part 66 - Training Materials Only  Operation Any one of three conditions will cause the FSMC to generate a Scavenge Pump ON Command. Two conditions will cause the pump to run for two hours or until the pump pressure switch senses a low pressure for five minutes: In the air with either CWT L&R O/J turned on and its respective pump not developing pressure A 30-s pump On Command when the Reserve Transfer Valves are opened, and A CMC Ground Test, during which the pump runs for the length of the test. EICAS Messages Scavenge Pump operation is monitored for 5 min each flight. Monitoring begins after the aircraft has been airborne for a minimum of 30 min and the pump has been commanded On. If a low pressure is sensed during this 5-min window, a latched ‘Fuel Scav Pump’ Status Message is generated. A ‘Scav Pump On’ Advisory Message is generated when the pump is developing pressure and the aircraft has been on the ground for longer than 60 s. 2023-03-03 B1-05a Digital Techniques / Electronic Instrument Systems Page 144 of 285 CASA Part 66 - Training Materials Only