Logic Circuits (5.5) PDF

Logic Circuits (5.5) Learning Objectives 5.5.1.1 Identification of common logic gate symbols, tables and equivalent circuits (Level 2). 5.5.1.2 Describe the applications of logic circuits used in aircraft systems and schematic diagrams (Level 2). 5.5.2.1 Interpret and understand lo...

Logic Circuits (5.5) Learning Objectives 5.5.1.1 Identification of common logic gate symbols, tables and equivalent circuits (Level 2). 5.5.1.2 Describe the applications of logic circuits used in aircraft systems and schematic diagrams (Level 2). 5.5.2.1 Interpret and understand logic diagrams (Level 2). 5.5.2.2 Describe the operation and use of latches and clocked flip-flop logic circuitry (S). 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 118 of 444 CASA Part 66 - Training Materials Only  Boolean Logic Representing Binary Quantities In digital systems, the information that is being processed is usually present in binary form. Binary quantities can be represented by any device that has only two operating states or possible conditions. For example, a switch has only two states: open or closed. We can arbitrarily let an open switch represent binary 0 and a closed switch represent binary 1. With this assignment, we can now represent any binary number as shown in the illustration on the left, where the states of the various switches represent 100102. Aviation Australia Binary quantities Another example is shown in the diagram on the right, where holes punched in paper are used to represent binary numbers. A punched hole is a binary 1, and absence of a hole is a binary 0. Numerous other devices have only two operating states or can be operated in two extreme conditions. Among these are a light bulb (bright or dark), diode (conducting or non-conducting), relay (energised or de-energised), transistor (cut off or saturated), photocell (illuminated or dark), thermostat (open or closed), mechanical clutch (engaged or disengaged) and spot on a magnetic disk (magnetised or demagnetised). In electronic digital systems, binary information is represented by voltages (or currents) that are present at the inputs and outputs of the various circuits. Typically, the binary 0 and 1 are represented by two nominal voltage levels. For example, 0 V might represent binary 0, and +5 V might represent binary 1. In actuality, because of circuit variations, the 0 and 1 would be represented by voltage ranges. This is illustrated below, where any voltage between 0 and 0.8 V represents a 0 and any voltage between 2 and 5 V represents a 1. All input and output signals normally fall within one of these ranges, except during transitions from one level to another. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 119 of 444 CASA Part 66 - Training Materials Only  Aviation Australia TTL voltage levels We can now see another significant difference between digital and analogue systems. In digital systems, the exact value of a voltage is not important; for example, for the voltage assignments in the diagram, a voltage of 3.6 V means the same as a voltage of 4.3 V. In analogue systems, the exact value of a voltage is important. For instance, if the analogue voltage is proportional to the temperature measured by a transducer, the 3.6 V represents a different temperature than does 4.3 V. In other words, the voltage value carries significant information. This characteristic means the design of accurate analogue circuitry is generally more difficult than that of digital circuitry because of the way exact voltage values are affected by variations in component values, temperature and noise (random voltage fluctuations). 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 120 of 444 CASA Part 66 - Training Materials Only  Digital Signals and Timing Diagrams The diagram below shows a typical digital signal and its variation over time. It is a graph of voltage versus time (t) and is called a timing diagram. The horizontal time scale is marked off at regular intervals, beginning at t0 and proceeding to t1, t2 and so on. For the example timing diagram shown here, the signal starts at 0 V (a binary 0) at time t0 and remains there until time t1. At t1, the signal makes a rapid transition (jump) up to 4 V (a binary 1). At t2, it jumps back down to 0 V. Similar transitions occur at t3 and t5. Aviation Australia Timing diagram Note that the signal does not change at t4 but stays at 4 V from t3 to t5. The transitions on this timing diagram are drawn as vertical lines, so they appear to be instantaneous when they are not. In many situations, however, the transition times are so short compared to the times between transitions that we can show them on the diagram as vertical lines. We will encounter situations later where it will be necessary to show the transitions more accurately on an expanded time scale. Timing diagrams are used extensively to show how digital signals change with time, and especially to show the relationship between two or more digital signals in the same circuit or system. By displaying one or more digital signals on an oscilloscope or logic analyser, we can compare the signals to their expected timing diagrams. This is an essential part of the testing and troubleshooting procedures used in digital systems. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 121 of 444 CASA Part 66 - Training Materials Only  Boolean Constants and Variables Boolean algebra differs significantly from ordinary algebra in that Boolean constants and variables are allowed to have only two possible values: 0 or 1. A Boolean variable is a quantity that may, at different times, be equal to either 0 or 1. Boolean variables are often used to represent the voltage level present on a wire or at the I/O terminals of a circuit. For example, in a certain digital system, the Boolean value of 0 might be assigned to any voltage in the range from 0 to 0.8 V, while the Boolean value of 1 might be assigned to any voltage in the range 2 to 5 V. Thus, Boolean 0 and 1 do not represent actual numbers but the state of a voltage variable, or what is called its logic level. A voltage in a digital circuit is said to be at the logic 0 level or the logic 1 level, depending on its actual numerical value. In digital logic, several other terms are used synonymously with 0 and 1. Some of the more common ones are shown in the table. We will use the 0/1 and LOW/HIGH designations most of the time. Logic 0 Logic 1 False True Off On Low High No Yes Open switch Closed Switch 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 122 of 444 CASA Part 66 - Training Materials Only  Boolean Values As we said in the introduction, boolean algebra is a means of expressing the relationship between a logic circuit's inputs and outputs. The inputs are considered logic variables whose logic levels at any time determine the output levels. In all our work to follow, we will use letter symbols to represent logic variables. For example, the letter A might represent a certain digital circuit input or output, and at any time we must have either A = 0 or A = 1; if not one, then the other. Because only two values are possible, Boolean algebra is relatively easy to work with as compared to ordinary algebra. In Boolean algebra there are no fractions, decimals, negative numbers, square roots, cube roots, logarithms, imaginary numbers and so on. In fact, in Boolean algebra there are only three basic operations: AND OR NOT AND, OR and NOT These basic operations are called logic operations. Digital circuits called logic gates can be constructed from diodes, transistors and resistors connected in such a way that the circuit output is the result of a basic logic operation (OR, AND, NOT) performed on the inputs. We will be using Boolean algebra first to describe and analyse these basic logic gates, then later to analyse and design combinations of logic gates connected as logic circuits. Aviation Australia Boolean logic 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 123 of 444 CASA Part 66 - Training Materials Only  Truth Tables A truth table is a means of describing how a logic circuit's output depends on the logic levels present at the circuit's inputs. The illustration depicts a truth table for one type of two-input logic circuit. The table lists all possible combinations of logic levels present at inputs A and B along with the corresponding output level X. The first entry in the table shows that when A and B are both at the 0 level, the output x is at the 0 level. The second entry shows that when input B is changed to the 1 state, so that A = 0 and B = 1, the output X becomes a 1. In a similar way, the table shows what happens to the output state for any set of input conditions. © Aviation Australia Truth table - AND logic gate The next table shows samples of truth tables for three- and four-input logic circuits. Again, each table lists all possible combinations of input logic levels on the left, with the resultant logic level for output x on the right. Of course, the actual values for x will depend on the type of logic circuit. Note that there are four table entries for the two-input truth table, eight entries for the three-input truth table and 16 entries for the four-input truth table. The number of input combinations will equal 2N for an N input truth table. Also note that the list of all possible input combinations follows the binary counting sequence, so it is an easy matter to write down all the combinations without missing any. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 124 of 444 CASA Part 66 - Training Materials Only  © Aviation Australia Three and four input truth tables 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 125 of 444 CASA Part 66 - Training Materials Only  Simple Logic Gates Logic Gates A logic gate is an ideal representation of a physical electronic device that implements boolean logic. A combination of logic gates creates a logic circuit. Logic circuits are used in electronic devices, creating integrated circuits and microprocessors. Logic circuits are formed by combining many logic gates. More complex logic circuits are assembled from simpler ones, which in turn are assembled from gates. The building block of all logic circuits is the logic gate. All logic actions, however complicated, can be analyzed and simplified into basic actions that are called OR gates, AND gates and NOT gates. Aviation Australia An integrated circuit is an example of a complex combination of logic circuits 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 126 of 444 CASA Part 66 - Training Materials Only  OR Gates The OR operation is the first of the three basic Boolean operations to be learned. The truth table below shows what happens when two logic inputs, A and B, are combined using the OR operation to produce an output, X. The table shows that the output is a logic 1 for every combination of input levels where one or more inputs are 1. The only case where X is a 0 is when both inputs are 0. © Aviation Australia OR gate (2 input) with truth table The boolean expression for the OR operation is: X = A + B In this expression, the + sign does not stand for ordinary addition; it stands for the OR operation. The OR operation is like ordinary addition except for the case where A and B are both 1; the OR operation produces 1 + 1 = 1, not 1 + 1 = 2. In boolean algebra, 1 is as high as we go, so we can never have a result greater than 1. The same holds true for combining three inputs using the OR operation. Here we have X = A + B + C. If we consider the case where all three inputs are 1, we have X = 1 + 1 + 1 = 1. The expression x = A + B is read as ‘X equals A OR B’, which means X will be 1 when A or B or both are 1. Likewise, the expression X = A + B + C is read as ‘X equals A OR B OR C’, which means X will be 1 when A or B or C or any combination of them are 1. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 127 of 444 CASA Part 66 - Training Materials Only  © Aviation Australia OR gate (3 input) with truth table The following illustration shows alternate equivalent OR logic gates and circuits. Aviation Australia OR gate equivalents 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 128 of 444 CASA Part 66 - Training Materials Only  AND Gates The AND operation is the second basic boolean operation. The truth table below shows what happens when two logic inputs, A and B, are combined using the AND operation to produce output X. The table shows that X is a logic 1 only when both A and B are at the logic 1 level. For any case when one of the inputs is 0, the output is 0. The boolean expression for the AND operation is: X = A. B In this expression the "." sign stands for the boolean AND operation and not the multiplication operation. However, the AND operation on boolean variables operates the same as in ordinary multiplication, as examination of the truth table shows, so we can think of them as being the same. This characteristic can be helpful when evaluating logic expressions that contain AND operations. The expression X = A. B is read as ‘X equals A AND B’, which means that X will be 1 only when A and B are both 1. The sign is usually omitted so that the expression simply becomes X = AB. © Aviation Australia AND gate (2 input) with truth table For the case when there are three AND inputs, we have X = A. B. C = ABC This is read as "X equals A AND B AND C", which means X will be 1 only when A, B and C are all 1. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 129 of 444 CASA Part 66 - Training Materials Only  © Aviation Australia AND gate (3 input) with truth table The following illustration shows alternate equivalent AND logic gates and circuits. Aviation Australia AND gate equivalents 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 130 of 444 CASA Part 66 - Training Materials Only  NOT Gate (Inverter) The NOT operation is unlike the OR and AND operations in that it can be performed on a single input variable. For example, if the variable A is subjected to the NOT operation, the result X can be expressed as follows. x = Ā It is often referred to as an inverter and throughout this lesson the terms 'NOT gate' and 'inverter' are used interchangeably. © Aviation Australia NOT gate (inverter) Where the over-bar represents the NOT operation. This expression is read as ‘X equals NOT A’ or ‘X equals the inverse of A’ or ‘x equals the complement of A’. Each of these is in common usage, and all indicate that the logic value of X = A is opposite to the logic value of A. The truth table clarifies this for the two cases A = 0 and A = 1. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 131 of 444 CASA Part 66 - Training Materials Only  © Aviation Australia Not truth table Combining Gates Multiple input gates can be constructed by placing gates in special configurations. A three-input AND gate may be constructed using two AND gates connected as shown. A three-input OR gate may be constructed using two OR gates connected as shown. Aviation Australia Combining gates 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 132 of 444 CASA Part 66 - Training Materials Only  Logic Circuits Simple AND and OR Circuits Any logic circuit, no matter how complex, can be completely described using the three basic boolean operations because the OR gate, AND gate and NOT circuit are the basic building blocks of digital systems. For example, consider the circuit in the illustration. This circuit has three inputs, A, B and C, and a single output, X. Using the boolean expression for each gate, we can easily determine the expression for the output. Aviation Australia Simple AND and OR combined logic circuit The expression for the AND gate output is written A.B. This AND output is connected as an input to the OR gate along with C, another input. The OR gate operates on its inputs so that its output is the OR sum of the inputs. Thus, we can express the OR output as: X = A ⋅ B + C This final expression could also be written as X = C + A.B since it does not matter which term of the OR sum is written first. Aviation Australia Simple AND and OR combined logic circuit 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 133 of 444 CASA Part 66 - Training Materials Only  Occasionally, there may be confusion as to which operation in an expression is performed first. Thus, the expression A.B + C can be interpreted in two different ways: 1. A.B is ORed with C, or 2. A is ANDed with the term B + C. To avoid this confusion, it will be understood that if an expression contains both AND and OR operations, the AND operations are performed first unless there are parentheses in the expression, in which case the operation inside the parentheses is to be performed first. This is the same rule used in ordinary algebra to determine the order of operations. In the previous circuit, the output X = 1 when the following conditions are met: C is 1 C is 0 and A and B are both 1. When C is 1, A and B don't matter to the output due to the OR gate. However, if C is 0, then A and B produce a 1 from the AND gate and therefore a 1 from the OR gate. Any other conditions result in X = 0. Alternate AND OR Circuit To illustrate further, consider the circuit shown below. The expression for the OR gate output is simply A + B. This output serves as an input to the AND gate along with another input, C. Thus, we express the output of the AND gate as X = (A + B).C. Note the use of parentheses here to indicate that A and B are ORed first, before their OR sum is ANDed with C. Without the parentheses, it would be interpreted incorrectly since A + B.C means A is ORed with the product B.C. Aviation Australia Alternate AND and OR combined logic circuit 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 134 of 444 CASA Part 66 - Training Materials Only  Inverters in Circuits Whenever an inverter is present in a logic-circuit diagram (NOT gate), its output expression is simply equal to the input expression with a bar over it. In the case where an inverted value needs to be expressed in plain text, if the variable is A, it will be referred to as 'A_bar'. Where possible however, a physical bar will be drawn over the variable. The following diagram below shows two examples of circuits using inverters. Aviation Australia Gates with inverters On the left, input A is fed through an inverter, whose output is therefore A_bar. The inverter output is then fed to an OR gate together with B. The equation (for the circuit on the left) is A_bar + B. Note that the bar is over the A alone, indicating that A is first inverted and then ORed with B. On the right, the output of the OR gate is equal to A + B and is fed through an inverter. The inverter output is therefore equal to the complete input expression negated. X equals the inverse of (A OR B). – (lef t) → X = A + B – (right) → X = A + B Note that in the right circuit, the bar covers the entire expression (A + B). This is important because, as will be shown later, the following expressions are NOT equal. – ¯ A + B̄ not equal to A + B e. g. A = 1, B = 0 – – ¯ ¯ ⟹ A + B = 1 + 0 = 1 – – ⟹ A + B = 1 + 0 = 0 The first expression indicates that A is inverted and B is inverted, and the results are then ORed, whereas the second expression indicates that A is ORed with B and then their OR sum is inverted. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 135 of 444 CASA Part 66 - Training Materials Only  Logic Circuit Worked Examples Example 1 Find the outputs of each logic gate and the total output of the logic circuit below. Write each answer using the correct logic syntax. © Aviation Australia Logic circuit example 1 Example 2 Find the outputs of each logic gate and the total output of the logic circuit below. Write each answer using the correct logic syntax. © Aviation Australia Logic circuit example 2 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 136 of 444 CASA Part 66 - Training Materials Only  Compound Logic Gates NOR Gate The symbol for a two-input NOR gate is shown below. It is the same as the OR gate symbol except that it has a small circle on the output. The small circle represents the inversion operation. Thus, the NOR gate operates like an OR gate followed by an inverter. © Aviation Australia NOR gate (2 input) and truth table The truth table shows that the NOR gate output is the exact inverse of the OR gate output for all possible input conditions. An OR gate output goes HIGH when any input is HIGH, and the NOR gate output goes LOW when any input is HIGH. This same operation can be extended to NOR gates with more than two inputs. Aviation Australia NOR gate and NOR gate timing diagram 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 137 of 444 CASA Part 66 - Training Materials Only  Aviation Australia NOR gate circuit equivalents NAND Gate The symbol for a two-input NAND gate is shown in the diagram. It is the same as the AND gate symbol except for the small circle on its output. Once again, this small circle denotes the inversion operation. The output is the same as an AND gate with a bar over all the inputs (shown below). © Aviation Australia NAND gate (2 input) with truth table The NAND operates like an AND gate followed by an inverter (NOT), thus the circuits in the diagram below are equivalent. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 138 of 444 CASA Part 66 - Training Materials Only  Aviation Australia NAND gate is the equivalent to an AND followed by a NOT The truth table in the diagram shows that the NAND gate output is the exact inverse of the AND gate for all possible input conditions. The AND output goes HIGH only when all inputs are HIGH, while the NAND output goes LOW only when all inputs are HIGH. This same characteristic is true of NAND gates having more than two inputs. Aviation Australia NAND timing diagram 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 139 of 444 CASA Part 66 - Training Materials Only  Exclusive-OR (XOR) An exclusive-OR (XOR), in the case of a two input circuit, means that if the input is either A or B it returns 1. If the input is both A and B it returns 0, and if the input is neither A or B it returns 0. Consider the logic circuit in the diagram below. Aviation Australia XOR gate and truth table To reiterate the explanation above, the accompanying truth table shows that X = 1 for only the following two cases: A = 0 and B =1 A = 1 and B = 0 Thus, the output of an XOR produces a HIGH whenever the two inputs are at opposite levels. This exclusive-OR circuit will hereafter be abbreviated to XOR. ¯ X = AB + AB̄ or alternatively ¯ ¯ (A. B) + (A. B) = 1 This combination of logic gates occurs quite often and is very useful in certain applications. In fact, the XOR circuit has been given a simplified symbol of its own, shown in the diagram below. This symbol is assumed to contain all the logic contained in the XOR circuit and therefore has the same logic expression and truth table. This XOR circuit is commonly referred to as an XOR gate, and we consider it another type of logic gate. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 140 of 444 CASA Part 66 - Training Materials Only  © Aviation Australia XOR gate (2 input) and truth table The IEEE/ANSI symbol for an XOR gate is shown below as well as the shorthand logic equation for an XOR. The dependency notation (= 1) inside the block indicates that the output will be active-HIGH only when a single input is HIGH. © Aviation Australia XOR Gate shorthand and IEEE/ANSI symbol (alternate) The ⊕ symbol represents XOR. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 141 of 444 CASA Part 66 - Training Materials Only  Exclusive-NOR (XNOR) The exclusive-NOR circuit (abbreviated XNOR) operates completely opposite to the XOR circuit. The following diagram shows an XNOR circuit and its accompanying truth table. Aviation Australia XNOR gate and truth table The output expression of an XNOR circuit is as follows. – X = AB + AB This indicates along with the truth table that X will be 1 for two cases: A = B = 1 (the AB term) A = B = 0 (the not AB term). The XNOR produces a HIGH output whenever the two inputs are at the same level. It should be apparent that the output of the XNOR circuit is the exact inverse of the output of the XOR circuit. The traditional symbol for an XNOR gate is obtained by simply adding a small circle at the output of the XOR symbol. © Aviation Australia XNOR gate (2 input) and IEEE/ANSI alternative symbol 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 142 of 444 CASA Part 66 - Training Materials Only  The IEEE/ANSI symbol adds the small triangle on the output of the XOR symbol. Both symbols indicate an output that goes to its active-LOW state when only one input is HIGH. The Universal Gates The NOR gate and the NAND gate can be said to be universal gates since combinations of them can be used to accomplish any of the basic operations and can thus produce an inverter, an OR gate or an AND gate. The non-inverting gates do not have this versatility since they cannot produce an invert. Aviation Australia Universal gate 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 143 of 444 CASA Part 66 - Training Materials Only  Buffers If two inverter gates were to be connected together so that the output of one fed into the input of the other, the inverters would cancel each other out. This is a buffer. While this may seem like a pointless thing to do in a theoretical logic circuit, in a real electric logic circuit, it has many practical benefits. It is useful as an impedance-matching device (and operates slightly different depending on the type - voltage buffer or current buffer). In logic circuits, the buffer is a single-input device which has a gain of 1, mirroring the input at the output. The basic emitter follower can be used as a buffer for a voltage source. The common collector amplifier (BJT) is often called an emitter follower since its output is taken from an emitter resistor. Aviation Australia Buffer An op-amp voltage follower can also serve as a voltage buffer. The voltage buffer, also known as a unity gain amplifier (an amplifier with a gain of 1) is one of the simplest possible op-amp circuits with closed-loop feedback. The voltage follower with an ideal op-amp gives simply Vout = Vin, but this turns out to be a very useful service because the input impedance of the op-amp is very high, giving effective isolation of the output from the signal source. You draw very little power from the signal source, thus avoiding ‘loading’ effects. The voltage follower is often used to construct buffers for logic circuits. Aviation Australia OpAmp buffer #1 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 144 of 444 CASA Part 66 - Training Materials Only  Inverting Buffers (Inverter) The inverting buffer is a single-input device which produces the state opposite the input. If the input is high, the output is low, and vice versa. This device is commonly referred to as just an inverter. A transistor switch with a collector resistor can serve as an inverting buffer. When the switch is open, no current flows in the base, so the collector current is cut off. The resistor RC must be small enough to drive the transistor to saturation so that most of the voltage VCC appears across the load. The output is taken below the load resistor and can function as an inverting buffer in digital circuits. Aviation Australia Inverting buffers Aviation Australia OpAmp buffer #2 An op-amp inverting amplifier with a gain of 1 serves as an inverting buffer. For an ideal op-amp, the inverting amplifier gain is given simply by: Vout −Rf = Vin R1 For equal resistors, it has a gain of -1 and is used in digital circuits as an inverting buffer. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 145 of 444 CASA Part 66 - Training Materials Only  Alternate Inverter Symbol The inverter symbol is utilised as required, but a more common method of indicating a signal is inverted is simply using an inversion symbol, O, on the leg of the device. Aviation Australia Inverter symbol IEEE Gate Symbols Together with the American National Standards Institute (ANSI), the Institute of ANSI Electrical and Electronic Engineers (IEEE) has developed a standard set of logic IEEE symbols. The most recent revision of the standard is ANSI/IEEE Std 91-1984, IEEE Standard Graphic Symbols for Logic Functions. It is compatible with standard 617 of the International Electrotechnical Commission (IEC) and must be used in all logic diagrams drawn for the U.S. Department of Defense. These symbols are being used more and more as time progresses. Aviation Australia IEEE symbols 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 146 of 444 CASA Part 66 - Training Materials Only  Fabrication of Gates Gates are fabricated as IC packs in dual, triple or quadruple circuit arrangements. The diagram illustrates a typical presentation of manufacturer's operating data, which in this example relates to a quadruple two-input NAND circuit arrangement contained within a Dual-In-Line (DIL) pack monolithic IC. The numbered squares represent the connecting pins. Aviation Australia Quad two input NAND gates 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 147 of 444 CASA Part 66 - Training Materials Only  Worked Logic Circuit Examples Logic Circuit Example Problems The following section provides some examples that may be worked through to demonstrate and understanding of logic gates, logic circuits and timing diagrams. The following section contains the answers for each example, however it is recommended that the questions are attempted prior to viewing the solutions. Determine the logic operation performed by the following circuits. Each circuit can be simplified into a single logic operation (a single logic gate). © Aviation Australia Write the truth tables and simplify the logic circuits above 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 148 of 444 CASA Part 66 - Training Materials Only  Logic Circuit Example Solutions The truth table and single combined gate solutions for the previous section. © Aviation Australia Simplified logic circuits 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 149 of 444 CASA Part 66 - Training Materials Only  Logic Waveform Example Problems The logic waveforms below are applied to the inputs of both an OR and a XOR gate. Drawn below are the output waveforms you would expect for each. Note that logic level 1 (HIGH) is represented by +5 V, and similarly logic level 0 (LOW) is represented by 0 V. © Aviation Australia Logic waveform 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 150 of 444 CASA Part 66 - Training Materials Only  Logic Waveform Example Solutions When the inputs A and B exit the gates below, these are the expected waveforms. © Aviation Australia When the inputs A and B exit the gates above, these are the expected waveforms Electrical Circuit Logic Examples Aviation Australia Switch representations #1 Many circuits in aircraft may be schematically represented by logic circuits for ease. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 151 of 444 CASA Part 66 - Training Materials Only  Flip-Flops and Latches Flip-Flops The Application of Flip-Flops One of the more interesting things you can do with logic gates is store binary data. Flip-flop circuits are an arrangement of logic gates that will remember an input value. It maintains a state (1 or 0), until it is directed to change its state. Historically, transistor versions of these circuits were common in computers, even after the introduction of integrated circuits, though flip-flops made from logic gates are very common now. The first flip-flop circuit was known differently as multivibrators or trigger circuits. This lesson focuses on flip-flops as they relate to logic circuits and as prerequisite knowledge to further topics in this module. Some of the most common applications of flip-flops are: Counters Registers Frequency Divider circuits Data transfer Flip-Flops In electronics, a flip-flop (or latch) is a circuit that has two stable states and can be used to store state information, it is known as a bistable multivibrator. As discussed, the basic function of a flip-flop is to store a single bit of binary data. The application of a pulse at one input, causes it to 'flip' into one of its two stable states and remain latched in that state. A pulse at the other input causes it to 'flop' into the other state. The two output terminals are usually designated Q and Q bar (a bar above the Q), remembering that the bar means to invert in logic circuits, so it can also be understood as 'Not Q'. The in-text descriptions of 'Not Q' will be referenced using Q' to denote the inversion. © Aviation Australia SR flip-flop block diagram 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 152 of 444 CASA Part 66 - Training Materials Only  A flip-flop is made up of a latch circuit. For example, the S-R flip-flop makes use of the S-R latch logic circuit. An S-R flip-flop typically has a clock to complete the flip-flop device, however initially, our explanations of the S-R flip-flop will ignore the clock. The types of flip-flops circuits we are going to discuss are the: Set-Reset (SR) flip-flop Master-Slave (JK) flip-flop Data (D) flip-flop Toggle (T) flip-flop. NAND Gate S-R Flip-Flops A simple type of flip-flop is the S-R (Set-Reset) Flip-Flop (or S-R Latch). It can be constructed using two NAND gates. Aviation Australia SR Flip-flop with two NAND gates The fundamental operation of flip-flops may be understood using the S-R flip-flop diagram above. Where S is Set, R is Reset, Q is output gate 1 and Q' is output gate 2. This circuit is also known as an S-R latch. Where the outputs "latch" to either 1 or 0 based on a pulsed input. Keep in mind this is a NAND gate version, other gates can be used to create latch circuits that operate the same way. Invalid State The term invalid (or indeterminate) noted in some cases means that for the inputs shown, the flip- flops may switch to reverse the output states or they may remain in an existing condition; in other words, they get into a state of ‘limbo’ and so produce undesirable operation. S-R Latch Operation (NAND) Before any values are applied to the inputs, the latch is in an invalid state. The latch is not made to operate in this state. Referring to the truth table above, it can be seen that this S-R latch is at rest when both inputs are high. When both inputs are high, the latch remains in the last state it was told to switch to. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 153 of 444 CASA Part 66 - Training Materials Only  Assume that power is applied and the following initial values are met: S and R inputs are connected (and current flows through the logic gate) and they are logic 0 and logic 1, respectively (a high is provided to the R input). The outputs of gates 1 and 2 (Q and Q') are initially logic 0 and logic 1 respectively. What will happen inside this latch is, it will cause the outputs to flip, so Q will become 1 and Q' will become 0. How the 'flip' happens: 1. In this case, before the flip-flop has a chance to change, the S and R inputs are connected so that S is a logic 0 (low) and R is a logic 1 (high). Remembering that the outputs at this point in time are Q = 0 and Q' = 1. 2. Firstly (looking from top to bottom), the 0 and 1 entering the upper NAND gate produce a logic 1 at the output. 3. The 1 at the output of the upper NAND gate applies a 1 to the upper input of the lower NAND gate. Since R is already 1 and this new input becomes 1, the two high values on the lower NAND gate produces a 0 at the output. 4. The logic 0 value from the output of the lower NAND gate when applied to the input of the upper NAND gate does not affect the upper gates output and it therefore remains at 1. 5. This now leaves the gates output both flipped, the Q output is logic 1 and Q' is logic 0. Aviation Australia The flip (step-by-step) 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 154 of 444 CASA Part 66 - Training Materials Only  Under normal conditions, the outputs will be the inverse of each other. If S and R inputs are now reversed, flip-flop output will cycle. It is worth noting however, that this flip started in an invalid state - therefore the output was subject to 'race conditions' and is unpredictable. Once the latch is in a known state (either set or reset), the flip-flop can function as intended. Shown below is a diagram with the inputs changed to both 1s. Referencing the truth table, this has no effect on the latch as expected. Now the S and R inputs are reversed, S at 1 and R at 0. The 'flop' occurs (shown in the bottom part of the diagram below). 1. The 1 and the 0 on the lower NAND gate produce a 1 at the Q' output. 2. The 1 at the output of the lower NAND gate is applied to input of upper NAND gate. 3. These two 1’s now on the upper NAND gate produce a 0 at the Q output. 4. The 0 at the output of the upper NAND gate is applied to the input of the lower NAND gate, but the output unaffected and remains at 1. Aviation Australia The flop (step-by-step) 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 155 of 444 CASA Part 66 - Training Materials Only  Regular Operation You may have noticed that the set and reset inputs when high, actually do the opposite of their named role. This is because the S-R flip-flop is at rest in the high position, and when the set input is pulsed low, the latch is set. When the reset input is pulsed low, the latch is reset. Therefore, the Set (S) and Reset (R) inputs are normally resting in the HIGH (1) state. Then an input is pulsed low whenever we want to change the latch outputs. Summary A flip-flop has a basic function of storing a single bit of binary data. It is so called because the application of a suitable pulse at one input causes it to ‘flip’ into one of its two stable states and remain latched in that state until a pulse at a second input causes it to ‘flop' into the other state (as shown previously). The device has two output terminals Q and Q', and the logic states of these terminals are referred to respectively as the normal and the complement. When the normal state is logic 1 and the complement is logic 0, the device is said to be set, and conversely it is said to be reset when the normal state is logic 0 and the complement is logic 1. The latching characteristic has some very important uses (computer memory). Aviation Australia S-R flip-flop (NAND gate) switching 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 156 of 444 CASA Part 66 - Training Materials Only  NOR Gate S-R Flip-Flops The most basic flip-flop circuit can be constructed from either two NAND gates, as described in previous slides, or two NOR gates. This latch regular operation is reversed. Aviation Australia NOR gate flip-flop Aviation Australia S-R flip-flop (NOR gate) operation 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 157 of 444 CASA Part 66 - Training Materials Only  Setting the S-R Latch (NOR) When the Set input is momentarily pulsed low and Clear is kept high, Q will latch to a high or 1 – high on Q keeps Q' at 0. When ‘Set’ returns to high – Q' unaffected: remains at 0 – latch remains ‘set’. If ‘Set’ selected low again – Q' output is still unaffected – latch state remains ‘set’. Low pulse on ‘Set’ input will always cause latch to end up in Q = 1 state – setting the latch or flip-flop. Clearing the S-R Latch (NOR) To clear the latch, 'Reset' is pulsed 'high' while 'Set' remains 'low'. When 'Reset' is pulsed high, Q goes low and the two lows on lower gate latches Q' at 1. When 'Reset' returns to low, Q is held at 0 due to 1 applied to the upper gate input from Q' output and the latch remains in 'Reset' state. If 'Reset' is selected high again, Q output is unaffected – latch remains in 'reset' state. High pulse on 'Reset' input will always cause latch to end up in Q = 0 state and reset the latch or flip- flop. Alternate Representations NAND gate flip-flops typically have S and R held high and will trigger the flip-flop when pulsed low – the inputs are active-low. When Set is pulsed low, Q = 1, and when Reset is pulsed low, Q = 0. NOR gate flip-flops typically have S and R held low and will trigger the flip-flop when pulsed high – the inputs are active-high. When Set is pulsed high, Q = 1, and when Reset is pulsed high, Q = 0. Thus, the Set and Reset (or Clear) inputs are reversed between the NAND gate and NOR gate configurations. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 158 of 444 CASA Part 66 - Training Materials Only  Flip-Flop Invalid and Initial States As introduced previously, the flip-flop can enter an invalid state. This is when the inputs cause the outputs to be either all high or all low. This occurs during either simultaneous setting or resetting and on start-up of the flip-flop device. Simultaneous Setting and Resetting The last case to consider is the case in which the Set and Reset inputs are simultaneously pulsed low. This will produce high levels at both NAND outputs so that. Clearly this is an undesired condition since the two outputs are supposed to be inverses of each other. Furthermore, when the Set and Reset inputs return high, the resulting output state will depend on which input returns high first. Simultaneous transitions back to the 1 state will produce unpredictable results. For these reasons, the Set = Reset = 0 condition is not used. The term indeterminate (or invalid) noted in some cases means that for the inputs shown, the flip- flops may switch to reverse the output states or they may remain in an existing condition; in other words, they get into a state of ‘limbo’ and so produce undesirable operation, where both outputs are high or both outputs are low. If the inputs are returned from the invalid state to 0 or 1 (depending on which type of gate we are referring to) simultaneously, the resulting output state is unpredictable. This input condition should not be used. Flip-Flop State on Power-Up When power is applied to a circuit, it is not possible to predict the starting state of a flip-flop’s output if its Set and Reset inputs are in their inactive state (e.g. S = R = 1 for a NAND latch, S = R = 0 for a NOR latch). There is just as much chance that the starting state will be Q = 0 as Q = 1. It will depend on factors such as internal propagation delays, parasitic capacitance and external loading. If a latch or flip-flop must start off in a state to ensure the proper operation of a circuit, then it must be placed in that state by momentarily activating the Set or Reset input at the start of the circuit’s operation. This is often achieved by applying a pulse to the appropriate input. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 159 of 444 CASA Part 66 - Training Materials Only  S-R Flip-Flop Practical Usage It is virtually impossible to obtain a ‘clean’ voltage transition from a mechanical switch because of the phenomenon of contact bounce. The action of moving the switch from contact position 1 to 2 produces several output voltage transitions as the switch bounces (makes and breaks contact with contact 2 several times) before coming to rest on contact 2. Aviation Australia S-R flip-flops as a de-bounce circuits The multiple transitions on the output signal generally last no longer than a few milliseconds, but they are unacceptable in many applications. A NAND latch can be used to prevent the presence of switch bounce from affecting the output. For such applications as counters and shift registers, flip-flops are operated synchronously with a clocked or strobed pulse train derived from an astable or free-running multivibrator, or a crystal oscillator, and applied to a third input. They consist of NAND or NOR gates and are fabricated as digital ICs. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 160 of 444 CASA Part 66 - Training Materials Only  Clocked Flip-Flops Clock Signals Digital systems can operate either asynchronously or synchronously. In asynchronous systems, the outputs of logic circuits can change state anytime one or more of the inputs change. An asynchronous system is generally more difficult to design and troubleshoot than a synchronous system. In synchronous systems, the exact times at which any output can change states are determined by a signal commonly called the clock. This clock signal is generally a rectangular pulse train or a square wave. Aviation Australia Clock signal used in flip-flops The clock signal is distributed to all parts of the system, and most (if not all) of the system outputs can change state only when the clock makes a transition. The transitions (also called edges) are illustrated on the slide. When the clock changes from a 0 to a 1, this is called the positive-going transition (PGT); when the clock goes from 1 to 0, this is the negative-going transition (NGT). We will use the abbreviations PGT and NGT since these terms appear so often throughout the text. Most digital systems are principally synchronous (although there are always some asynchronous parts) since synchronous circuits are easier to design and troubleshoot. They are easier to troubleshoot because the circuit outputs can change only at specific instants of time. In other words, almost everything is synchronised to the clock-signal transitions. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 161 of 444 CASA Part 66 - Training Materials Only  Triggering or Clock Pulsing There are two basic categories of clocked flip-flops. They are: Level-triggered Edge-triggered. Level-Triggering When a flip-flop is designed to be clocked by a logic HIGH 1 or logic LOW 0 level, it is said to be level- triggered. If the flip-flop is designed to be clocked by a logic HIGH, the clock line is drawn as shown in the slide on the left. Note these symbols. This is called an active-HIGH input. If the flip-flop is designed to be clocked by a logic LOW, the clock line is drawn with the addition of an inversion bubble. This is called an active-LOW input. Aviation Australia Level triggered flip-flops For an active-HIGH level-triggered flip-flop, whenever the clock line into the flip-flop is HIGH, any data at its inputs will be processed by the flip-flop and its outputs will change state accordingly. Whenever the clock pulse is LOW, the data will remain at the inputs and the outputs of the flip-flop will not change. Conversely, with an active-LOW level-triggered flip-flop, whenever the clock line into a flip-flop is LOW, any data at its inputs will be processed by the flip-flop and its outputs will change state accordingly. Whenever the clock pulse is HIGH, the data will remain at the inputs and the outputs of the flip-flop will remain as they were. The disadvantage of the level-triggered clocked S-R flip-flop is that if there are any changes in the R and S inputs while a HIGH clock signal is present, the Q output will change. To overcome the problem of Q changing during a clock pulse, we use an edge-triggered flip-flop. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 162 of 444 CASA Part 66 - Training Materials Only  Edge-Triggering The illustration shows how the CLK signal is generated for edge-triggered flip-flops that trigger on a PGT. The inverter produces a delay of a few nanoseconds so that the transitions occur a little bit after those of CLK. The AND gate produces an output spike that is HIGH only for the few nanoseconds when CLK and are both HIGH. The result is a narrow pulse at CLK*, which occurs on the PGT of CLK. Aviation Australia Edge triggered SC flip-flop The right circuit (of the circuit showing the internal workings of a flip-flop) produces CLK on the NGT of CLK for NGT-triggered flip-flops. Since the CLK* signal is HIGH for only a few nanoseconds, Q is affected by the levels at S and R for only a short time during and after the occurrence of the active edge of CLK. This is what gives the flip-flop its edge-triggered property. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 163 of 444 CASA Part 66 - Training Materials Only  Clocked Flip-flops Several types of clocked flip-flops are used in a wide range of applications. Before we begin our study of the different clocked flip-flops, we will describe the principal ideas that are common to all of them. As previously explain, a clock signal is typically included to complete the flip-flop device (otherwise it is simply a latch logic circuit). Another way to think of this is; clocked flip-flops are practical applications of logic latch circuits. Aviation Australia Flip-flop clocking types Clocked flip-flops have an input that is typically labelled CLK, CK or CP. In many clocked flip-flops, the CLK input is edge-triggered, which means it is activated by a signal transition; this is indicated by the presence of a small triangle on the CLK input. This contrasts with the latches, which are level- triggered. The illustration above (A & C) shows a flip-flop with a small triangle on its CLK input to indicate that this input is activated only when a PGT occurs; no other part of the input pulse will influence the CLK input. In the right illustration, the flip-flop symbol has a bubble as well as a triangle on its CLK input. This signifies that the CLK input is activated only when an NGT occurs; no other part of the input pulse will influence the CLK input. Clocked flip-flops also have one or more control inputs that can have various names, depending on their operation. The control inputs will have no effect on Q until the active clock transition occurs. In other words, their effect is synchronised with the signal applied to CLK. For this reason, they are called synchronous control inputs. For example, the control inputs of the left flip-flop will have no effect on Q until the PGT of the clock signal occurs. Likewise, the control inputs on the right flip-flop will have no effect until the NGT clock signal occurs. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 164 of 444 CASA Part 66 - Training Materials Only  In summary, we can say that the control inputs get the flip-flop outputs ready to change, while the active transition at the CLK input triggers the change. The control inputs control the ‘what’ (i.e. what state the output will go to); the CLK input determines the ‘when’. Setup and Hold Times Two timing requirements must be met if a clocked flip-flop is to respond reliably to its control inputs when the active CLK transition occurs. These requirements are illustrated in the slide for a flip-flop that triggers on a PGT. Aviation Australia Set up and hold times Setup time (tS) is the time interval immediately preceding the active transition of the CLK signal during which the control input must be maintained at the proper level. IC manufacturers usually specify the minimum allowable setup time tS (min). If this time requirement is not met, the flip-flop may not respond reliably when the clock edge occurs. The hold time (tH) is the time interval immediately following the active transition of the CLK signal during which the synchronous control input must be maintained at the proper level. IC manufacturers usually specify the minimum acceptable value of hold time tH (min). If this requirement is not met, the flip-flop will not trigger reliably. Control inputs must be held stable for a time tS prior to active clock transition and for a time tH after the active block transition. Thus, to ensure that a clocked flip-flop will respond properly when the active clock transition occurs, the control inputs must be stable (unchanging) for at least a time interval equal to tS (min) prior to the clock transition, and for at least a time interval equal to tH (min) after the clock transition. IC flip-flops will have minimum allowable tS and tH values in the nanosecond range. Setup times are usually in the range of 5 to 50 ns, whereas hold times are generally from 0 to 10 ns. Notice that these times are measured between the 50% points on the transitions. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 165 of 444 CASA Part 66 - Training Materials Only  These timing requirements are very important in synchronous systems because, as we will see, there will be many situations where the synchronous control inputs to a flip-flop are changing at approximately the same time as the CLK input. The Clocked S-R Flip-Flop The illustration in the slide shows the logic symbol for a clocked S-R flip-flop triggered by PGT (transition from 0 to 1). The S and R inputs control the state of the flip-flop in the same manner as described earlier for the NOR gate latch, but the flip-flop does not respond to these inputs until the occurrence of the PGT of the clock signal. Aviation Australia Clocked S-R flip-flop (positive edge-triggered) and truth table The truth table shows how the flip-flop output responds to CLK input PGT for the various combinations of S and R inputs. This truth table uses some new nomenclature. The up arrow (↑) indicates that a PGT is required at CLK, and the label QO indicates the level at Q prior to the PGT. This nomenclature is often used by IC manufacturers in their IC data manuals. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 166 of 444 CASA Part 66 - Training Materials Only  The waveforms illustrate the operation of the clocked S-C flip-flop. If we assume that the setup and hold time requirements are being met in all cases, we can analyse these waveforms as follows: Initially all inputs are 0 and the Q output is assumed to be 0; that is, Q = 0. When the PGT of the first clock pulse occurs (point a), the S and R inputs are both 0, so the flip- flop is not affected and remains in the Q = 0 state (i.e. Q =QO). At PGT of the second clock pulse (point c), S input is now high, with R still low. Thus, the flip- flop sets to the 1 state at the rising edge of this clock pulse. When the third clock pulse makes its positive transition (point e), it finds that S = 0 and R = 1, which causes the flip-flop to clear to the 0 state. The fourth pulse sets the flip-flop once again to the Q = 1 state (point g) because S = 1 and R = 0 when the positive edge occurs. The fifth pulse also finds that S = 1 and R = 0 when it makes its PGT. However, Q is already high, so it remains in that state. The S = R = 1 condition should not be used because it results in an ambiguous condition. Aviation Australia Timing diagram 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 167 of 444 CASA Part 66 - Training Materials Only  It should be noted from these waveforms that the flip-flop is not affected by the NGTs of the clock pulses. Also, note that the S and R levels have no effect on the flip-flop except on the occurrence of a PGT of the clock signal. The S and R inputs are synchronous control inputs; they control which state the flip-flop will go to when the clock pulse occurs; the CLK input is the trigger input that causes the flip-flop to change states according to what the S and R inputs are when the active clock transition occurs. The illustration below shows the symbol and the truth table for a clocked S-R flip-flop that triggers on the NGT at its CLK input. Aviation Australia Flip flop NGT triggered The small circle and triangle on the CLK input indicate that this flip-flop will trigger only when the CLK input goes from 1 to 0. This flip-flop operates in the same manner as the positive-edge flip-flop, except that the output can change states only on the falling edge of the clock pulses. Both positive-edge- and negative-edge- triggering flip-flops are used in digital systems. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 168 of 444 CASA Part 66 - Training Materials Only  Internal Circuitry of the Edge-Triggered S-R Flip-Flop A detailed analysis of the internal circuitry of a clocked flip-flop is not necessary since all types are readily available as ICs. Although our main interest is in the flip-flop’s external operation, our understanding of this external operation can be aided by looking at a simplified version of the flip- flop’s internal circuitry. The diagram shows this for an edge-triggered SR flip-flop. The circuit contains three sections: 1. A basic NAND latch formed by NAND-3 and NAND-4 2. A pulse-steering circuit formed by NAND-1 and NAND-2 3. An edge-detector circuit. The edge detector produces a narrow positive-going spike (CLK*) that occurs coincident with the active transition of the CLK input pulse. The pulse-steering circuit ‘steers’ the spike through to the Set or Reset input of the latch in accordance with the levels present at S and R. For example, with S = 1 and R = 0, the CLK* signal is inverted and passed through NAND-1 to produce a LOW pulse at the Set input of the latch that sets Q = 1. With S = 0, R = 1, the CLK* signal is inverted and passed through NAND-2 to produce a low pulse at the Reset input of the latch that resets Q = 0. Aviation Australia Clocked SR flip-flop Note: The SET and RESET may be referenced as SET or RESET to denote the bar. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 169 of 444 CASA Part 66 - Training Materials Only  The Clocked J-K Flip-Flop The illustration shows a clocked J-K flip-flop that is triggered by the positive-going edge of the clock signal. The J and K inputs control the state of the flip-flop in the same ways the S and C inputs do for the clocked S-C flip-flop, except for one major difference: the J = K = 1 condition (invalid in an S-R flip- flop) does not result in an ambiguous output. For this 1, 1 condition, the flip-flop will always go to its opposite state upon the positive transition of the clock signal. Aviation Australia Clocked JK flip-flop This is called the toggle mode of operation. In this mode, if both J and K are left HIGH, the flip-flop will change states (toggle) for each PGT of the clock. The truth table summarises how the J-K flip-flop responds for each combination of J and K. Notice that the truth table is the same as for the clocked S-R flip-flop, except for the J = K = 1 condition. This condition results in Q = Q0 , which means the new value of Q will be the inverse of the value it had prior to the PGT; this is the toggle operation. Aviation Australia Timing diagram Waveforms explaining operation of this flip-flop are illustrated above. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 170 of 444 CASA Part 66 - Training Materials Only  Initially all inputs are 0, and the Q output is assumed to be 1; that is, Q0 = 1. When the positive-going edge of the first clock pulse occurs (point a), J = 0 and K = 1. The flip- flop will be cleared to the Q0 = 0 state. The second clock pulse finds J = K = 1 (point c). The flip-flop will toggle to its opposite state, Q = 1. At point e on the clock waveform, J = K = 0, so the flip-flop does not change states on this transition. At point g, J = 1 and K = 0. This is the condition that sets Q to the 1 state. However, it is already 1, so it will remain there. At point i, J = K = 1, so the flip-flop toggles to its opposite state. The same thing occurs at point k. Note from these waveforms that the flip-flop is not affected by the negative-going edge of the clock pulses. Also, the J and K input levels have no effect except on the occurrence of the PGT of the clock signal. The J and K inputs by themselves cannot cause the flip-flop to change states. The symbol for a clocked J-K flip-flop that triggers on the negative-going clock-signal transitions includes the small inversion circle on the CLK input. This indicates that the flip-flop will trigger when the CLK input goes from 1 to 0. This flip-flop operates in the same manner as the positive-edge flip- flop in the diagram, except that the output can change states only on negative-going clock-signal transitions (points b, d, f, h and j). Both polarities of edge-triggered J-K flip-flops are in common usage. It is often not necessary to include the NOT Q output in a timing diagram, as it is the complement of the Q output. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 171 of 444 CASA Part 66 - Training Materials Only  Internal Circuitry of the Edge-Triggered J-K Flip-Flop A simplified version of the internal circuitry of an edge-triggered J-K flip-flop is shown below. It contains the same three sections as the edge-triggered S-R flip-flop. In fact, the only difference between the two circuits is that the Q and Q' outputs are fed back to the pulse-steering NAND gates. This feedback connection is what gives the J-K flip-flop its toggle operation for the J=K=1 condition Aviation Australia Edge-triggered JK flip-flop Let’s examine this toggle condition more closely. Assume that J = K = 1 and that Q is sitting in the LOW state when a CLK pulse occurs. With Q = 0 and Q' = 1, NAND gate 1 will steer CLK* (inverted – low pulse clocks NAND gate 3) to the SET' input of the NAND latch (gate 3) to produce Q = 1. The 1 on Q will be felt at the input to NAND 4, setting Q' to 0. If we assume that Q is HIGH when a CLK pulse occurs (J = K = 1), NAND gate 2 will steer CLK* (inverted) to the RESET' input of the latch to produce Q = 0. The 1 on Q' will be felt at the input to NAND 3, setting Q to 0 – the flip-flop is ‘toggled’ again. Thus, Q always ends up in the opposite state. For the toggle operation to work as described above, the CLK* pulse must be very narrow. It must return to 0 before the Q and Q' outputs toggle to their new values; otherwise, the new values of Q and Q' will cause the CLK pulse to toggle the latch outputs again. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 172 of 444 CASA Part 66 - Training Materials Only  Clocked D Type Flip-Flop The illustration shows the symbol and the truth table for a clocked D flip-flop that triggers on a PGT. Unlike the SR and J-K flip-flops, this flip-flop has only one synchronous control input, D, which stands for data. The operation of the D flip-flop is very simple: Q will go to the same state that is present on the D input when a PGT occurs at CLK. In other words, the level present at D will be stored in the flip- flop at the instant the PGT occurs. Aviation Australia Clocked D type flip-flop and timing waveform The waveforms illustrate D flip-flop operation. Assume that Q is initially HIGH. When the first PGT occurs at point a, the D input is LOW; thus, Q will go to the 0 state. Even though the D input level changes between points a and b, it has no effect on Q; Q is storing the LOW that was on D at point a. When the PGT at b occurs, Q goes HIGH since D is HIGH at that time. Q stores this HIGH until the PGT at point c causes Q to go LOW, since D is LOW at that time. In a similar manner, the Q output takes on the levels present at D when the PGTs occur at points d, e, f and g. Note that Q stays HIGH at point e because D is still HIGH. Again, it is important to remember that Q can change only when a PGT occurs. The D input has no effect between PGTs. A negative-edge-triggered D flip-flop operates in the same way just described, except that Q takes on the value of D when an NGT occurs at CLK. The symbol for the D flip-flop that triggers on NGTs includes a bubble on the CLK input. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 173 of 444 CASA Part 66 - Training Materials Only  Implementation of the D Flip-Flop An edge-triggered D flip-flop is easily implemented by adding a single inverter to the edge-triggered J-K flip-flop as shown previously. If you try both values of D, you should see that Q takes on the level present at D when a PGT occurs. The same can be done to convert an S-C flip-flop to a D flip-flop. An edge-triggered D flip-flop is easily implemented by adding a single inverter to the edge-triggered J-K flip-flop. If you try both values of D, you should see that Q takes on the level present at D when a PGT occurs. The same can be done to convert an S-C flip-flop to a D flip-flop. Aviation Australia Clocked D type flip-flop 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 174 of 444 CASA Part 66 - Training Materials Only  Parallel Data Transfer At this point, you may well be wondering about the usefulness of the D flip-flop since it appears that the Q output is the same as the D input. Not quite; remember, Q takes on the value of D only at certain time instances, so it is not identical to D. Aviation Australia Parallel transfer using D flip-flops In most applications of the D flip-flop, the Q output must take on the value at its D input only at precisely defined times. One example of this is illustrated in the slide. Outputs X, Y and Z from a logic circuit are to be transferred to flip-flops Q1, Q2 and Q3 for storage. Using the D flip-flops, the levels present at X, Y and Z will be transferred to Q1, Q2 and Q3, respectively, upon application of a TRANSFER pulse to the common CLK inputs. The flip-flops can store these values for subsequent processing. This is an example of parallel transfer of binary data; the three bits X, Y and Z are all transferred simultaneously. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 175 of 444 CASA Part 66 - Training Materials Only  D Latch The edge-triggered D flip-flop uses an edge-detector circuit to ensure that the output will respond to the D input only when the active transition of the clock occurs. If this edge detector is not used, the resultant circuit operates somewhat differently. It is called a D latch and has the arrangement shown in the diagram. The logic symbol for the D latch is shown in the slide. Note that even though the EN input operates much like the CLK input of an edge-triggered flip-flop, there is no small triangle on the EN input. This is because the small triangle symbol is used strictly for inputs that can cause an output change only when a transition occurs. The D latch is not edge-triggered. The circuit contains the NAND latch and the steering NAND gates 1 and 2 without the edge-detector circuit. The common input to the steering gates is called an enable input (abbreviated EN) rather than a clock input because its effect on the Q and outputs is not restricted to occurring only on its transitions. Aviation Australia D latch The operation of the D latch is described as follows: When EN is HIGH, the D input will produce a LOW at either the or inputs of the NAND latch to cause Q to become the same level as D. If D changes while EN is HIGH, Q will follow the changes exactly. In other words, while EN = 1, the Q output will look exactly like D; in this mode, the D latch is said to be ‘transparent’. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 176 of 444 CASA Part 66 - Training Materials Only  When EN goes LOW, the D input is inhibited from affecting the NAND latch since the outputs of both steering gates are held HIGH. Thus, the Q and outputs will stay at whatever level they had just before EN went LOW. In other words, the outputs are ‘latched’ to their current level and cannot change while EN is LOW even if D changes. This operation is summarised in the truth table. Prior to time T1, EN is LOW, so that Q is latched at its current 0 level and cannot change even though D is changing. During the interval T1 to T2, EN is HIGH so that Q will follow the signal present at D. Thus, Q goes HIGH at T1 and stays there since D is not changing. When EN returns LOW at T2, Q will latch at the HIGH level that it has at T2 and remain there while EN is LOW. At T3, when EN goes HIGH again, Q will follow the changes in the D input until T4, when EN returns LOW. During the interval T3 to T4, the D latch is ‘transparent’ since the variations in D go through to the output Q. At T4, when EN goes LOW, Q will latch at the 0 level since that is its level at T4. After T4, the variations in D will have no effect on Q since it is latched (i.e. EN = 0). © Aviation Australia D latch timing diagram 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 177 of 444 CASA Part 66 - Training Materials Only  Asynchronous Inputs For the clocked flip-flops that we have been studying, the S, R, J, K and D inputs have been referred to as control inputs. These inputs are also called synchronous inputs because their effect on the flip-flop output is synchronised with the CLK input. The synchronous control inputs must be used in conjunction with a clock signal to trigger the flip-flop. Most clocked flip-flops also have one or more asynchronous inputs which operate independently of the synchronous inputs and clock input. These asynchronous inputs can be used to set the flip-flop to the 1 state or clear the flip-flop to the 0 state at any time, regardless of the conditions at the other inputs. Stated another way, the asynchronous inputs are override inputs, which can be used to override all the other inputs to place the flip-flop in one state or the other. Aviation Australia Asynchronous inputs The illustration below shows a J-K flip-flop with two asynchronous inputs designated as Preset and Clear. These are active-LOW inputs as indicated by the bubbles on the flip-flop symbol. The accompanying truth table summarises how they affect the flip-flop output. Aviation Australia JK with PRESET and CLEAR inputs 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 178 of 444 CASA Part 66 - Training Materials Only  PRESET' = CLEAR' = 1 The asynchronous inputs are inactive, and the FF is free to respond to the J, K, and CLK inputs; in other words, the clocked operation can take place. PRESET' = 0 and CLEAR' = 1 The PRESET is activated and Q is immediately set to 1 no matter what conditions are present at the J, K, and CLK inputs. The CLK input cannot affect the FF while PRESET = 0. PRESET' = 1 and CLEAR' = 0 The (CLEAR) ̅ is activated and Q is immediately cleared to 0 independent of the conditions on the J, K, or CLK inputs. The CLK input has no effect while (CLEAR) ̅ = 0. PRESET' = CLEAR' = 0 This condition should not he used since it can result in an ambiguous response. It is important to realise that these asynchronous inputs respond to DC levels. This means if a constant 0 is held on the PRESET' input, the flip-flop will remain in the Q = 1 state regardless of what is occurring at the other inputs. Similarly, a constant LOW on the CLEAR' input holds the flip-flop in the Q = 0 state. Thus, the asynchronous inputs can be used to hold the flip-flop in a state for any desired interval. Most often, however, the asynchronous inputs are used to set or clear the flip-flop to the desired state by application of a momentary pulse. Many clocked flip-flops that are available as ICs will have both asynchronous inputs; some will have only the Clear input. Some flip-flops will have asynchronous inputs that are active-HIGH rather than active-LOW. For these flip-flops, the flip-flop symbol would not have a bubble on the asynchronous inputs. The J and K inputs are shown tied HIGH in this example. Determine the Q output in response to the input waveforms shown. Assume that Q is initially HIGH. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 179 of 444 CASA Part 66 - Training Materials Only  Aviation Australia Timing diagram Designations for Asynchronous Inputs IC manufacturers have not agreed on what nomenclature should be used for these asynchronous inputs. The most common designations are PRE (short for Preset) and CLR (short for Clear). The designations SD (direct Set) and RD (direct Reset) are also used. When asynchronous inputs are active-LOW, as they generally are, the overbar is typically used to indicate their active-LOW status, that is, PRE' and CLR'. Although most IC flip-flops have at least one or more asynchronous inputs, there are some circuit applications where they are not used. In such cases, they are held permanently at their inactive level. Often, unused asynchronous inputs are not shown in logic diagrams. In this case, it is assumed that they are permanently connected to their inactive logic level. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 180 of 444 CASA Part 66 - Training Materials Only  IEEE/ANSI Symbols The illustration shows the IEEE/ANSI symbol for a negative-edge-triggered J-K flip-flop with asynchronous inputs. Aviation Australia IEEE symbol Note the right triangle on the CLK input to indicate that it is activated by an NGT. Recall that in the IEEE/ANSI symbols, a right triangle has the same meanings as the small bubble in the traditional symbols. Also note that the clock input is labelled C inside the rectangle. IEEE/ANSI always uses a C to denote any input that controls when other inputs will affect the output. The PRE and CLR inputs are active-LOW as indicated by the right triangles on these inputs. IEEE/ASNI also uses the labels S and R inside the rectangle to denote the asynchronous SET and RESET operations, which are the same as PRESET and CLEAR respectively. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 181 of 444 CASA Part 66 - Training Materials Only  Aviation Australia 74LS112 The illustration shows the IEEE/ANSI logic symbol for an IC that is part of the 74LS series of TTL devices. This same IC symbol applies to the CMOS 74HC112. The 74L5112 is a dual negative-edge-triggered J-K flip-flop with Preset and Clear capabilities. It contains two J-K flip-flops like the one symbolised on the left. Note how the inputs and outputs are numbered. Also note that the input labels inside the rectangles are shown only for the top flip-flop. It is understood that the inputs to the bottom flip-flop are in the same arrangement as the top one. This same IC symbol applies to the CMOS 74HC112. On the left below is the IEEE/ANSI symbol for a positive-edge-triggered D flip-flop with asynchronous inputs. There is no right triangle on the clock input since this flip-flop is clocked by PGTs. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 182 of 444 CASA Part 66 - Training Materials Only  Aviation Australia 74HC175 On the right above is the IEEE/ANSI symbol for a 74HC175 IC, which contains four D flip-flops that share a common CLK input and a common CLR input. The flip-flops do not have a PRE' input. This symbol contains a separate rectangle to represent each flip-flop and a special common-control block, which is the notched rectangle on top. The common-control block is used whenever an IC has one or more inputs that are common to more than one of the circuits on the chip. For the 74HC175, the CLK and CLR inputs are common to all four of the D flip-flops on the IC. This means a PGT on CLK will cause each Q output to take on the level present at its D input; it also means a LOW on CLR will clear all Q outputs to the LOW state. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 183 of 444 CASA Part 66 - Training Materials Only  Flip-Flop Timing Considerations Flip-Flop Parameters Manufacturers of IC flip-flops will specify several important timing parameters and characteristics that must be considered before a flip-flop is used in any circuit application. We will describe the most important of these and then give some examples of specific IC flip-flops from the TL and CMOS logic families. Aviation Australia D-type edge-triggered flip-flop datasheet snippet This datasheet snippet shows an example of a manufacturers recommended operating conditions of a flip-flop device. Setup and Hold Times Aviation Australia Setup and hold times 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 184 of 444 CASA Part 66 - Training Materials Only  The setup and hold times, which have already been discussed, represent requirements that must be met for reliable flip-flop triggering. The manufacturer’s IC data sheet will always specify the minimum values of tS and tH. Setup time (tS) – time interval immediately preceding the active transition of the CLK signal. Control input must be maintained at the proper level for this period. Hold time (tH) – time interval immediately following the active transition of the CLK signal. Control input must be maintained at the proper level for this period. Control inputs must be held stable for a time (tS) prior to active clock transition and for a time (tH) after the active clock transmission, measured in nanoseconds. Times are measured between the 50% points on the transitions. Propagation Delays Aviation Australia Propagation delay Whenever a signal is to change the state of a flip-flop’s output, there is a delay from the time the signal is applied to the time when the output makes its change. The diagram above illustrates the propagation delays that occur in response to a positive transition on the CLK input. Note that these delays are measured between the 50% points on the input and output waveforms. The same types of delays occur in response to signals on a flip-flop’s asynchronous inputs (PRESET and CLEAR). The manufacturers’ data sheets usually specify propagation delays in response to all inputs, and they usually specify the maximum values for tPLH and tPHL. Modern IC flip-flops have propagation delays that range from a few nanoseconds to around 100 ns. The values of tPLH and tPHL are generally not the same, and they increase in direct proportion to the number of loads being driven by the Q output. Flip-flop propagation delays play an important part in certain situations that we will encounter later. 2024-11-05 B2-05a Digital Techniques / Electronic Instrument Systems Page 185 of 444 CASA Part 66 - Training Materials Only  Maximum Clocking Frequency The maximum clocking frequency is the highest frequency that may be applied to the CLK input of a flip-flop and still allow it to trigger reliably. Th