VLSI Design Flow: RTL to GDS PDF

VLSI DESIGN FLOW: RTL TO GDS Lecture 12 RTL Synthesis- Part I Sneh Saurabh Electronics and Communications Engineering IIIT Delhi ...

VLSI DESIGN FLOW: RTL TO GDS Lecture 12 RTL Synthesis- Part I Sneh Saurabh Electronics and Communications Engineering IIIT Delhi Lecture Plan RTL synthesis: ▪ Parsing, Elaboration ▪ Initial part of logic synthesis that translates the Verilog code into netlist of generic logic ▪ Translation of some Verilog gates Constructs to Circuit VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh  RTL Synthesis Tasks VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh RTL Synthesis: Parsing ▪ Reads the given RTL files and populates a data structure for further processing ▪ Lexical analysis: keywords, identifiers ▪ Grammar/syntax checking ▪ Syntax tree built: If grammar is correct Hierarchical data structure VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh RTL Synthesis: Elaboration (1) ▪ Checks whether the connections among RTL-specified components are legitimate. If legitimate, then make connections in the internal model; else report error module leaf(d, clk, module Top(data, clk, q); result); input d, clk; input data, clk; output q; output result;... wire w1, w2; endmodule leaf I1(.d(data),.clk(clk), module middle(D,.q(w1)); CLK, Q); input D, CLK; leaf I2(.d(w1),.clk(clk), output Q;.q(w2)); leaf F1(.d(D), middle I3(.D(w2),.clk(CLK),.q(Q));.Q(result),.CLK(clk)); endmodule endmodule VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh RTL Synthesis: Elaboration (2) VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh RTL Synthesis: Elaboration (3) ▪ Elaboration needs to process parameterized modules Parameterized modules can have different interfaces for varying parameters. ▪ Creates separate modules with different interfaces for each distinct set of parameters module counter(clk, rst, count); module top(clk, rst, count1, count2, parameter WIDTH=4; count3); input clk, rst; input clk, rst; output [WIDTH-1:0]count; output [15:0]count1; reg [WIDTH-1:0]count; output [7:0]count2;... output [3:0]count3; endmodule counter C1(clk, rst, count3); counter #(8) C2(clk, rst, count2); counter #(.WIDTH(16)) C3(clk, rst, count1); endmodule S. Saurabh, “Introduction to VLSI Design Flow”.Cambridge University Press, 2023. VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh  RTL Synthesis Verilog Constructs to Circuit VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Synthesizable and Non-synthesizable Constructs ▪ Some Verilog constructs cannot be Typically non-synthesizable: synthesized into circuit elements They are helpful in other design tasks ▪ Delay specification: such as functional verification ▪ out1