Power Dissipation in Circuits

Overview

• Power dissipation broadly consists of two components: dynamic power dissipation, and static power dissipation.
• Dynamic power dissipation occurs when a circuit actively computes.
• Static power dissipation occurs when the circuit is powered on, but not actively computing.

Dynamic Power Dissipation

• Dynamic power dissipation is also referred to as switching power.
• The formula to calculate switching power in a synchronous circuit is: 𝑃𝑠𝑤 = 𝐶𝐿 𝑉𝐷𝐷 𝛼𝑓𝑐𝑙𝑘, where:
  • 𝑓𝑐𝑙𝑘 = frequency of the clock in the circuit
  • 𝛼 = activity of the signal
  • 𝐶𝐿 = load capacitance
  • 𝑉𝐷𝐷 = supply voltage
• The energy dissipated during one cycle of 0→1→0 transition is: 𝐸𝑠𝑤 = 𝐶𝐿 𝑉𝐷𝐷

Non-Linear Power Model (NLPM)

• Internal power dissipation depends on the output load and input slew.
• It is modeled as a two-dimensional table, referred to as the Non-linear Power Model (NLPM), representing the internal power dissipation.
• The table represents energy dissipation per transition as dependent on the output load and input slew.

Technology Library Models: Static Power

• Static power dissipated inside a CMOS logic gate depends on the value (0 or 1) at its input pin.
• It can be modeled using a when condition in the library, with a value representing the static power dissipation for different input pin values.

Estimating Power Dissipation

• The total power dissipation can be calculated using the following formula: 𝑃𝑡𝑜𝑡 = 𝐶𝐿 𝑉𝐷𝐷 𝛼𝑓𝑐𝑙𝑘 + 𝑉𝐷𝐷 𝐼𝑆𝐶 + 𝑉𝐷𝐷 𝐼𝑙𝑒𝑎𝑘, where:
  • 𝑉𝐷𝐷 = supply voltage
  • 𝐶𝐿 = load capacitance
  • 𝑓𝑐𝑙𝑘 = frequency of the clock in the circuit
  • 𝛼 = activity of the signal
  • 𝐼𝑆𝐶 = short circuit current
  • 𝐼𝑙𝑒𝑎𝑘 = leakage current

Estimation of Activity

• Activity of a signal depends on the application and the circuit's logical structure and topology.
• Simulation-based techniques (Vector-based Technique) rely on test benches to estimate activity.

Scan Cells

• Scan cells are used for testing.
• They are typically multiplexer-based D flip-flops with scan input (SI), scan enable (SE), and scan output (SO) pins.
• Most popular is the MUXED-D Scan Cell.
• During normal/capture mode, SE=0 and the value at D is latched.
• In shift mode, SE=1 and the SI value is latched.
• Output pin produces the content of the D flip-flop.

Scan Design Flow: Tasks

• Design Preparation: Ensures the design is testable.
• Scan Synthesis: Converts the design into a scan design.
  • Scan Configuration: Decides on the number of scan chains, scan cells, and excludes elements from being converted to scan cells.
  • Scan Replacement: Replaces flip-flops with scan cells.
  • Scan Reordering and Stitching: Reorders scan cells based on physical location to facilitate easier routing.
• Test Vector Generation: Generates test vectors.
• Scan Verification: Verifies scan shift/capture operation and timing (STA).

Scan Design Flow: Costs

• Area Overhead: Scan cells and routing resources contribute to area overhead.
• IO Pin Cost: Increased IO pins are required.
• Performance Degradation: The multiplexer adds delay, leading to performance degradation.
• Design Effort Cost: Increased design effort is required for scan design.

OpenSTA Tutorial: Power Analysis

• OpenSTA is a tool for power analysis.
• Tutorial 9 of the course explores the power analysis using OpenSTA tool.
• OpenSTA installation and usage information is detailed in Tutorial 7.

This quiz covers key concepts of power dissipation in electronic circuits, focusing on dynamic and static power. You will learn about the formulas for calculating switching power and the Non-Linear Power Model as it relates to internal power dissipation. Prepare to test your understanding of these critical elements in circuit design.