CMOS VLSI Design: A Circuits and Systems Perspective (4th Edition) PDF

CMOS VLSI Design A Circuits and Systems Perspective Fourth Edition This page intentionally left blank CMOS VLSI Design A Circuits and Systems Perspective Fourth Edition...

CMOS VLSI Design A Circuits and Systems Perspective Fourth Edition This page intentionally left blank CMOS VLSI Design A Circuits and Systems Perspective Fourth Edition Neil H. E. Weste Macquarie University and The University of Adelaide David Money Harris Harvey Mudd College Addison-Wesley Boston Columbus Indianapolis New York San Francisco Upper Saddle River Amsterdam Cape Town Dubai London Madrid Milan Munich Paris Montreal Toronto Delhi Mexico City Sao Paulo Sydney Hong Kong Seoul Singapore Taipei Tokyo  Editor in Chief: Michael Hirsch Acquisitions Editor: Matt Goldstein Editorial Assistant: Chelsea Bell Managing Editor: Jeffrey Holcomb Senior Production Project Manager: Marilyn Lloyd Media Producer: Katelyn Boller Director of Marketing: Margaret Waples Marketing Coordinator: Kathryn Ferranti Senior Manufacturing Buyer: Carol Melville Senior Media Buyer: Ginny Michaud Text Designer: Susan Raymond Art Director, Cover: Linda Knowles Cover Designer: Joyce Cosentino Wells/J Wells Design Cover Image: Cover photograph courtesy of Nick Knupffer—Intel Corporation. Copyright © 2009 Intel Corporation. All rights reserved. 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H. This page intentionally left blank  Contents Preface xxv Chapter 1 Introduction 1.1 A Brief History................................................... 1 1.2 Preview......................................................... 6 1.3 MOS Transistors.................................................. 6 1.4 CMOS Logic..................................................... 9 1.4.1 The Inverter 9 1.4.2 The NAND Gate 9 1.4.3 CMOS Logic Gates 9 1.4.4 The NOR Gate 11 1.4.5 Compound Gates 11 1.4.6 Pass Transistors and Transmission Gates 12 1.4.7 Tristates 14 1.4.8 Multiplexers 15 1.4.9 Sequential Circuits 16 1.5 CMOS Fabrication and Layout..................................... 19 1.5.1 Inverter Cross-Section 19 1.5.2 Fabrication Process 20 1.5.3 Layout Design Rules 24 1.5.4 Gate Layouts 27 1.5.5 Stick Diagrams 28 1.6 Design Partitioning.............................................. 29 1.6.1 Design Abstractions 30 1.6.2 Structured Design 31 1.6.3 Behavioral, Structural, and Physical Domains 31 1.7 Example: A Simple MIPS Microprocessor........................... 33 1.7.1 MIPS Architecture 33 1.7.2 Multicycle MIPS Microarchitecture 34 1.8 Logic Design.................................................... 38 1.8.1 Top-Level Interfaces 38 1.8.2 Block Diagrams 38 1.8.3 Hierarchy 40 1.8.4 Hardware Description Languages 40 1.9 Circuit Design.................................................. 42 vii viii Contents 1.10 Physical Design................................................. 45 1.10.1 Floorplanning 45 1.10.2 Standard Cells 48 1.10.3 Pitch Matching 50 1.10.4 Slice Plans 50 1.10.5 Arrays 51 1.10.6 Area Estimation 51 1.11 Design Verification.............................................. 53 1.12 Fabrication, Packaging, and Testing................................ 54 Summary and a Look Ahead 55 Exercises 57 Chapter 2 MOS Transistor Theory 2.1 Introduction.................................................... 61 2.2 Long-Channel I-V Characteristics.................................. 64 2.3 C-V Characteristics.............................................. 68 2.3.1 Simple MOS Capacitance Models 68 2.3.2 Detailed MOS Gate Capacitance Model 70 2.3.3 Detailed MOS Diffusion Capacitance Model 72 2.4 Nonideal I-V Effects............................................. 74 2.4.1 Mobility Degradation and Velocity Saturation 75 2.4.2 Channel Length Modulation 78 2.4.3 Threshold Voltage Effects 79 2.4.4 Leakage 80 2.4.5 Temperature Dependence 85 2.4.6 Geometry Dependence 86 2.4.7 Summary 86 2.5 DC Transfer Characteristics....................................... 87 2.5.1 Static CMOS Inverter DC Characteristics 88 2.5.2 Beta Ratio Effects 90 2.5.3 Noise Margin 91 2.5.4 Pass Transistor DC Characteristics 92 2.6 Pitfalls and Fallacies............................................ 93 Summary 94 Exercises 95 Chapter 3 CMOS Processing Technology 3.1 Introduction.................................................... 99 3.2 CMOS Technologies............................................ 100 3.2.1 Wafer Formation 100 3.2.2 Photolithography 101  Contents ix 3.2.3 Well and Channel Formation 103 3.2.4 Silicon Dioxide (SiO2) 105 3.2.5 Isolation 106 3.2.6 Gate Oxide 107 3.2.7 Gate and Source/Drain Formations 108 3.2.8 Contacts and Metallization 110 3.2.9 Passivation 112 3.2.10 Metrology 112 3.3 Layout Design Rules............................................ 113 3.3.1 Design Rule Background 113 3.3.2 Scribe Line and Other Structures 116 3.3.3 MOSIS Scalable CMOS Design Rules 117 3.3.4 Micron Design Rules 118 3.4 CMOS Process Enhancements.................................... 119 3.4.1 Transistors 119 3.4.2 Interconnect 122 3.4.3 Circuit Elements 124 3.4.4 Beyond Conventional CMOS 129 3.5 Technology-Related CAD Issues................................... 130 3.5.1 Design Rule Checking (DRC) 131 3.5.2 Circuit Extraction 132 3.6 Manufacturing Issues........................................... 133 3.6.1 Antenna Rules 133 3.6.2 Layer Density Rules 134 3.6.3 Resolution Enhancement Rules 134 3.6.4 Metal Slotting Rules 135 3.6.5 Yield Enhancement Guidelines 135 3.7 Pitfalls and Fallacies........................................... 136 3.8 Historical Perspective........................................... 137 Summary 139 Exercises 139 Chapter 4 Delay 4.1 Introduction.................................................. 141 4.1.1 Definitions 141 4.1.2 Timing Optimization 142 4.2 Transient Response............................................. 143 4.3 RC Delay Model................................................ 146 4.3.1 Effective Resistance 146 4.3.2 Gate and Diffusion Capacitance 147 4.3.3 Equivalent RC Circuits 147 4.3.4 Transient Response 148 4.3.5 Elmore Delay 150 x Contents 4.3.6 Layout Dependence of Capacitance 153 4.3.7 Determining Effective Resistance 154 4.4 Linear Delay Model............................................. 155 4.4.1 Logical Effort 156 4.4.2 Parasitic Delay 156 4.4.3 Delay in a Logic Gate 158 4.4.4 Drive 159 4.4.5 Extracting Logical Effort from Datasheets 159 4.4.6 Limitations to the Linear Delay Model 160 4.5 Logical Effort of Paths.......................................... 163 4.5.1 Delay in Multistage Logic Networks 163 4.5.2 Choosing the Best Number of Stages 166 4.5.3 Example 168 4.5.4 Summary and Observations 169 4.5.5 Limitations of Logical Effort 171 4.5.6 Iterative Solutions for Sizing 171 4.6 Timing Analysis Delay Models.................................... 173 4.6.1 Slope-Based Linear Model 173 4.6.2 Nonlinear Delay Model 174 4.6.3 Current Source Model 174 4.7 Pitfalls and Fallacies........................................... 174 4.8 Historical Perspective........................................... 175 Summary 176 Exercises 176 Chapter 5 Power 5.1 Introduction................................................... 181 5.1.1 Definitions 182 5.1.2 Examples 182 5.1.3 Sources of Power Dissipation 184 5.2 Dynamic Power................................................ 185 5.2.1 Activity Factor 186 5.2.2 Capacitance 188 5.2.3 Voltage 190 5.2.4 Frequency 192 5.2.5 Short-Circuit Current 193 5.2.6 Resonant Circuits 193 5.3 Static Power................................................... 194 5.3.1 Static Power Sources 194 5.3.2 Power Gating 197 5.3.3 Multiple Threshold Voltages and Oxide Thicknesses 199  Contents xi 5.3.4 Variable Threshold Voltages 199 5.3.5 Input Vector Control 200 5.4 Energy-Delay Optimization....................................... 200 5.4.1 Minimum Energy 200 5.4.2 Minimum Energy-Delay Product 203 5.4.3 Minimum Energy Under a Delay Constraint 203 5.5 Low Power Architectures........................................ 204 5.5.1 Microarchitecture 204 5.5.2 Parallelism and Pipelining 204 5.5.3 Power Management Modes 205 5.6 Pitfalls and Fallacies............................................ 206 5.7 Historical Perspective........................................... 207 Summary 209 Exercises 209 Chapter 6 Interconnect 6.1 Introduction................................................... 211 6.1.1 Wire Geometry 211 6.1.2 Example: Intel Metal Stacks 212 6.2 Interconnect Modeling.......................................... 213 6.2.1 Resistance 214 6.2.2 Capacitance 215 6.2.3 Inductance 218 6.2.4 Skin Effect 219 6.2.5 Temperature Dependence 220 6.3 Interconnect Impact............................................ 220 6.3.1 Delay 220 6.3.2 Energy 222 6.3.3 Crosstalk 222 6.3.4 Inductive Effects 224 6.3.5 An Aside on Effective Resistance and Elmore Delay 227 6.4 Interconnect Engineering........................................ 229 6.4.1 Width, Spacing, and Layer 229 6.4.2 Repeaters 230 6.4.3 Crosstalk Control 232 6.4.4 Low-Swing Signaling 234 6.4.5 Regenerators 236 6.5 Logical Effort with Wires........................................ 236 6.6 Pitfalls and Fallacies............................................ 237 Summary 238 Exercises 238 xii Contents Chapter 7 Robustness 7.1 Introduction................................................... 241 7.2 Variability..................................................... 241 7.2.1 Supply Voltage 242 7.2.2 Temperature 242 7.2.3 Process Variation 243 7.2.4 Design Corners 244 7.3 Reliability..................................................... 246 7.3.1 Reliability Terminology 246 7.3.2 Oxide Wearout 247 7.3.3 Interconnect Wearout 249 7.3.4 Soft Errors 251 7.3.5 Overvoltage Failure 252 7.3.6 Latchup 253 7.4 Scaling....................................................... 254 7.4.1 Transistor Scaling 255 7.4.2 Interconnect Scaling 257 7.4.3 International Technology Roadmap for Semiconductors 258 7.4.4 Impacts on Design 259 7.5 Statistical Analysis of Variability.................................. 263 7.5.1 Properties of Random Variables 263 7.5.2 Variation Sources 266 7.5.3 Variation Impacts 269 7.6 Variation-Tolerant Design........................................ 274 7.6.1 Adaptive Control 275 7.6.2 Fault Tolerance 275 7.7 Pitfalls and Fallacies........................................... 277 7.8 Historical Perspective........................................... 278 Summary 284 Exercises 284 Chapter 8 Circuit Simulation 8.1 Introduction................................................... 287 8.2 A SPICE Tutorial............................................... 288 8.2.1 Sources and Passive Components 288 8.2.2 Transistor DC Analysis 292 8.2.3 Inverter Transient Analysis 292 8.2.4 Subcircuits and Measurement 294 8.2.5 Optimization 296 8.2.6 Other HSPICE Commands 298  Contents xiii 8.3 Device Models................................................. 298 8.3.1 Level 1 Models 299 8.3.2 Level 2 and 3 Models 300 8.3.3 BSIM Models 300 8.3.4 Diffusion Capacitance Models 300 8.3.5 Design Corners 302 8.4 Device Characterization......................................... 303 8.4.1 I-V Characteristics 303 8.4.2 Threshold Voltage 306 8.4.3 Gate Capacitance 308 8.4.4 Parasitic Capacitance 308 8.4.5 Effective Resistance 310 8.4.6 Comparison of Processes 311 8.4.7 Process and Environmental Sensitivity 313 8.5 Circuit Characterization......................................... 313 8.5.1 Path Simulations 313 8.5.2 DC Transfer Characteristics 315 8.5.3 Logical Effort 315 8.5.4 Power and Energy 318 8.5.5 Simulating Mismatches 319 8.5.6 Monte Carlo Simulation 319 8.6 Interconnect Simulation......................................... 319 8.7 Pitfalls and Fallacies............................................ 322 Summary 324 Exercises 324 Chapter 9 Combinational Circuit Design 9.1 Introduction................................................... 327 9.2 Circuit Families................................................ 328 9.2.1 Static CMOS 329 9.2.2 Ratioed Circuits 334 9.2.3 Cascode Voltage Switch Logic 339 9.2.4 Dynamic Circuits 339 9.2.5 Pass-Transistor Circuits 349 9.3 Circuit Pitfalls................................................. 354 9.3.1 Threshold Drops 355 9.3.2 Ratio Failures 355 9.3.3 Leakage 356 9.3.4 Charge Sharing 356 9.3.5 Power Supply Noise 356 9.3.6 Hot Spots 357 xiv Contents 9.3.7 Minority Carrier Injection 357 9.3.8 Back-Gate Coupling 358 9.3.9 Diffusion Input Noise Sensitivity 358 9.3.10 Process Sensitivity 358 9.3.11 Example: Domino Noise Budgets 359 WEB ENHANCED 9.4 More Circuit Families........................................... 360 9.5 Silicon-On-Insulator Circuit Design............................... 360 9.5.1 Floating Body Voltage 361 9.5.2 SOI Advantages 362 9.5.3 SOI Disadvantages 362 9.5.4 Implications for Circuit Styles 363 9.5.5 Summary 364 9.6 Subthreshold Circuit Design..................................... 364 9.6.1 Sizing 365 9.6.2 Gate Selection 365 9.7 Pitfalls and Fallacies........................................... 366 9.8 Historical Perspective........................................... 367 Summary 369 Exercises 370 Chapter 10 Sequential Circuit Design 10.1 Introduction................................................... 375 10.2 Sequencing Static Circuits....................................... 376 10.2.1 Sequencing Methods 376 10.2.2 Max-Delay Constraints 379 10.2.3 Min-Delay Constraints 383 10.2.4 Time Borrowing 386 10.2.5 Clock Skew 389 10.3 Circuit Design of Latches and Flip-Flops........................... 391 10.3.1 Conventional CMOS Latches 392 10.3.2 Conventional CMOS Flip-Flops 393 10.3.3 Pulsed Latches 395 10.3.4 Resettable Latches and Flip-Flops 396 10.3.5 Enabled Latches and Flip-Flops 397 10.3.6 Incorporating Logic into Latches 398 10.3.7 Klass Semidynamic Flip-Flop (SDFF) 399 10.3.8 Differential Flip-Flops 399 10.3.9 Dual Edge-Triggered Flip-Flops 400 10.3.10 Radiation-Hardened Flip-Flops 401 WEB 10.3.11 True Single-Phase-Clock (TSPC) Latches and Flip-Flops 402 ENHANCED 10.4 Static Sequencing Element Methodology........................... 402 10.4.1 Choice of Elements 403 10.4.2 Characterizing Sequencing Element Delays 405  Contents xv 10.4.3 State Retention Registers 408 10.4.4 Level-Converter Flip-Flops 408 10.4.5 Design Margin and Adaptive Sequential Elements 409 WEB ENHANCED 10.4.6 Two-Phase Timing Types 411 WEB ENHANCED 10.5 Sequencing Dynamic Circuits.................................... 411 10.6 Synchronizers................................................. 411 10.6.1 Metastability 412 10.6.2 A Simple Synchronizer 415 10.6.3 Communicating Between Asynchronous Clock Domains 416 10.6.4 Common Synchronizer Mistakes 417 10.6.5 Arbiters 419 10.6.6 Degrees of Synchrony 419 10.7 Wave Pipelining................................................ 420 10.8 Pitfalls and Fallacies........................................... 422 WEB ENHANCED 10.9 Case Study: Pentium 4 and Itanium 2 Sequencing Methodologies..... 423 Summary 423 Exercises 425 Chapter 11 Datapath Subsystems 11.1 Introduction................................................... 429 11.2 Addition/Subtraction............................................ 429 11.2.1 Single-Bit Addition 430 11.2.2 Carry-Propagate Addition 434 11.2.3 Subtraction 458 11.2.4 Multiple-Input Addition 458 11.2.5 Flagged Prefix Adders 459 11.3 One/Zero Detectors............................................. 461 11.4 Comparators................................................... 462 11.4.1 Magnitude Comparator 462 11.4.2 Equality Comparator 462 11.4.3 K = A + B Comparator 463 11.5 Counters...................................................... 463 11.5.1 Binary Counters 464 11.5.2 Fast Binary Counters 465 11.5.3 Ring and Johnson Counters 466 11.5.4 Linear-Feedback Shift Registers 466 11.6 Boolean Logical Operations...................................... 468 11.7 Coding....................................................... 468 11.7.1 Parity 468 11.7.2 Error-Correcting Codes 468 11.7.3 Gray Codes 470 11.7.4 XOR/XNOR Circuit Forms 471 xvi Contents 11.8 Shifters....................................................... 472 11.8.1 Funnel Shifter 473 11.8.2 Barrel Shifter 475 11.8.3 Alternative Shift Functions 476 11.9 Multiplication................................................. 476 11.9.1 Unsigned Array Multiplication 478 11.9.2 Two’s Complement Array Multiplication 479 11.9.3 Booth Encoding 480 11.9.4 Column Addition 485 11.9.5 Final Addition 489 11.9.6 Fused Multiply-Add 490 WEB 11.9.7 Serial Multiplication 490 ENHANCED 11.9.8 Summary 490 11.10 Parallel-Prefix Computations..................................... 491 11.11 Pitfalls and Fallacies........................................... 493 Summary 494 Exercises 494 Chapter 12 Array Subsystems 12.1 Introduction................................................... 497 12.2 SRAM........................................................ 498 12.2.1 SRAM Cells 499 12.2.2 Row Circuitry 506 12.2.3 Column Circuitry 510 12.2.4 Multi-Ported SRAM and Register Files 514 12.2.5 Large SRAMs 515 12.2.6 Low-Power SRAMs 517 12.2.7 Area, Delay, and Power of RAMs and Register Files 520 12.3 DRAM........................................................ 522 12.3.1 Subarray Architectures 523 12.3.2 Column Circuitry 525 12.3.3 Embedded DRAM 526 12.4 Read-Only Memory............................................. 527 12.4.1 Programmable ROMs 529 12.4.2 NAND ROMs 530 12.4.3 Flash 531 12.5 Serial Access Memories......................................... 533 12.5.1 Shift Registers 533 12.5.2 Queues (FIFO, LIFO) 533 12.6 Content-Addressable Memory.................................... 535 12.7 Programmable Logic Arrays...................................... 537  Contents xvii 12.8 Robust Memory Design.......................................... 541 12.8.1 Redundancy 541 12.8.2 Error Correcting Codes (ECC) 543 12.8.3 Radiation Hardening 543 12.9 Historical Perspective........................................... 544 Summary 545 Exercises 546 Chapter 13 Special-Purpose Subsystems 13.1 Introduction................................................... 549 13.2 Packaging and Cooling.......................................... 549 13.2.1 Package Options 549 13.2.2 Chip-to-Package Connections 551 13.2.3 Package Parasitics 552 13.2.4 Heat Dissipation 552 13.2.5 Temperature Sensors 553 13.3 Power Distribution.............................................. 555 13.3.1 On-Chip Power Distribution Network 556 13.3.2 IR Drops 557 13.3.3 L di/dt Noise 558 13.3.4 On-Chip Bypass Capacitance 559 13.3.5 Power Network Modeling 560 13.3.6 Power Supply Filtering 564 13.3.7 Charge Pumps 564 13.3.8 Substrate Noise 565 13.3.9 Energy Scavenging 565 13.4 Clocks........................................................ 566 13.4.1 Definitions 566 13.4.2 Clock System Architecture 568 13.4.3 Global Clock Generation 569 13.4.4 Global Clock Distribution 571 13.4.5 Local Clock Gaters 575 13.4.6 Clock Skew Budgets 577 13.4.7 Adaptive Deskewing 579 13.5 PLLs and DLLs................................................ 580 13.5.1 PLLs 580 13.5.2 DLLs 587 13.5.3 Pitfalls 589 13.6 I/0........................................................... 590 13.6.1 Basic I/O Pad Circuits 591 13.6.2 Electrostatic Discharge Protection 593 13.6.3 Example: MOSIS I/O Pads 594 13.6.4 Mixed-Voltage I/O 596 xviii Contents 13.7 High-Speed Links.............................................. 597 13.7.1 High-Speed I/O Channels 597 13.7.2 Channel Noise and Interference 600 13.7.3 High-Speed Transmitters and Receivers 601 13.7.4 Synchronous Data Transmission 606 13.7.5 Clock Recovery in Source-Synchronous Systems 606 13.7.6 Clock Recovery in Mesochronous Systems 608 13.7.7 Clock Recovery in Pleisochronous Systems 610 13.8 Random Circuits............................................... 610 13.8.1 True Random Number Generators 610 13.8.2 Chip Identification 611 13.9 Pitfalls and Fallacies........................................... 612 Summary 613 Exercises 614 Chapter 14 Design Methodology and Tools 14.1 Introduction................................................... 615 14.2 Structured Design Strategies..................................... 617 14.2.1 A Software Radio—A System Example 618 14.2.2 Hierarchy 620 14.2.3 Regularity 623 14.2.4 Modularity 625 14.2.5 Locality 626 14.2.6 Summary 627 14.3 Design Methods............................................... 627 14.3.1 Microprocessor/DSP 627 14.3.2 Programmable Logic 628 14.3.3 Gate Array and Sea of Gates Design 631 14.3.4 Cell-Based Design 632 14.3.5 Full Custom Design 634 14.3.6 Platform-Based Design—System on a Chip 635 14.3.7 Summary 636 14.4 Design Flows.................................................. 636 14.4.1 Behavioral Synthesis Design Flow (ASIC Design Flow) 637 14.4.2 Automated Layout Generation 641 14.4.3 Mixed-Signal or Custom-Design Flow 645 14.5 Design Economics.............................................. 646 14.5.1 Non-Recurring Engineering Costs (NREs) 647 14.5.2 Recurring Costs 649 14.5.3 Fixed Costs 650 14.5.4 Schedule 651 14.5.5 Personpower 653 14.5.6 Project Management 653 14.5.7 Design Reuse 654  Contents xix 14.6 Data Sheets and Documentation.................................. 655 14.6.1 The Summary 655 14.6.2 Pinout 655 14.6.3 Description of Operation 655 14.6.4 DC Specifications 655 14.6.5 AC Specifications 656 14.6.6 Package Diagram 656 14.6.7 Principles of Operation Manual 656 14.6.8 User Manual 656 WEB ENHANCED 14.7 CMOS Physical Design Styles.................................... 656 14.8 Pitfalls and Fallacies........................................... 657 Exercises 657 Chapter 15 Testing, Debugging, and Verification 15.1 Introduction................................................... 659 15.1.1 Logic Verification 660 15.1.2 Debugging 662 15.1.3 Manufacturing Tests 664 15.2 Testers, Test Fixtures, and Test Programs.......................... 666 15.2.1 Testers and Test Fixtures 666 15.2.2 Test Programs 668 15.2.3 Handlers 669 15.3 Logic Verification Principles...................................... 670 15.3.1 Test Vectors 670 15.3.2 Testbenches and Harnesses 671 15.3.3 Regression Testing 671 15.3.4 Version Control 672 15.3.5 Bug Tracking 673 15.4 Silicon Debug Principles........................................ 673 15.5 Manufacturing Test Principles.................................... 676 15.5.1 Fault Models 677 15.5.2 Observability 679 15.5.3 Controllability 679 15.5.4 Repeatability 679 15.5.5 Survivability 679 15.5.6 Fault Coverage 680 15.5.7 Automatic Test Pattern Generation (ATPG) 680 15.5.8 Delay Fault Testing 680 15.6 Design for Testability........................................... 681 15.6.1 Ad Hoc Testing 681 15.6.2 Scan Design 682 15.6.3 Built-In Self-Test (BIST) 684 15.6.4 IDDQ Testing 687 15.6.5 Design for Manufacturability 687 xx Contents WEB ENHANCED 15.7 Boundary Scan................................................ 688 15.8 Testing in a University Environment............................... 689 15.9 Pitfalls and Fallacies........................................... 690 Summary 697 Exercises 697 Appendix A Hardware Description Languages A.1 Introduction................................................... 699 A.1.1 Modules 700 A.1.2 Simulation and Synthesis 701 A.2 Combinational Logic............................................ 702 A.2.1 Bitwise Operators 702 A.2.2 Comments and White Space 703 A.2.3 Reduction Operators 703 A.2.4 Conditional Assignment 704 A.2.5 Internal Variables 706 A.2.6 Precedence and Other Operators 708 A.2.7 Numbers 708 A.2.8 Zs and Xs 709 A.2.9 Bit Swizzling 711 A.2.10 Delays 712 A.3 Structural Modeling............................................ 713 A.4 Sequential Logic............................................... 717 A.4.1 Registers 717 A.4.2 Resettable Registers 718 A.4.3 Enabled Registers 719 A.4.4 Multiple Registers 720 A.4.5 Latches 721 A.4.6 Counters 722 A.4.7 Shift Registers 724 A.5 Combinational Logic with Always / Process Statements.............. 724 A.5.1 Case Statements 726 A.5.2 If Statements 729 A.5.3 SystemVerilog Casez 731 A.5.4 Blocking and Nonblocking Assignments 731 A.6 Finite State Machines.......................................... 735 A.6.1 FSM Example 735 A.6.2 State Enumeration 736 A.6.3 FSM with Inputs 738 A.7 Type Idiosyncracies............................................. 740  Contents xxi A.8 Parameterized Modules......................................... 742 A.9 Memory....................................................... 745 A.9.1 RAM 745 A.9.2 Multiported Register Files 747 A.9.3 ROM 748 A.10 Testbenches................................................... 749 A.11 SystemVerilog Netlists.......................................... 754 A.12 Example: MIPS Processor....................................... 755 A.12.1 Testbench 756 A.12.2 SystemVerilog 757 A.12.3 VHDL 766 Exercises 776 References 785 Index 817 Credits 838 This page intentionally left blank  Preface In the two-and-a-half decades since the first edition of this book was published, CMOS technology has claimed the preeminent position in modern electrical system design. It has enabled the widespread use of wireless communication, the Internet, and personal com- puters. No other human invention has seen such rapid growth for such a sustained period. The transistor counts and clock frequencies of state-of-the-art chips have grown by orders of magnitude. 1st Edition 2nd Edition 3rd Edition 4th Edition Year 1985 1993 2004 2010 Transistor Counts 105–106 106–107 108–109 109–1010 Clock Frequencies 107 108 109 109 Worldwide Market $25B $60B $170B $250B This edition has been heavily revised to reflect the rapid changes in integrated circuit design over the past six years. While the basic principles are largely the same, power con- sumption and variability have become primary factors for chip design. The book has been reorganized to emphasize the key factors: delay, power, interconnect, and robustness. Other chapters have been reordered to reflect the order in which we teach the material. How to Use This Book This book intentionally covers more breadth and depth than any course would cover in a semester. It is accessible for a first undergraduate course in VLSI, yet detailed enough for advanced graduate courses and is useful as a reference to the practicing engineer. You are encouraged to pick and choose topics according to your interest. Chapter 1 previews the entire field, while subsequent chapters elaborate on specific topics. Sections are marked with the “Optional” icon (shown here in the margin) if they are not needed to understand subsequent sections. You may skip them on a first reading and return when they are rele- vant to you. We have endeavored to include figures whenever possible (“a picture is worth a thou- sand words”) to trigger your thinking. As you encounter examples throughout the text, we urge you to think about them before reading the solutions. We have also provided exten- sive references for those who need to delve deeper into topics introduced in this text. We xxiii xxiv Preface Contents have emphasized the best practices that are used in industry and warned of pitfalls and fal- lacies. Our judgments about the merits of circuits may become incorrect as technology and applications change, but we believe it is the responsibility of a writer to attempt to call out the most relevant information. Supplements Numerous supplements are available on the Companion Web site for the book, www.cmosvlsi.com. Supplements to help students with the course include:  A lab manual with laboratory exercises involving the design of an 8-bit micropro- cessor covered in Chapter 1.  A collection of links to VLSI resources including open-source CAD tools and pro- cess parameters.  A student solutions manual that includes answers to odd-numbered problems.  Certain sections of the book moved online to shorten the page count. These sec- WEB ENHANCED tions are indicated by the “Web Enhanced” icon (shown here in the margin). Supplements to help instructors with the course include:  A sample syllabus.  Lecture slides for an introductory VLSI course.  An instructor’s manual with solutions. These materials have been prepared exclusively for professors using the book in a course. Please send email to [email protected] for information on how to access them. Acknowledgments We are indebted to many people for their reviews, suggestions, and technical discussions. These people include: Bharadwaj “Birdy” Amrutur, Mark Anders, Adnan Aziz, Jacob Baker, Kaustav Banerjee, Steve Bibyk, David Blaauw, Erik Brunvand, Neil Burgess, Wayne Burleson, Robert Drost, Jo Ebergen, Sarah Harris, Jacob Herbold, Ron Ho, David Hopkins, Mark Horowitz, Steven Hsu, Tanay Karnik, Omid Kaveh, Matthew Keeter, Ben Keller, Ali Keshavarzi, Brucek Khailany, Jaeha Kim, Volkan Kursun, Simon Knowles, Ram Krishnamurthy, Austin Lee, Ana Sonia Leon, Shih-Lien Lu, Sanu Mathew, Alek- sandar Milenkovic, Sam Naffziger, Braden Phillips, Stefan Rusu, Justin Schauer, James Stine, Jason Stinson, Aaron Stratton, Ivan Sutherland, Jim Tschanz, Alice Wang, Gu- Yeon Wei, and Peiyi Zhao. We apologize in advance to anyone we overlooked. MOSIS and IBM kindly provided permission to use nanometer SPICE models for many examples. Nathaniel Pinckney spent a summer revising the laboratory exercises and updating simulations. Jaeha Kim contributed new sections on phase-locked loops and high-speed I/O for Chapter 13. David would like to thank Bharadwaj Amrutur of the Indian Institute of Science and Braden Phillips of the University of Adelaide for hosting him during two productive summers of writing.  Preface Contents xxv Addison-Wesley has done an admirable job with the grueling editorial and produc- tion process. We would particularly like to thank our editor, Matt Goldstein, and our compositor, Gillian Hall. Sally Harris has been editing family books since David was an infant on her lap. She read the page proofs with amazing attention to detail and unearthed hundreds of errors. This book would not have existed without the support of our families. David would particularly like to thank his wife Jennifer and sons Abraham and Samuel for enduring two summers of absence while writing, and to our extended family for their tremendous assistance. We have become painfully aware of the ease with which mistakes creep into a book. Scores of 3rd edition readers have reported bugs that are now corrected. Despite our best efforts at validation, we are confident that we have introduced a similar number of new errors. Please check the errata sheet at www.cmosvlsi.com/errata.pdf to see if the bug has already been reported. Send your reports to [email protected]. N. W. D. M. H. January 2010 This page intentionally left blank  Introduction 1 1.1 A Brief History In 1958, Jack Kilby built the first integrated circuit flip-flop with two transistors at Texas Instruments. In 2008, Intel’s Itanium microprocessor contained more than 2 billion tran- sistors and a 16 Gb Flash memory contained more than 4 billion transistors. This corre- sponds to a compound annual growth rate of 53% over 50 years. No other technology in history has sustained such a high growth rate lasting for so long. This incredible growth has come from steady miniaturization of transistors and improvements in manufacturing processes. Most other fields of engineering involve trade- offs between performance, power, and price. However, as transistors become smaller, they also become faster, dissipate less power, and are cheaper to manufacture. This synergy has not only revolutionized electronics, but also society at large. The processing performance once dedicated to secret government supercomputers is now available in disposable cellular telephones. The memory once needed for an entire company’s accounting system is now carried by a teenager in her iPod. Improvements in integrated circuits have enabled space exploration, made automobiles safer and more fuel- efficient, revolutionized the nature of warfare, brought much of mankind’s knowledge to our Web browsers, and made the world a flatter place. Figure 1.1 shows annual sales in the worldwide semiconductor market. Integrated cir- cuits became a $100 billion/year business in 1994. In 2007, the industry manufactured approximately 6 quintillion (6 × 1018) transistors, or nearly a billion for every human being on the planet. Thousands of engineers have made their fortunes in the field. New fortunes lie ahead for those with innovative ideas and the talent to bring those ideas to reality. During the first half of the twentieth century, electronic circuits used large, expensive, power-hungry, and unreliable vacuum tubes. In 1947, John Bardeen and Walter Brattain built the first functioning point contact transistor at Bell Laboratories, shown in Figure 1.2(a) [Riordan97]. It was nearly classified as a military secret, but Bell Labs publicly introduced the device the following year. We have called it the Transistor, T-R-A-N-S-I-S-T-O-R, because it is a resistor or semiconductor device which can amplify electrical signals as they are transferred through it from input to output terminals. It is, if you will, the electrical equivalent of a vacuum tube amplifier. But there the similarity ceases. It has no vacuum, no filament, no glass tube. It is composed entirely of cold, solid substances. 1 2 Chapter 1 Introduction 250 Global Semiconductor Billings 200 (Billions of US$) 150 100 50 0 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 2008 Year FIGURE 1.1 Size of worldwide semiconductor market (Courtesy of Semiconductor Industry Association.) Ten years later, Jack Kilby at Texas Instruments realized the potential for miniaturiza- tion if multiple transistors could be built on one piece of silicon. Figure 1.2(b) shows his first prototype of an integrated circuit, constructed from a germanium slice and gold wires. The invention of the transistor earned the Nobel Prize in Physics in 1956 for Bardeen, Brattain, and their supervisor William Shockley. Kilby received the Nobel Prize in Physics in 2000 for the invention of the integrated circuit. Transistors can be viewed as electrically controlled switches with a control terminal and two other terminals that are connected or disconnected depending on the voltage or current applied to the control. Soon after inventing the point contact transistor, Bell Labs developed the bipolar junction transistor. Bipolar transistors were more reliable, less noisy, and more power-efficient. Early integrated circuits primarily used bipolar transistors. Bipolar transistors require a small current into the control (base) terminal to switch much larger currents between the other two (emitter and collector) terminals. The quiescent power dissipated by these base currents, drawn even when the circuit is not switching, (a) (b) FIGURE 1.2 (a) First transistor (Property of AT&T Archives. Reprinted with permission of AT&T.) and (b) first integrated circuit (Courtesy of Texas Instruments.)  1.1 A Brief History 3 limits the maximum number of transistors that can be integrated onto a single die. By the 1960s, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) began to enter production. MOSFETs offer the compelling advantage that they draw almost zero control current while idle. They come in two flavors: nMOS and pMOS, using n-type and p-type silicon, respectively. The original idea of field effect transistors dated back to the German scientist Julius Lilienfield in 1925 [US patent 1,745,175] and a structure closely resem- bling the MOSFET was proposed in 1935 by Oskar Heil [British patent 439,457], but materials problems foiled early attempts to make functioning devices. In 1963, Frank Wanlass at Fairchild described the first logic gates using MOSFETs [Wanlass63]. Fairchild’s gates used both nMOS and pMOS transistors, earning the name Complementary Metal Oxide Semiconductor, or CMOS. The circuits used discrete tran- sistors but consumed only nanowatts of power, six orders of magnitude less than their bipolar counterparts. With the development of the silicon planar process, MOS integrated circuits became attractive for their low cost because each transistor occupied less area and the fabrication process was simpler [Vadasz69]. Early commercial processes used only pMOS transistors and suffered from poor performance, yield, and reliability. Processes using nMOS transistors became common in the 1970s [Mead80]. Intel pioneered nMOS technology with its 1101 256-bit static random access memory and 4004 4-bit micropro- cessor, as shown in Figure 1.3. While the nMOS process was less expensive than CMOS, nMOS logic gates still consumed power while idle. Power consumption became a major issue in the 1980s as hundreds of thousands of transistors were integrated onto a single die. CMOS processes were widely adopted and have essentially replaced nMOS and bipo- lar processes for nearly all digital logic applications. In 1965, Gordon Moore observed that plotting the number of transistors that can be most economically manufactured on a chip gives a straight line on a semilogarithmic scale [Moore65]. At the time, he found transistor count doubling every 18 months. This obser- vation has been called Moore’s Law and has become a self-fulfilling prophecy. Figure 1.4 shows that the number of transistors in Intel microprocessors has doubled every 26 months since the invention of the 4004. Moore’s Law is driven primarily by scaling down the size of transistors and, to a minor extent, by building larger chips. The level of integra- tion of chips has been classified as small-scale, medium-scale, large-scale, and very large- scale. Small-scale integration (SSI) circuits, such as the 7404 inverter, have fewer than 10 (a) (b) FIGURE 1.3 (a) Intel 1101 SRAM (© IEEE 1969 [Vadasz69]) and (b) 4004 microprocessor (Reprinted with permission of Intel Corporation.) 4 Chapter 1 Introduction 1,000,000,000 Core 2 Quad Core 2 Duo Pentium M 100,000,000 Pentium 4 Pentium II 10,000,000 Pentium Pro Pentium III Pentium Transistors Intel486 1,000,000 Intel386 80286 100,000 8086 10,000 8008 8080 4004 1,000 1970 1975 1980 1985 1990 1995 2000 2005 Year FIGURE 1.4 Transistors in Intel microprocessors [Intel10] gates, with roughly half a dozen transistors per gate. Medium-scale integration (MSI) cir- cuits, such as the 74161 counter, have up to 1000 gates. Large-scale integration (LSI) circuits, such as simple 8-bit microprocessors, have up to 10,000 gates. It soon became apparent that new names would have to be created every five years if this naming trend continued and thus the term very large-scale integration (VLSI) is used to describe most integrated circuits from the 1980s onward. A corollary of Moore’s law is Dennard’s Scaling Law [Dennard74]: as transistors shrink, they become faster, consume less power, and are cheaper to manufacture. Figure 1.5 shows that Intel microprocessor clock frequencies have doubled roughly every 34 months.This frequency scaling hit the power wall around 2004, and clock frequencies have leveled off around 3 GHz. Computer performance, measured in time to run an application, has advanced even more than raw clock speed. Presently, the performance is driven by the number of cores on a chip rather than by the clock. Even though an individual CMOS transistor uses very little energy each time it switches, the enormous number of transistors switching at very high rates of speed have made power consumption a major design consideration again. Moreover, as transistors have become so small, they cease to turn completely OFF. Small amounts of current leaking through each transistor now lead to significant power consumption when multiplied by millions or bil- lions of transistors on a chip. The feature size of a CMOS manufacturing process refers to the minimum dimension of a transistor that can be reliably built. The 4004 had a feature size of 10 Rm in 1971. The Core 2 Duo had a feature size of 45 nm in 2008. Manufacturers introduce a new process generation (also called a technology node) every 2–3 years with a 30% smaller feature size to pack twice as many transistors in the same area. Figure 1.6 shows the progression of process generations. Feature sizes down to 0.25 Rm are generally specified in microns (10–6 m), while smaller feature sizes are expressed in nanometers (10–9 m). Effects that were relatively minor in micron processes, such as transistor leakage, variations in characteristics of adjacent tran- sistors, and wire resistance, are of great significance in nanometer processes. Moore’s Law has become a self-fulfilling prophecy because each company must keep up with its competitors. Obviously, this scaling cannot go on forever because transistors cannot be smaller than atoms. Dennard scaling has already begun to slow. By the 45 nm  1.1 A Brief History 5 10,000 4004 8008 1,000 8080 8086 Clock Speed (MHz) 80286 100 Intel386 Intel486 Pentium 10 Pentium Pro/II/III Pentium 4 Pentium M 1 Core 2 Duo 0 1970 1975 1980 1985 1990 1995 2000 2005 2010 Year FIGURE 1.5 Clock frequencies of Intel microprocessors 10 10 μm 6 μm 3 μm 1.5 μm 1 μm 1 0.8 μm Feature Size (μm) 0.6 μm 0.35 μm 0.25 μm 180 nm 130 nm 0.1 90 nm 65 nm 45 nm 32 nm 22 nm 0.01 1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 Year FIGURE 1.6 Process generations. Future predictions from [SIA2007]. 6 Chapter 1 Introduction generation, designers are having to make trade-offs between improving power and improving delay. Although the cost of printing each transistor goes down, the one-time design costs are increasing exponentially, relegating state-of-the-art processes to chips that will sell in huge quantities or that have cutting-edge performance requirements. However, many predictions of fundamental limits to scaling have already proven wrong. Creative engineers and material scientists have billions of dollars to gain by getting ahead of their competitors. In the early 1990s, experts agreed that scaling would continue for at least a decade but that beyond that point the future was murky. In 2009, we still believe that Moore’s Law will continue for at least another decade. The future is yours to invent. 1.2 Preview As the number of transistors on a chip has grown exponentially, designers have come to rely on increasing levels of automation to seek corresponding productivity gains. Many designers spend much of their effort specifying functions with hardware description lan- guages and seldom look at actual transistors. Nevertheless, chip design is not software engineering. Addressing the harder problems requires a fundamental understanding of cir- cuit and physical design. Therefore, this book focuses on building an understanding of integrated circuits from the bottom up. In this chapter, we will take a simplified view of CMOS transistors as switches. With this model we will develop CMOS logic gates and latches. CMOS transistors are mass- produced on silicon wafers using lithographic steps much like a printing press process. We will explore how to lay out transistors by specifying rectangles indicating where dopants should be diffused, polysilicon should be grown, metal wires should be deposited, and contacts should be etched to connect all the layers. By the middle of this chapter, you will understand all the principles required to design and lay out your own simple CMOS chip. The chapter concludes with an extended example demonstrating the design of a simple 8- bit MIPS microprocessor chip. The processor raises many of the design issues that will be developed in more depth throughout the book. The best way to learn VLSI design is by doing it. A set of laboratory exercises are available at www.cmosvlsi.com to guide you through the design of your own microprocessor chip. 1.3 MOS Transistors Silicon (Si), a semiconductor, forms the basic starting material for most integrated circuits [Tsividis99]. Pure silicon consists of a three-dimensional lattice of atoms. Silicon is a Group IV element, so it forms covalent bonds with four adjacent atoms, as shown in Fig- ure 1.7(a). The lattice is shown in the plane for ease of drawing, but it actually forms a cubic crystal. As all of its valence electrons are involved in chemical bonds, pure silicon is a poor conductor. The conductivity can be raised by introducing small amounts of impuri- ties, called dopants, into the silicon lattice. A dopant from Group V of the periodic table, such as arsenic, has five valence electrons. It replaces a silicon atom in the lattice and still bonds to four neighbors, so the fifth valence electron is loosely bound to the arsenic atom, as shown in Figure 1.7(b). Thermal vibration of the lattice at room temperature is enough to set the electron free to move, leaving a positively charged As+ ion and a free electron. The free electron can carry current so the conductivity is higher. We call this an n-type  1.3 MOS Transistors 7 Si Si Si Si Si - Si Si Si Si + + - Si Si Si Si As Si Si B Si Si Si Si Si Si Si Si Si Si (a) (b) (c) FIGURE 1.7 Silicon lattice and dopant atoms semiconductor because the free carriers are negatively charged electrons. Similarly, a Group III dopant, such as boron, has three valence electrons, as shown in Figure 1.7(c). The dopant atom can borrow an electron from a neighboring silicon atom, which in turn becomes short by one electron. That atom in turn can borrow an electron, and so forth, so the missing electron, or hole, can propagate about the lattice. The hole acts as a positive carrier so we call this a p-type semiconductor. A junction between p-type and n-type silicon is called a diode, as shown in Figure 1.8. When the voltage on the p-type semiconductor, called the anode, is raised above the n- p-type n-type type cathode, the diode is forward biased and current flows. When the anode voltage is less than or equal to the cathode voltage, the diode is reverse biased and very little current flows. Anode Cathode A Metal-Oxide-Semiconductor (MOS) structure is created by superimposing several layers of conducting and insulating materials to form a sandwich-like structure. These structures are manufactured using a series of chemical processing steps involving oxidation FIGURE 1.8 of the silicon, selective introduction of dopants, and deposition and etching of metal wires p-n junction diode structure and symbol and contacts. Transistors are built on nearly flawless single crystals of silicon, which are available as thin flat circular wafers of 15–30 cm in diameter. CMOS technology provides two types of transistors (also called devices): an n-type transistor (nMOS) and a p-type transistor (pMOS). Transistor operation is controlled by electric fields so the devices are also called Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) or simply FETs. Cross-sections and symbols of these transistors are shown in Figure 1.9. The n+ and p+ regions indicate heavily doped n- or p-type silicon. Source Gate Drain Source Gate Drain Polysilicon SiO2 n+ n+ p+ p+ p bulk Si n bulk Si (a) (b) FIGURE 1.9 nMOS transistor (a) and pMOS transistor (b)  8 Chapter 1 Introduction Each transistor consists of a stack of the conducting gate, an insulating layer of silicon dioxide (SiO2, better known as glass), and the silicon wafer, also called the substrate, body, or bulk. Gates of early transistors were built from metal, so the stack was called metal- oxide-semiconductor, or MOS. Since the 1970s, the gate has been formed from polycrys- talline silicon (polysilicon), but the name stuck. (Interestingly, metal gates reemerged in 2007 to solve materials problems in advanced manufacturing processes.) An nMOS tran- sistor is built with a p-type body and has regions of n-type semiconductor adjacent to the gate called the source and drain. They are physically equivalent and for now we will regard them as interchangeable. The body is typically grounded. A pMOS transistor is just the opposite, consisting of p-type source and drain regions with an n-type body. In a CMOS technology with both flavors of transistors, the substrate is either n-type or p-type. The other flavor of transistor must be built in a special well in which dopant atoms have been added to form the body of the opposite type. The gate is a control input: It affects the flow of electrical current between the source and drain. Consider an nMOS transistor. The body is generally grounded so the p–n junc- tions of the source and drain to body are reverse-biased. If the gate is also grounded, no current flows through the reverse-biased junctions. Hence, we say the transistor is OFF. If the gate voltage is raised, it creates an electric field that starts to attract free electrons to the underside of the Si–SiO2 interface. If the voltage is raised enough, the electrons out- number the holes and a thin region under the gate called the channel is inverted to act as an n-type semiconductor. Hence, a conducting path of electron carriers is formed from source to drain and current can flow. We say the transistor is ON. For a pMOS transistor, the situation is again reversed. The body is held at a positive voltage. When the gate is also at a positive voltage, the source and drain junctions are reverse-biased and no current flows, so the transistor is OFF. When the gate voltage is low- ered, positive charges are attracted to the underside of the Si–SiO2 interface. A sufficiently low gate voltage inverts the channel and a conducting path of positive carriers is formed from source to drain, so the transistor is ON. Notice that the symbol for the pMOS transistor has a bubble on the gate, indicating that the transistor behavior is the opposite of the nMOS. The positive voltage is usually called VDD or POWER and represents a logic 1 value in digital circuits. In popular logic families of the 1970s and 1980s, VDD was set to 5 volts. Smaller, more recent transistors are unable to withstand such high voltages and have used supplies of 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 1.0 V, and so forth. The low voltage is called GROUND (GND) or VSS and represents a logic 0. It is normally 0 volts. In summary, the gate of an MOS transistor controls the flow of current between the source and drain. Simplifying this to the extreme allows the MOS transistors to be viewed as simple ON/OFF switches. When the gate of an nMOS transistor is 1, the transistor is ON and there g=0 g=1 is a conducting path from source to drain. When the gate is low, the nMOS transistor is OFF and almost d d d zero current flows from source to drain. A pMOS nMOS g OFF ON transistor is just the opposite, being ON when the s s s gate is low and OFF when the gate is high. This switch model is illustrated in Figure 1.10, where g, s, d d d and d indicate gate, source, and drain. This model pMOS g ON OFF will be our most common one when discussing cir- s s cuit behavior. s FIGURE 1.10 Transistor symbols and switch-level models  1.4 CMOS Logic 9 1.4 CMOS Logic 1.4.1 The Inverter Figure 1.11 shows the schematic and symbol for a CMOS inverter or NOT gate using one VDD nMOS transistor and one pMOS transistor. The bar at the top indicates VDD and the trian- gle at the bottom indicates GND. When the input A is 0, the nMOS transistor is OFF and A Y the pMOS transistor is ON. Thus, the output Y is pulled up to 1 because it is connected to VDD but not to GND. Conversely, when A is 1, the nMOS is ON, the pMOS is OFF, and Y is pulled down to ‘0.’ This is summarized in Table 1.1. GND (a) TABLE 1.1 Inverter truth table A Y A Y 0 1 (b) 1 0 FIGURE 1.11 Inverter schematic 1.4.2 The NAND Gate (a) and symbol (b) Y = A Figure 1.12(a) shows a 2-input CMOS NAND gate. It consists of two series nMOS tran- sistors between Y and GND and two parallel pMOS transistors between Y and VDD. If either input A or B is 0, at least one of the nMOS transistors will be OFF, breaking the path from Y to GND. But at least one of the pMOS transistors will be ON, creating a path from Y to VDD. Hence, the output Y will be 1. If both inputs are 1, both of the nMOS Y A transistors will be ON and both of the pMOS transistors will be OFF. Hence, the output will be 0. The truth table is given in Table 1.2 and the symbol is shown in Figure 1.12(b). B Note that by DeMorgan’s Law, the inversion bubble may be placed on either side of the gate. In the figures in this book, two lines intersecting at a T-junction are connected. Two (a) lines crossing are connected if and only if a dot is shown. TABLE 1.2 NAND gate truth table (b) A B Pull-Down Network Pull-Up Network Y 0 0 OFF ON 1 FIGURE 1.12 2-input NAND gate schematic (a) and symbol 0 1 OFF ON 1 (b) Y = A · B 1 0 OFF ON 1 1 1 ON OFF 0 k-input NAND gates are constructed using k series nMOS transistors and k parallel Y A pMOS transistors. For example, a 3-input NAND gate is shown in Figure 1.13. When any B of the inputs are 0, the output is pulled high through the parallel pMOS transistors. When C all of the inputs are 1, the output is pulled low through the series nMOS transistors. FIGURE 1.13 3-input NAND 1.4.3 CMOS Logic Gates gate schematic Y = A · B · C The inverter and NAND gates are examples of static CMOS logic gates, also called comple- mentary CMOS gates. In general, a static CMOS gate has an nMOS pull-down network to connect the output to 0 (GND) and pMOS pull-up network to connect the output to 1 (VDD), as shown in Figure 1.14. The networks are arranged such that one is ON and the other OFF for any input pattern.  10 Chapter 1 Introduction The pull-up and pull-down networks in the inverter each consist of a single transistor. The NAND gate uses a series pull-down network and a parallel pull- pMOS up network. More elaborate networks are used for more complex gates. Two or pull-up network more transistors in series are ON only if all of the series transistors are ON. Two or more transistors in parallel are ON if any of the parallel transistors are Inputs ON. This is illustrated in Figure 1.15 for nMOS and pMOS transistor pairs. Output By using combinations of these constructions, CMOS combinational gates can be constructed. Although such static CMOS gates are most widely used, nMOS Chapter 9 explores alternate ways of building gates with transistors. pull-down In general, when we join a pull-up network to a pull-down network to network form a logic gate as shown in Figure 1.14, they both will attempt to exert a logic level at the output. The possible levels at the output are shown in Table 1.3. From this table it can be seen that the output of a CMOS logic gate can be in FIGURE 1.14 General logic gate using pull-up and pull-down networks four states. The 1 and 0 levels have been encountered with the inverter and NAND gates, where either the pull-up or pull-down is OFF and the other structure is ON. When both pull-up and pull-down are OFF, the high- impedance or floating Z output state results. This is of importance in multiplexers, memory elements, and tristate bus drivers. The crowbarred (or contention) X level exists when both pull-up and pull-down are simultaneously turned ON. Contention between the two net- works results in an indeterminate output level and dissipates static power. It is usually an unwanted condition. a a a a a 0 0 1 1 g1 g2 0 1 0 1 b b b b b (a) OFF OFF OFF ON a a a a a 0 0 1 1 g1 g2 0 1 0 1 b b b b (b) ON OFF OFF OFF a a a a a g1 g2 0 0 0 1 1 0 1 1 b b b b b (c) OFF ON ON ON a a a a a g1 g2 0 0 0 1 1 0 1 1 b b b b b (d) ON ON ON OFF FIGURE 1.15 Connection and behavior of series and parallel transistors  1.4 CMOS Logic 11 TABLE 1.3 Output states of CMOS logic gates pull-up OFF pull-up ON pull-down OFF Z 1 pull-down ON 0 crowbarred (X) 1.4.4 The NOR Gate A 2-input NOR gate is shown in Figure 1.16. The nMOS transistors are in parallel to pull the output low when either input is high. The pMOS transistors are in series to pull the A output high when both inputs are low, as indicated in Table 1.4. The output is never crow- B barred or left floating. Y TABLE 1.4 NOR gate truth table A B Y (a) 0 0 1 0 1 0 1 0 0 (b) 1 1 0 FIGURE 1.16 2-input NOR gate schematic (a) and symbol (b) Y = A + B Example 1.1 Sketch a 3-input CMOS NOR gate. SOLUTION: Figure 1.17 shows such a gate. If any input is high, the output is pulled low A through the parallel nMOS transistors. If all inputs are low, the output is pulled high B through the series pMOS transistors. C Y 1.4.5 Compound Gates A compound gate performing a more complex logic function in a single stage of logic is FIGURE 1.17 3-input NOR formed by using a combination of series and parallel switch structures. For example, the gate schematic Y = A + B + C derivation of the circuit for the function Y = (A · B) + (C · D) is shown in Figure 1.18. This function is sometimes called AND-OR-INVERT-22, or AOI22 because it per- forms the NOR of a pair of 2-input ANDs. For the nMOS pull-down network, take the uninverted expression ((A · B) + (C · D)) indicating when the output should be pulled to ‘0.’ The AND expressions (A · B) and (C · D) may be implemented by series connections of switches, as shown in Figure 1.18(a). Now ORing the result requires the parallel con- nection of these two structures, which is shown in Figure 1.18(b). For the pMOS pull-up network, we must compute the complementary expression using switches that turn on with inverted polarity. By DeMorgan’s Law, this is equivalent to interchanging AND and OR operations. Hence, transistors that appear in series in the pull-down network must appear in parallel in the pull-up network. Transistors that appear in parallel in the pull- down network must appear in series in the pull-up network. This principle is called con- duction complements and has already been used in the design of the NAND and NOR gates. In the pull-up network, the parallel combination of A and B is placed in series with the parallel combination of C and D. This progression is evident in Figure 1.18(c) and Figure 1.18(d). Putting the networks together yields the full schematic (Figure 1.18(e)). The symbol is shown in Figure 1.18(f ).  12 Chapter 1 Introduction A C A C B D B D (a) (b) C D A B C D A B (c) (d) C D A A B B Y Y C A C D B D (e) (f) FIGURE 1.18 CMOS compound gate for function Y = (A · B) + (C · D) This AOI22 gate can be used as a 2-input inverting multiplexer by connecting C = A as a select signal. Then, Y = B if C is 0, while Y = D if C is 1. Section 1.4.8 shows a way to improve this multiplexer design. A Example 1.2 B Sketch a static CMOS gate computing Y = (A + B + C) · D. C D Y SOLUTION: Figure 1.19 shows such an OR-AND-INVERT-3-1 (OAI31) gate. The D nMOS pull-down network pulls the output low if D is 1 and either A or B or C are 1, A B C so D is in series with the parallel combination of A, B, and C. The pMOS pull-up net- work is the conduction complement, so D must be in parallel with the series combina- FIGURE 1.19 tion of A, B, and C. CMOS compound gate for function Y = (A + B + C) · D 1.4.6 Pass Transistors and Transmission Gates The strength of a signal is measured by how closely it approximates an ideal voltage source. In general, the stronger a signal, the more current it can source or sink. The power sup- plies, or rails, (VDD and GND) are the source of the strongest 1s and 0s. An nMOS transistor is an almost perfect switch when passing a 0 and thus we say it passes a strong 0. However, the nMOS transistor is imperfect at passing a 1. The high voltage level is somewhat less than VDD, as will be explained in Section 2.5.4. We say it passes a degraded or weak 1. A pMOS transistor again has the opposite behavior, passing strong 1s but degraded 0s. The transistor symbols and behaviors are summarized in Figure 1.20 with g, s, and d indicating gate, source, and drain. When an nMOS or pMOS is used alone as an imperfect switch, we sometimes call it a pass transistor. By combining an nMOS and a pMOS transistor in parallel (Figure 1.21(a)), we obtain a switch that turns on when a 1 is applied to g (Figure 1.21(b)) in which 0s and 1s are both passed in an acceptable fashion (Figure 1.21(c)). We term this a transmission gate or pass gate. In a circuit where only a 0 or a 1 has to be passed, the appro- priate transistor (n or p) can be deleted, reverting to a single nMOS or pMOS device.  1.4 CMOS Logic 13 g g=0 Input g = 1 Output nMOS s d 0 strong 0 s d g=1 g=1 s d 1 degraded 1 (a) (b) (c) g g=0 Input Output g=0 pMOS s d 0 degraded 0 s d g=1 g=0 s d 1 strong 1 (d) (e) (f) FIGURE 1.20 Pass transistor strong and degraded outputs Note that both the control input and its complement are required by the transmission gate. This is called double rail logic. Some circuit symbols for the transmission gate are shown in Figure 1.21(d).1 None are easier to draw than the simple schematic, so we will use the schematic version to represent a transmission gate in this book. In all of our examples so far, the inputs drive the gate terminals of nMOS transistors in the pull-down network and pMOS transistors in the complementary pull-up network, as was shown in Figure 1.14. Thus, the nMOS transistors only need to pass 0s and the pMOS only pass 1s, so the output is always strongly driven and the levels are never degraded. This is called a fully restored logic gate and simplifies circuit design considerably. In contrast to other forms of logic, where the pull-up and pull-down switch networks have to be ratioed in some manner, static CMOS gates operate correctly independently of the physical sizes of the transistors. Moreover, there is never a path through ‘ON’ transistors from the 1 to the 0 supplies for any combination of inputs (in contrast to single-channel MOS, GaAs technologies, or bipolar). As we will find in subsequent chapters, this is the basis for the low static power dissipation in CMOS. Input Output g g = 0, gb = 1 g = 1, gb = 0