Lecture 01 Introduction to Microprocessor PDF

Introduction to Microprocessor Dr. Hassanein Shaban Ahmed DELTA TECHNOLOGICAL UNIVERSITY Faculty of Technological Industry & Energy 1 Microcomputer Architecture  Introduction Writing a program in assembly language requires knowledge about the working of the main CPU...

Introduction to Microprocessor Dr. Hassanein Shaban Ahmed DELTA TECHNOLOGICAL UNIVERSITY Faculty of Technological Industry & Energy 1 Microcomputer Architecture  Introduction Writing a program in assembly language requires knowledge about the working of the main CPU components and the details of its instruction set. An explanation of the basic hardware : bit, bytes, registers, memory, microprocessor, and buses is provided in this lecture. The instruction set are listed in the rest lectures.  Components of a Microcomputer system. A microcomputer contains a microprocessor, but also contains other circuits such as memory devices to store information, interface adapters to connect it with the outside world, and a clock circuit to act as a master timer for the system 2 Dr. Hassanein Shaban Ahmed Major components of Microcomputer Clock Microprocessor Memory Interface adapter Input/Output Device A Basic Microcomputer 3 Dr. Hassanein Shaban Ahmed A simple computer model is given by the following: Chapter 2 4 The CPU is the heart of the computer, most of computations occur inside the CPU. RAM is a place to where the programs are loaded in order to be executed. The system bus connects the various components of a computer. 5 Dr. Hassanein Shaban Ahmed Relation between Memory & CPU The memory circuits are usually organized into groups that can store eight bits which its called byte. Each memory byte is identified by a number that is called its address, like the street address of a house. The first memory byte has address 0. The data stored in a memory byte are called its contents. The main difference between address and contents 1. The address of memory byte “location” is fixed but the contents of memory location can be changed 2. The contents of a memory location are always 8-bits, the number of bits in an address depends on the processor. For example, the Intel 8086 microprocessor assigns a 20-bit address, and the Intel 80286 microprocessor uses a 24-bit address 6 Dr. Hassanein Shaban Ahmed  Relation between Memory & CPU Any Byte has a content and an address Byte Content Byte Address changed Fixed Contain 8 binary digits No. of digits in it is changed Repeated (more than one byte unique contain the same value) No. of bytes the processor can access depending on the No. of bits the address(n). It is equal 2n 7 Dr. Hassanein Shaban Ahmed  5- System Buses There are 3 types of buses – Control Bus – Address Bus – Data Bus To Read the contents of a memory location – CPU put address of the memory location on the address bus – Received the data on the data bus – A control signal send in the control bus to inform memory to perform a read Chapter 1 8  Memory Capacity Example: Suppose a processor uses 20-bits for address. How many memory locations can be accessed. Solution: The number of bits used in the address determines the number of memory locations that can be accessed by the precursor a bit can have two possible values, so in a 20-bit address there can be 220 =1,048,576 or 1 megabyte Memory Address Binary Contents 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 1 3 2 1 0 0 0 0 0 0 1 0 0 The organization of memory locations 9 Dr. Hassanein Shaban Ahmed Instruction Execution Any machine instruction has two parts:  Opcode : to specify the type of operation.  Operands : which are often given as memory address to the data The microprocessor goes through the following steps to execute a machine instruction (fetch and execute cycle) Fetch cycle  Fetch an instruction from memory  Decode the instruction to determine the type of operation Execute cycle  Retrieve data from memory if necessary  Perform the operation on the data  Store the result in memory if needed 10 Dr. Hassanein Shaban Ahmed Execution a Program To understand how the microprocessor operates, consider the following sample of a program Example LDA 7 ADD 10 HLT st 1000 0110 Opcode for LDA 1 instruction LDA 7 0000 0111 Operand (7) 1000 1011 Opcode for ADD st 2 instruction ADD 10 0000 1010 Operand (10) st 3 instruction HLT 0011 1110 Opcode for HLT To Read the contents of a memory location 1. CPU put address of the memory location on the address bus 2. Received the data on the data bus 3. A control signal send in the control bus to inform memory to perform a read 11 Dr. Hassanein Shaban Ahmed  Execution a Program Microprocessor  Before a Program can be run, UNIT Arithmetic Logic Unit (ALU) it must be placed in memory Controller  To begin executing the Accumulator Sequencer program, the program counter must be set to the Instruction 0 0 0 0 0 0 0 0 Program Decoder address of the first instruction Counter i.e 0000 0000 zero Address Data Register Register MEMORY Binary Assembly Address Contents Code 0000 0000 1000 0110 LDA 0000 0001 0000 0111 7 0000 0010 1000 1011 ADD 0000 0011 0000 1010 10 0000 0100 0011 1110 HLT 12 Dr. Hassanein Shaban Ahmed  Fetch Cycle of LDA instruction Microprocessor 1. The contents of the program UNIT Arithmetic Logic Unit (ALU) counter (0000 0000) are Controller transferred to the address Sequencer Accumulator register Instruction Program 0 0 0 0 0 0 0 0 Decoder Counter Address Data 0 0 0 0 0 0 0 0 Register Register MEMORY Binary Assembly Address Contents Code 0000 0000 1000 0110 LDA 0000 0001 0000 0111 7 0000 0010 1000 1011 ADD 0000 0011 0000 1010 10 0000 0100 0011 1110 HLT 13 Dr. Hassanein Shaban Ahmed  Fetch Cycle of LDA instruction Microprocessor 2. The program counter is UNIT Arithmetic Logic Unit (ALU) incremented by one Controller Sequencer Accumulator Instruction Program 0 0 0 0 0 0 0 1 Decoder Counter Address Data 0 0 0 0 0 0 0 0 Register Register MEMORY Binary Assembly Address Contents Code 0000 0000 1000 0110 LDA 0000 0001 0000 0111 7 0000 0010 1000 1011 ADD 0000 0011 0000 1010 10 0000 0100 0011 1110 HLT 14 Dr. Hassanein Shaban Ahmed  Fetch Cycle of LDA instruction Microprocessor 3. The address is placed on the UNIT Arithmetic Logic Unit (ALU) address bus Controller Sequencer Accumulator Instruction Program 0 0 0 0 0 0 0 1 Decoder Counter Address Data 0 0 0 0 0 0 0 0 Register Register Address bus MEMORY Binary Assembly Address Contents Code 0000 0000 1000 0110 LDA 0000 0001 0000 0111 7 0000 0010 1000 1011 ADD 0000 0011 0000 1010 10 0000 0100 0011 1110 HLT 15 Dr. Hassanein Shaban Ahmed  Fetch Cycle of LDA instruction Microprocessor 4. The contents of the selected UNIT Arithmetic Logic Unit (ALU) memory location are Controller transferred to the data Sequencer Accumulator register Instruction Program 0 0 0 0 0 0 0 1 Decoder Counter Address Data 0 0 0 0 0 0 0 0 Register 1 0 0 0 0 1 1 0 Register MEMORY Data bus Binary Assembly Address Contents Code 0000 0000 1000 0110 LDA 0000 0001 0000 0111 7 0000 0010 1000 1011 ADD 0000 0011 0000 1010 10 0000 0100 0011 1110 HLT 16 Dr. Hassanein Shaban Ahmed  Fetch Cycle of LDA instruction Microprocessor 5. The contents of the data register UNIT Arithmetic Logic Unit (ALU) are decoded by the instruction Controller decoder. The instruction Sequencer Accumulator decoder informs the controller LDA sequencer to produce the Instruction Program 0 0 0 0 0 0 0 1 Decoder necessary control signal to carry Counter out the instruction Address Data 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 Register Register MEMORY Binary Assembly Address Contents Code 0000 0000 1000 0110 LDA 0000 0001 0000 0111 7 0000 0010 1000 1011 ADD 0000 0011 0000 1010 10 0000 0100 0011 1110 HLT 17 Dr. Hassanein Shaban Ahmed  Execute Cycle of LDA instruction Microprocessor 1. The contents of the program UNIT Arithmetic Logic Unit (ALU) counter (0000 0001) are Controller transferred to the address Sequencer Accumulator register Instruction Program 0 0 0 0 0 0 0 1 Decoder Counter Address Data 0 0 0 0 0 0 0 1 Register 1 0 0 0 0 1 1 0 Register MEMORY Binary Assembly Address Contents Code 0000 0000 1000 0110 LDA 0000 0001 0000 0111 7 0000 0010 1000 1011 ADD 0000 0011 0000 1010 10 0000 0100 0011 1110 HLT 18 Dr. Hassanein Shaban Ahmed  Execute Cycle of LDA instruction Microprocessor 2. The program counter is UNIT Arithmetic Logic incremented by one for the Unit (ALU) next fetch cycle Controller Sequencer Accumulator Instruction 0 0 0 0 0 0 1 0 Program Decoder Counter Address Data 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 Register Register MEMORY Binary Assembly Address Contents Code 0000 0000 1000 0110 LDA 0000 0001 0000 0111 7 0000 0010 1000 1011 ADD 0000 0011 0000 1010 10 0000 0100 0011 1110 HLT 19 Dr. Hassanein Shaban Ahmed  Execute Cycle of LDA instruction Microprocessor 3. The address of the operand is UNIT Arithmetic Logic Unit (ALU) placed on the address bus Controller Sequencer Accumulator Instruction Program 0 0 0 0 0 0 1 0 Decoder Counter Address Data 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 Register Register Address bus MEMORY Binary Assembly Address Contents Code 0000 0000 1000 0110 LDA 0000 0001 0000 0111 7 0000 0010 1000 1011 ADD 0000 0011 0000 1010 10 0000 0100 0011 1110 HLT 20 Dr. Hassanein Shaban Ahmed  Execute Cycle of LDA instruction Microprocessor 4. The contents of the selected UNIT Arithmetic Logic Unit (ALU) memory location are Controller transferred to the data Sequencer Accumulator 0 0 0 0 0 1 1 1 register and also transferred into the accumulator Instruction Program 0 0 0 0 0 0 0 1 Decoder Counter Address Data 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Register Register MEMORY Data bus Binary Assembly Address Contents Code 0000 0000 1000 0110 LDA 0000 0001 0000 0111 7 0000 0010 1000 1011 ADD 0000 0011 0000 1010 10 0000 0100 0011 1110 HLT 21 Dr. Hassanein Shaban Ahmed  Fetch Cycle of ADD instruction Microprocessor 1. The contents of the program counter UNIT Arithmetic Logic (0000 0010) are transferred to the Unit (ALU) address register Controller 2. The program counter is incremented by Accumulator 0 0 0 0 0 1 1 1 Sequencer one ADD 3. The address is placed on the address bus 2 Instruction Program 4. The contents of the selected memory 0 0 0 0 0 0 1 0 Counter Decoder location are transferred to the data 1 5 register Address Data 0 0 0 0 0 0 1 0 1 0 0 0 1 1 0 1 Register Register 5. The contents of the data register are Address decoded by the instruction decoder. The bus instruction decoder informs the 3 MEMORY Data bus controller sequencer to produce the Address Binary Assembly Contents Code necessary control signal to carry out the 0000 0000 1000 0110 LDA 0000 0001 0000 0111 7 instruction 0000 0010 1000 1011 ADD 0000 0011 0000 1010 10 4 0000 0100 0011 1110 HLT 22 Dr. Hassanein Shaban Ahmed  Execute Cycle of ADD instruction Microprocessor 1. The contents of the program counter UNIT Arithmetic Logic 5a (0000 0011) are transferred to the address Unit (ALU) register 5b Controller 2. The program counter is incremented by Accumulator 0 0 0 1 0 0 0 1 Sequencer one for the next fetch cycle 3. The address of operand is placed on the 2 Instruction Program address bus 0 0 0 0 0 0 1 1 Counter Decoder 4. The operand (1010) is transferred to the 1 data register Address Data 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 Register Register 5a. The operand (1010) is transferred into one Address input of the ALU bus 5b. Simultaneously, The other operand (710) 3 MEMORY Data bus is transferred from the accumulator to Address Binary Assembly Contents Code the other input of the ALU 0000 0000 1000 0110 LDA 0000 0001 0000 0111 7 6. The ALU adds the two operands. The 0000 0010 1000 1011 ADD 4 sum (1710) is loaded into the accumulator 0000 0011 0000 1010 10 0000 0100 0011 1110 HLT 23 Dr. Hassanein Shaban Ahmed  Fetch and Execute Cycle of HLT instruction Microprocessor Fetch cycle UNIT Arithmetic Logic Unit (ALU) 1. The contents of the program counter (0000 0100) are transferred to the Controller Sequencer address register Accumulator 0 0 0 1 0 0 0 1 2. The program counter is incremented by HLT one 2 Instruction Program 3. The address is placed on the address bus 0 0 0 0 0 1 0 0 Decoder Counter 4. The contents of the selected memory 1 5 Address Data location are transferred to the data 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 Register Register register Address 5. The contents of the data register are bus decoded by the instruction decoder. 3 MEMORY Data bus Binary Assembly Address Contents Code Execute cycle 0000 0000 0000 0001 1000 0110 0000 0111 LDA 7 1. The execution of the HLT instruction is 0000 0010 1000 1011 ADD 4 0000 0011 0000 1010 10 very simple. The instruction sequencer 0000 0100 0011 1110 HLT stops producing control signals then all computer operations stop. 24 Dr. Hassanein Shaban Ahmed  Machine Cycle A clock circuit controls the microprocessor by generating a train of clock pulses as shown Voltage Time One machine cycle A one machine cycle can be defined as the minimum time required to fetch a data from memory[1,12],[3,76]. If the microprocessor speed is one megahertz 1MHz, the machine cycle is expressed as: T=1/f =1/1000000 =1 micro second Thus, the fetch cycle of an instruction requires one machine cycle. In inherent and immediate addressing modes ,the execute cycle also requires one machine cycle. Therefore, the minimum time required to fetch and execute any instruction is two machine cycle. As will see later in a lecture of addressing modes 25 Dr. Hassanein Shaban Ahmed  Programming languages We know that, the operations of the computer’s hardware are controlled by its software. The software program is written by one of the following programming languages:  Machine language A microprocessor can only execute machine language instructions. As we’ve seen, they are bit strings from 0 or 1.  Assembly language A more convenient language to use is the assembly language. In assembly language, we use symbolic names to represent operations, register, and memory location. Such as, mov ax,7 A program written in assembly language must be converted to machine language before the microprocessor can execute it. The assembler is used to translated from assembly language into machine language 26 Dr. Hassanein Shaban Ahmed  Programming languages  High-Level language Different high-level languages are designed for different applications, but they generally allow programmers to write programs that look more like natural language text than is possible in assembly language A program called a compiler is needed to translate a high-level language program into machine code  Advantages of High-Level Language 1. Because high-level languages are closer to natural languages, it easer to convert a natural language algorithm to a high-level language program than to an assembly language program 2. Assembly language program generally contains more statements than an equivalent high-level language program. So more time is needed to code the assembly language program 3. Assembly instruction sets are unique for each type of the microprocessor, but high-level language program can be executed on any machine 27 Dr. Hassanein Shaban Ahmed Programming in Assembly Language When assembly language is needed? to write programs in which speed or size are critical or no high- level language is available (e.g., programming embedded computer: a computer that is incorporated in another device). to exploit hardware features and specialized instructions that have no analogues in high-level languages. Drawbacks of assembly language Inherently machine-specific and must be totally rewritten to run on another computer architecture. Assembly programs are longer and they lack structure. Longer programs are more difficult to read and understand and hence they are likely to have more bugs. Programmers are more productive using high-level languages.  The 8086 Microprocessors Execution Unit EU Bus Interface Unit BIU AX BX General registers CX Internal Block Diagram of The 8086 Microprocessor DX CS SP DS BP SS SI ES DI IP External Bus Internal Bus Bus Controller Logic Temporary registers ALU Instruction queue Flags 29 Dr. Hassanein Shaban Ahmed Chapter 1&3  Intel 8086 Microprocessors Organization The 8086 microprocessor is organized into main components: the execution unit EU and the bus interface unit BIU. ♣ The purpose of the execution unit is to execute instructions. It contains ALU and a eight registers (AX, BX, CX, DX, SP, BP, SI, and DI) for storing date. In addition, the EU contains temporary registers for holding operands for the ALU, and the Flags register ♣ The bus interface unit BIU facilitates communication between the EU and memory or I/O devices. It also contains a five registers (CS, DS, ES, SS, and IP); they hold the address of memory locations. ♣ The EU and BIU are connected by an internal bus. While the EU is executing an instruction, the BIU fetches up to 6 bytes (8086) of the next instruction. This operation is called instruction prefetch. 30 Dr. Hassanein Shaban Ahmed Chapter 1&3 Intel 8086 Microprocessors Organization Notes ♣ Intel implemented the concepts of pipelining in the 8086 by splitting the internal structure of the microprocessor into two sections the EU and BIU. These two units work simultaneously. ♣ The BIU of 8086 contains a buffer or instruction queue. ♣ A register is like a memory location except that we normally refer to it by a name rather than a number ♣ Because registers are located inside the CPU, they are much faster than memory. What is the difference between Registers and Memory locations? 31 Dr. Hassanein Shaban Ahmed Chapter 1&3  8086 Registers AX AH Data Registers AL BX BH BL The 8086 has four general date CX CH CL registers; the address registers are DX DH DL divided into segment, pointer, and Segment Registers CS index registers; and the status DS register is called the Flags register. In SS total, there are fourteen 16 bit ES registers Pointer and Index Registers 8086 Registers SI DI SP BP IP Flags Register 32 Dr. Hassanein Shaban Ahmed Chapter 1&3  Data Registers : AX, BX, CX, DX These four registers are available to the programmer for general data manipulation, also they perform special functions such as: ♣ AX ( accumulator register ) AX is used for I/O operations and most arithmetic operations(+,-,*,/) ♣ BX ( Base register ) Can be used as an index to extend addressing. Also used for basic computations (+, -) ♣ CX ( Counter register ) CX is used as a counter in loop operation ♣ DX ( Data register ) DX is used to point data in I/O operation 33 Dr. Hassanein Shaban Ahmed Chapter 1&3  Flags Register The Flags register is an individual 16 bits reflect the result of a computation. There are two kinds of flags: ♣ Status flags : many instructions involving comparison and arithmetic change the status flags (such as ZE zero flag) ♣ Control flags : which enable or disable certain operations of the processor ( such as IF interrupt flag ) Flags Register determines the current state of the processor. 34 Dr. Hassanein Shaban Ahmed Chapter 1&3 Segment Registers CS, DS, SS, ES The address (segment) registers store addresses of instructions and data in memory CS : Code Segment DS : Data Segment SS : Stack Segment ES : Extra Segment A typical assembly language program consists of at least three segments: a code segment, a data segment, and a stack segment. The code segment contains the assembly language instructions that perform the tasks. The data segment is used to store information (data) that needs to be processed by the instructions in the code segment. The stack is used to store information temporarily If a program needs to access a second data segment, it can use the ES register 35 Dr. Hassanein Shaban Ahmed Chapter 1&3 Continued.. Memory..... Code segment area CS register Data segment area DS register Stack segment area SS register.. Each register contains. the starting address... On the 80386 and later Intel processors, there are other Segment registers which have specialized uses: ES, FS, GS registers. 36 Dr. Hassanein Shaban Ahmed Chapter 1&3 Memory Segment A segment is an area of successive memory bytes up to 216 (64kb). Each segment is identified by a segment number, starting with 0. A segment number is 16 bit, so the highest segment number is FFFFh. A memory location may be specified by providing a segment number and an offset, written in the form segment:offset. For example Segment 0 start at address 0000:0000=00000h and ends at 0000:FFFF=0FFFFh. Segment 1 starts at address 0001:0000=00010h and ends at 0001:FFFF==1000Fh In the 8085 there are only 64 kb of memory for all code, data, and stack information, but in the 8086 there can be up to 64kb of memory assigned to each category 37 Dr. Hassanein Shaban Ahmed Chapter 1&3 Logical and Physical address In the Intel 8086, there are three type of addresses: the physical address, the offset address, and the logical address. The physical address is the 20 bit address that is actually put on the address pins of the 8086 microprocessor and decoded by address decoder. This address range from 00000h to FFFFFh for the 8086. The offset address is the location within a 64KB segment range. So the offset range from 0000h to FFFFh. The logical address consists of a segment value and an offset address. To obtain a 20 bit physical address, the 8086 microprocessor first shifts the segment address 4 bit to the left, and then adds the offset. 38 Dr. Hassanein Shaban Ahmed Chapter 1&3 Example If CS=24F6 and IP=634Ah, show 1. The logical address 24F6:634A 2. The offset address 634A And calculate : 3. The physical address 24F60+634A=2B2AA 4. The lower and upper rang of that segment Lower range=24F60+0000=24F60 Upper range=24F60+FFFF=34F5F 39 Dr. Hassanein Shaban Ahmed Chapter 1&3 Pointer and Index Registers: SP, BP, SI, DI The registers SP, BP, SI, and DI normally point (contain the offset address of) memory locations. Unlike segment registers, the pointer and index register can be used in arithmetic and other operations. SP: Stack Pointer The stack pointer register is used in connection with SS for accessing the stack segment. BP: Base Pointer The base pointer register is used primarily to access data on the stack. However, unlike SP, we can also use BP to access data in the other segments SI: Source Index The SI register is used to point the memory locations in the data segment addressed by DS. DI: Destination Index The DI register is used to point the memory locations in the extra segment addressed by ES 40 Dr. Hassanein Shaban Ahmed Chapter 1&3  Instruction Pointer: IP To access instructions in the code segment, the 8086 uses the registers CS and IP. The CS register contains the segment number and the IP contains the offset 41 Dr. Hassanein Shaban Ahmed Chapter 1&3