Lecture 03 Memory Addressing Modes & Program Flow Control PDF

Flag Register and Program Flow Control 1- Introduction The execution of instructions is done in sequential way. In some applications you need to control the program flow. Some instructions (jumps or looping) are necessary to implement this control by making decision. Processor making decision usin...

Flag Register and Program Flow Control 1- Introduction The execution of instructions is done in sequential way. In some applications you need to control the program flow. Some instructions (jumps or looping) are necessary to implement this control by making decision. Processor making decision using Flags. Flags are bits in a Flag register. 2 Dr. Hassanein Shaban Ahmed Chapter 5&6 Flags Register: 3 Dr. Hassanein Shaban Ahmed Chapter 5&6  Flag Register The flag register is a 16-bit register. Although the flag register is 16bits wide, only 9 bits of the flag register are used to making a decision (control Flags) and the other bits are not significant (Status Flags). The rest are either undefined or reserved by Intel.  Status Flags Six of the flags are called conditional or status flags. It reflects a result of a computation i.e. meaning that they indicate some status that resulted after and instruction was executed. These six are located in bits 0,2,4,6,7, and 11 and are called as CF,PF,AF,ZF,SF, and OF.  Control Flags The three reminding flags are sometimes called control flags since they are used to control the operation of instruction before they are executed i.e. enable or disable certain operation of a processor 4 Dr. Hassanein Shaban Ahmed Chapter 5&6  Flag Register The 16 bit of the Flag Register is shown below. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R R R R OF DF IF TF SF ZF U AF U PF U CF Where R Reserved SF Sign flag U Undefined ZF Zero flag OF Overflow AF Auxiliary carry flag DF Direction Flag PF Parity flag IF Interrupt Flags CF Carry flag TF Trap Flag 5 Dr. Hassanein Shaban Ahmed Chapter 5&6  Flag Register/ Status Flags ♣ Bit 0: Carry Flag CF, CF =1 if there is a carry out (in addition) or a borrow into (in subtraction) MSB otherwise CF=0, either from d7 after an 8-bit operation, or from d15 after a 16-bit operation ♣ Bit 2: Parity Flag PF, PF=1, if number of 1’s in a low byte of the result is even, otherwise PF=0 ♣ Bit 4: Auxiliary Carry Flag CF, this flag is set if there is a carry from d3 to d4 otherwise it is cleared. AF is used in binary-coded decimal (BCD) operations 6 Dr. Hassanein Shaban Ahmed Chapter 5&6  Flag Register ♣ Bit 4: Zero Flag ZF, it is set to 1 if the result of arithmetic or logical operation is zero; otherwise it is cleared. ♣ Bit 7: Sign Flag SF, SF=1 if the MSB of the result is 1; it means the result is negative, otherwise SF =0 if the MSB is 0. ♣ Bit 11: Overflow Flag OF, OF=1 if the signed operation is too large causing the high-order bit to overflow into the sign bit. The overflow flag is only used to detect errors in signed arithmetic operations 7 Dr. Hassanein Shaban Ahmed Chapter 5&6 How instructions Affect the Flags Instruction Affects Flags MOV and XCHG No Flags are changed ADD and SUB All flags affected INC and DEC All except CF NEG All flags affected All (CF=1 unless result is 0, OF=1 if word operand is 8000h Or byte operand is 80h 8 Dr. Hassanein Shaban Ahmed Chapter 5&6  Example Show how the flag register is affected by the addition of 38H and 2FH. Solution : MOV BH,38H ADD BH,2FH 0 1 38H 0011 1000 OF SF ZF AF PF CF + 2FH 0010 1111 0 0 0 1 0 0 67H 0110 0111 CF=0 Since there is no carry beyond d7 PF=0 Since there is an odd number of 1’s in the result AF=1 Since there is a carry from d3 to d4 ZF=0 Since the result is not zero SF=0 Since d7 of the result is zero 9 Dr. Hassanein Shaban Ahmed Chapter 5&6  Ex.5.1.model small.stack 100h.CODE MAIN PROC MOV BH,38H ADD BH,2FH MOV AX,4CH INT 21H MAIN ENDP END MAIN 10 Dr. Hassanein Shaban Ahmed Chapter 5&6  Example Show how the flag register is affected by MOV AL,9CH MOV DH,64H ADD AL,DH Solution : 1 1 9CH 1001 1100 OF SF ZF AF PF CF + 64H 0110 0100 1 0 1 1 1 1 00H 0000 0000 CF=1 Since there is a carry beyond d7 PF=1 Since there is an even number of 1’s in the result AF=1 Since there is a carry from d3 to d4 ZF=1 Since the result is zero SF=0 Since d7 of the result is zero 11 Dr. Hassanein Shaban Ahmed Chapter 5&6  Ex. 5.2.model small.stack 100h.CODE MAIN PROC MOV AL,9CH MOV DH,64H ADD AL,DH MOV AX,4CH INT 21H MAIN ENDP END MAIN 12 Dr. Hassanein Shaban Ahmed Chapter 5&6  Example Show how the flag register is affected by MOV AX,34F5H MOV DX,95EBH ADD AX,DX Solution : 34F5H 0011 0100 1111 0101 + 95EBH 1001 0101 1110 1011 CAE0H 1100 1010 1110 0000 CF=0 Since there is no carry beyond d15 OF SF ZF AF PF CF PF=0 Since there is an odd number of 1’s in the result AF=1 Since there is a carry from d3 to d4 0 1 0 1 0 0 ZF=0 Since the result is not zero SF=1 Since d15 of the result is one 13 Dr. Hassanein Shaban Ahmed Chapter 5&6  Ex. 5.3.model small.stack 100h.CODE MAIN PROC MOV BX,34F5H ADD BX,95EBH MOV AX,4CH INT 21H MAIN ENDP END MAIN 14 Dr. Hassanein Shaban Ahmed Chapter 5&6  Ex. 5.4 Show how the flag register is affected by AAAA 1010 1010 1010 1010 + 5556 0101 0101 0101 0110 0000 0000 0000 0000 0000 CF=1 Since there is a carry beyond d15 PF=1 Since there is an even number of 1’s in the result AF=1 Since there is a carry from d3 to d4 ZF=1 Since the result is zero.model small SF=0 Since d15 of the result is zero.stack 100h.CODE MAIN PROC MOV BX,0AAAAH ADD BX,5556H MOV AX,4CH INT 21H MAIN ENDP END MAIN 15 Dr. Hassanein Shaban Ahmed Chapter 5&6 Flow Control Instructions  For assembly language programs to carry out useful tasks, there must be a way to make decisions and repeat sections of code  The jump and loop instructions transfer control to another part of the program. This transfer can be unconditional or conditional 16  Jump and loop Instructions  In assembly we have 2 types of jumps and loops. Unconditional jumps and loops. & conditional jumps and loops.  Unconditional jump instruction unconditionally transfers control to another point in the program. 17 Dr. Hassanein Shaban Ahmed Chapter 5&6 Unconditional Jump : JMP Instruction JMP is an unconditional jump to a label that is usually within the same procedure. The Syntax is JMP destination Example 18 Dr. Hassanein Shaban Ahmed Chapter 5&6 Conditional Jumps  Conditional jump instructions transfer control to another point in the program only when some conditions are true.  The conditional jump instructions can be classified as the following categories 1. Single Flag jumps 2. Register jumps  The syntax of conditional jump instruction is : Jxxx destination_label The conditional-jump instruction takes a single operand containing the target address. If the condition for the jump is true, the next instruction to be executed is the one at destination_label, which may precede or follow the jump instruction itself. If the condition is false, the instruction following the jump is done next. 19 Dr. Hassanein Shaban Ahmed Chapter 5&6 Conditional Jumps All conditional jumps except (JCXZ) use the processor flags for their criteria. Thus, any statement that sets or clears a flag can serve as a test basis for a conditional jump. The jump statement can be any one of a conditional-jump instructions. For Example: JNZ - Jump if zero flag is clear (0) meaning the result of a previous operation was non-zero JC - Jump if a previous operation caused the carry flag to be set (1) JZ - jump to a label if the Zero flag is set 20 Dr. Hassanein Shaban Ahmed Chapter 5&6  Example : Jumps Based on Specific Flags Ex. 5.6.MODEL SMALL.STACK 100h.CODE MAIN PROC MOV AH,2 MOV CX,127 MOV DL,0 PRINT_LOOP: INT 21h INC DL DEC CX JNZ PRINT_LOOP MOV AX,4CH INT 21H MAIN ENDP END MAIN 21 Dr. Hassanein Shaban Ahmed Chapter 5&6 4- Physical memory address To access a physical memory address, the CPU multiplies the segment value by sixteen (10h) and adds the offset portion: Physical address = Segment address*10h + Offset 23 Dr. Hassanein Shaban Ahmed Chapter 4&10 Example: Consider the segmented address: 1000:1F00 To convert this to a physical address: Physical address = Segment address*10 + Offset Physical address = 1000*10 + 1F00 = 10000 + 1F00 = 11F00 24 Dr. Hassanein Shaban Ahmed Chapter 4&10 Exercise: Calculate the Logical address of the following: Suppose the segment is given by 1240h and the physical address is 1256ah Physical address = 1240*10 + offset 1256a = 12400+ offset offset = 1256a-12400 = 016a Logical address = 1240:016a 25 Dr. Hassanein Shaban Ahmed Chapter 4&10  8086 Addressing Modes The microprocessor can access operands (data) in various ways called addressing modes. The 8086 provides a total of seven distinct addressing modes: 1. Register 2. Immediate 3. Direct 4. Register indirect 5. Based relative 6. Indexed relative 7. Based index relative There are different ways to access memory, but the most common addressing modes used are direct addressing mode and indirect addressing mode 26 Dr. Hassanein Shaban Ahmed Chapter 4&10  Register Addressing Mode The register addressing mode involves the use of registers to hold the data to be manipulated. Memory is not accessed when this addressing mode is executed; therefore, it is relatively fast. As example: MOV BX,DX ;copy the content of DX into BX MOV ES,AX ;copy the content of AX into ES ADD AL,BH ;add the content of BH to the content of AL It should be noted that the source and destination registers must match in size. In other words coding “ MOV CL,AX “ will give an error. Since the source is a 16-bit register and the destination is an 8- bit 27 Dr. Hassanein Shaban Ahmed Chapter 4&10 Next  Immediate Addressing Mode In the immediate addressing mode, the source operand is a constant. When the instruction is assembled, the operand comes immediately after the opcode. For this reason, this addressing mode executes quickly. As an example: MOV AX,2550H ;move 2550h into AX MOV CX,625 ;load the decimal value 625 into CX MOV BL,40H ;load 40H into BL In the first two addressing modes, the operands are either inside the microprocessor or tagged along with the instruction which that are not referred to the memory. There are many ways of accessing the data in the data segment as the following of addressing modes. 28 Dr. Hassanein Shaban Ahmed Chapter 4&10 Next  Direct Addressing Mode In the direct addressing mode the data is in some memory locations and the address of the data in memory comes immediately after the instruction. Note that in immediate addressing, the operand itself is provided with the instruction, whereas in direct addressing mode, the address of the operand is provided with the instruction. As an example MOV DL, ;move contents of DS:2400H into DL In this case the physical address is calculated by combining the contents of offset location 2400 with DS, the data segment register. Note, if the absence of the bracket it will give an error since it is interpreted to move 16bit into 8bit 29 Dr. Hassanein Shaban Ahmed Chapter 4&10 Next Cont….Direct Addressing Mode The direct addressing mode consists of a 16 bit constant that specifies the address of the target location. If we don’t specify the segment value, the direct values provide offsets into the data segment. 30 Dr. Hassanein Shaban Ahmed Chapter 4&10 Next  Example Find the physical address of the memory location and its contents after the execution of the following, assuming that DS=1512H. MOV AL,99 MOV ,AL Solution First AL is initialized to 99H, then in line two, the contents of AL are stored to logical address DS:3518 which is 1512:3518. shifting DS left and adding it to the offset gives the physical address of (15120H+3518H=18638H). That means after execution of the second instruction, the memory location with address 18638H will contain the value 99H 31 Dr. Hassanein Shaban Ahmed Chapter 4&10 Next Example: MOV AL,DS:[8088h] ; loads the AL register with a copy of the byte at memory location 8088h in the data segment. MOV DS:[1234h],DL ;stores the value in the DL register to memory location 1234h. Data segment 32 Dr. Hassanein Shaban Ahmed Chapter 4&10  Register indirect Addressing Mode In the register indirect addressing mode, the address of the operand is held by a register. The registers used for this purpose are SI, DI, BP, and BX as a pointer. 33 Dr. Hassanein Shaban Ahmed Chapter 4&10 Next  Cont…indirect Addressing Mode For example MOV AL,[BX] ;moves into AL the contents of the ;memory location pointed to by DS:BX Example : assume that DS=1120, BX=2498, and AX=17FE. Show the contents of memory locations after the execution of MOV [BX],AX Solution The contents of AX moves into memory locations with The logical address DS:BX and DS:BX+1; therefore the physical address starts at DS (shifted left) +BX=13698. Low address 13698Hcontains FE, low byte, and high address 13699H will contain 17, the high byte 34 Dr. Hassanein Shaban Ahmed Chapter 4&10 Next