Instruction set and assembler directives.pdf

8086/8088 Instruction Set and Assembler Directives 43 2.3 INSTRUCTION SET OF 8086/8088 The 8086/8088 instructions are categorised into the following main types. This section explains the function of each of the instructions with su...

8086/8088 Instruction Set and Assembler Directives 43 2.3 INSTRUCTION SET OF 8086/8088 The 8086/8088 instructions are categorised into the following main types. This section explains the function of each of the instructions with suitable examples wherever necessary. (i) Data Copy/Transfer Instructions These types of instructions are used to transfer data from source operand to destination operand. All the store, move, load, exchange, input and output in- structions belong to this category. (ii) Arithmetic and Logical Instructions All the instructions performing arithmetic, logical, incre- ment, decrement, compare and scan instructions belong to this category. (iii) Branch Instructions These instructions transfer control of execution to the specified address. All the call, jump, interrupt and return instructions belong to this class. (iv) Loop Instructions If these instructions have REP prefix with CX used as count register, they can be used to implement unconditional and conditional loops. The LOOP, LOOPNZ and LOOPZ instructions belong to this category. These are useful to implement different loop structures. (v) Machine Control Instructions These instructions control the machine status. NOP, HLT, WAIT and LOCK instructions belong to this class. (vi) Flag Manipulation Instructions All the instructions which directly affect the flag register, come under this group of instructions. Instructions like CLD,STD,CLI,STI, etc. belong to this category of instructions. (vii) Shift and Rotate Instructions These instructions involve the bitwise shifting or rotation in either direction with or without a count in CX. (viii) String Instructions These instructions involve various string manipulation operations like load, move, scan, compare, store, etc. These instructions are only to be operated upon the strings. 2.3.1 Data Copy/Transfer Instructions MOV: Move This data transfer instruction transfers data from one register/memory location to another register/memory location. The source may be any one of the segment registers or other general or special purpose registers or a memory location and, another register or memory location may act as destination. 44 Advanced Microprocessors and Peripherals However, in case of immediate addressing mode, a segment register cannot be a destination register. In other words, direct loading of the segment registers with immediate data is not permitted. To load the seg- ment registers with immediate data, one will have to load any general purpose register with the data and then it will have to be moved to that particular segment register. The following example instructions explain the fact. Example 2.16 Load OS with 5000H. 1. MOV OS, 5000H; Not permitted (invalid) Thus to transfer an immediate data into the segment register, the correct procedure is given below. 2. MOV AX, 5000H MOV OS, AX It may be noted here that both the source and destination operands cannot be memory loca- tions (except for string instructions). Other MOV instruction examples are given below with the corresponding addressing modes. 3. MOV AX, 5000H; Immediate 4. MOV AX, BX; Register 5. MOV AX, [SI]; Indirect 6. MOV AX, [2000H]; Direct 7. MOV AX, 50H[BX]; Based relative, 50H Displacement PUSH: Push to Stack This instruction pushes the contents of the specified register/memory location on to the stack. The stack pointer is decremented by 2, after each execution of the instruction. The actual current stack-top is always occupied by the previously pushed data. Hence, the push operation decrements SP by two and then stores the two byte contents of the operand onto the stack. The higher byte is pushed first and then the lower byte. Thus out of the two decremented stack addresses the higher byte occupies the higher address and the lower byte occupies the lower address. The actual operation takes place as given below SS : SP points to the stack top of 8086 system as shown in Fig. 2.2 and AH, AL contains data to be pushed. Physical SS= 2000H Address SP PUSH AX t t AH AL 55 22 22 H 2 FFFD FFFD 55 H 2 FFFE FFFE xx 2 FFFF FFFF Fig. 2.2 Pushing Data to Stack Memory  8086/8088 Instruction Set and Assembler Directives 45 The sequence of operation as below: 1. Current stack top is already occupied so decrement SP by one then store AH into the address pointed to by SP. 2. Further decrement SP by one and store AL into the location pointed to by SP. Thus SP is decremented by 2 and AH-AL contents are stored in stack memory as shown in Fig. 2.2. Contents of SP points to a new stack top. The examples of these instructions are as follows: Example 2.17 1. PUSH AX 2. PUSH OS 3. PUSH [5000H]; Content of location 5000H and 5001 H in OS are pushed onto the stack POP: Pop from Stack This instruction when executed, loads the specified register/memory location with the contents of the memory location of which the address is formed using the current stack segment and stack pointer as usual. The stack pointer is incremented by 2. The POP instruction serves exactly opposite to the PUSH instruction. 16-bit contents of current stack top are poped into the specified operand as follows. The sequence of operation is as below. 1. Contents of stack top memory location is stored in AL and SP is incremented by one 2. Further contents of memory location pointed to by SP are copied to AH and SP is again incremented by 1 Effectively SP is incremented by 2 and points to next stack top. The examples of these instructions are shown as follows: Example 2.18 l.POP AX 2.POP OS 3. POP [5000HJ Physical SS= 2000H Address SP POP AX t t 22 H 2 FFFD FFFDH 55 H 2 FFFE FFFEH AH 0AL l Fig. 2.3 Popping Register Contents from Stack Memory 46 Advanced Microprocessors and Peripherals XCHG: Exchange This instruction exchanges the contents of the specified source and destination operands, which may be registers or one of them may be a memory location. However, exchange of contents of two memory locations is not permitted. Immediate data is also not allowed in these instructions. The examples are as follows: Example 2.19 1. XCHG [5000HJ, AX ; This instruction exchanges data between AX and a ; memory location [5000H] in the data segment. 2. XCHG BX, AX ; This instruction exchanges data between AX and BX. IN: Input the Port This instruction is used for reading an input port. The address of the input port may be specified in the instruction directly or indirectly. AL and AX are the allowed destinations for 8 and 16-bit input operations. DX is the only register (implicit) which is allowed to carry the port address. If the port ad- dress is of 16 bits it must be in DX. The examples are given as shown: Example 2.20 1. IN AL,03H ; This instruction reads data from an 8-bit port whose address ; is 03H and stores it in AL. 2. IN AX, DX ; This instruction reads data from a 16-bit port whose ; address is in DX (implicit) and stores it in AX. 3. MOV DX, 0800H ; The 16-bit address is taken in DX. IN AX, DX ; Read the content of the port in AX. OUT: Output to the Port This instruction is used for writing to an output port. The address of the output port may be specified in the instruction directly or implicitly in DX. Contents of AX or AL are transferred to a directly or indirectly addressed port after execution of this instruction. The data to an odd addressed port is transferred on D8-D15 while that to an even addressed port is transferred on D0-D7. The registers AL and AX are the allowed source operands for 8-bit and 16-bit operations respectively. If the port address is of 16 bits it must be in DX. The examples are given as shown: Example 2.21 1. OUT 03H,AL; This sends data available in AL to a port whose ; address is 03H. 2. OUT DX, AX ; Th is sends data available in AX to a port whose ; address is specified implicitly in DX. 3. MOV DX, 0300H ; The 16-bit port address is taken in DX. OUT DX, AX ; Write the content of AX to a port of which address is in DX. XLAT: Translate The translate instruction is used for finding out the codes in case of code conver- sion problems, using look up table technique. We will explain this instruction with the aid of the following example. Suppose, a hexadecimal key pad having 16 keys from Oto Fis interfaced with 8086 using 8255. Whenever a key is pressed, the code of that key (0 to F) is returned in AL. For displaying the number corresponding to the pressed key on the 7-segment display device, it is required that the 7-segment code corresponding to the key pressed is found out and sent to the display port. This translation from the code of the key pressed to the corresponding 7-segment code is performed using XLA T instruction. For this purpose, one is required to prepare a look up table of codes, starting from an offset say 2000H, and store the 7-segment codes for Oto F at the locations 2000H to 200FH sequentially. For executing the  8086/8088 Instruction Set and Assembler Directives 47 XLA T instruction, the code of the pressed key obtained from the keyboard ( i.e. the code to be translated) is moved in AL and the base address of the look up table containing the 7-segment codes is kept in BX. After the execution of the XLA T instruction, the 7-segment code corresponding to the pressed key is returned in AL, replacing the key code which was in AL prior to the execution of the XLAT instruction. To find out the exact address of the 7-segment code from the base address oflook up table, the content of AL is added to BX internally, and the contents of the address pointed to by this new content of BX in DS are transferred to AL. The following sequence of instructions perform the task. Example 2.22 MOV AX, SEG TABLE Address of the segment containing look-up-table MOV OS.AX is transferred in OS MOV AL, CODE Code of the pressed key is transferred in AL MOV BX, OFFSET TABLE; Offset of the code look-up-table in BX XLAT Find the equivalent code and store in AL Mnemonics & Description Instruction Code Data Transfer MOV= Move 76543210 76543210 76543210 76543210 Register/Memory to/from Register 100010 dw mod reg rim Immediate to Register/Memory 1100011 w mod 000 rim data data if w = 1 Immediate to Register 1011 w reg data data if w = 1 Memory to Accumulator 1010000 w addr-low addr-high Accumulator to Memory 1010001 w addr-low addr-high Register/Memory to Segment Register 10001110 mod Oreg rim Segment Register to Register/Memory 10001100 mod Oreg rim PUSH= Push: Register/Memory 11111111 mod 110 rim Register 01010 reg Segment Register 000 reg 110 POP= Pop: Register/Memory 10001111 mod 000 rim Register 01011 reg Segment Register 000 reg 111 XCHG = Exchange Register/Memory with Register 1000011 w mod reg rim Register with Accumulator 10010 reg IN= Input from: Fixed Port 1110010 w port Variable Port 1110110w OUT = Output to Fixed Port 1110011 w port Variable Port 1110111 w XLAT = Translate Byte to AL 11010111 LEA = Load EA to Register 10001101 mod reg rim LDS = Load Pointer to OS 11000101 mod reg rim LES = Load Pointer to ES 11000100 mod reg rim LAH F = Load AH with Flags 10011111 SAH F = Store AH into Flags 10011110 PUSHF = Push Flags 10011100 POPF = Pop Flags 10011101 ARITHMETIC 76543210 76543210 76543210 76543210 ADD =Add: Reg/Memory with Register to Either 000000 dw mod reg rim 48 Advanced Microprocessors and Peripherals Mnemonics & Description Instruction Code Immediate to Accumulator 0000010 w data data if w = 1 ADC = Add with Carry: Reg/Memory with Register to Either 000100 dw mod reg rim Immediate to Register/Memory 100000 SW mod 010 rim data data ifs w = 01 Immediate to Accumulator 0001010w data data if w = 1 INC= Increment: Register/Memory 1111111 w mod 000 rim Register 01000 reg AAA = ASCII Adjust for Addition 00110111 DAA = Decimal Adjust for Addition 00100111 SUB = Subtract Reg/Memory and Register to Either 001010 dw mod reg rim Immediate from Register/Memory 100000 SW mod 101 rim data data ifs w = 01 Immediate from Accumulator 0010110 w data data if w = 1 SBB = Subtract with Borrow Reg/Memory and Register to Either 000110 dw mod reg rim Immediate from Register/Memory 100000 SW mod 011 rim data data ifs w = 01 Immediate from accumulator 0001110 w data data if w = 1 DEC = Decrement: Register/Memory 1111111 w mod 001 rim Register 01001 reg NEG = Change sign 1111011 w mod 011 rim CMP = Compare: Register/Memory and Register 001110 dw mod reg rim Immediate with Register/Memory 100000 SW mod 111 rim data data ifs w = 01 Immediate with Accumulator 0011110 w data data if w = 1 AAS= ASCII Adjust for Subtract 00111111 DAS = Decimal Adjust for Subtract 00101111 MUL = Multiply (Unsigned) 1111011 w mod 100 rim IMUL = Integer Multiply (Signed) 1111011 w mod 101 rim AAM = ASCII Adjust Multiply 11010100 00001010 DIV= Divide (Unsigned) 1111011 w mod 110 rim IDIV = Integer Divide (Signed) 1111011 w mod 111 rim AAD = ASCII Adjust for Divide 11010101 00001010 CBW = Convert Byte to Word 10011000 CWD = Convert Word to Double Word 10011001 LOGICAL 76543210 76543210 76543210 76543210 NOT= Invert 1111011 w mod 010 rim SHL/SAL = Shift Logical/Arithmetic 110100 v w mod 100 rim Left SHR = Shift Logical Right 110100 v w mod 101 rim SAR = Shift Arithemtic Right 110100 v w mod 111 rim ROL = Rotate Left 110100 v w mod 000 rim ROR = Rotate Right 110100 v w mod 001 rim RCL = Rotate Through Carry Flag Left 110100v w mod 010 rim RCR = Rotate Through Carry Right 110100 v w mod 011 rim AND =And: Reg/Memory and Register to Either 001000 dw mod reg rim Immediate to Register/Memory 1000000 w mod 100 rim data data if w = 1 Immediate to Accumulator 0010010 w data data if w = 1 TEST= And Function to Flags, No Result: Register/Memory and Register 1000010 w mod reg rim Immediate Data and Register/Memory 1111011 w mod 000 rim data data if w = 1 Immediate Data and Accumulator 1010100 w data data if w = 1 OR=Or: Reg/Memory and Register to Either 000010 dw mod reg rim Immediate to Register/Memory 1000000 w mod 001 rim data data if w = 1 Immediate to Accumulator 0000110 w data data if w = 1  8086/8088 Instruction Set and Assembler Directives 49 Mnemonics & Description Instruction Code XOR = Exclusive or: Reg/Memory and Register to Either 001100 dw mod reg rim Immediate to Register/Memory 1000000 w mod 110 rim data data if w = 1 Immediate to Accumulator 0011010w data data if w =1 STRING MANIPULATIONS REP= Repeat 1111001 z MOVS = Move Byte/Word 1010010w CMPS = Compare Byte/Word 1010011w SCAS = Scan Byte/Word 1010111 w LODS = Load byte/Wd to AL/AX 1010110w STOS = Stor Byte/Wd from AL/A 1010101 w CONTROL TRANSFER CALL= Call: Direct Within Segment 11101000 disp-low disp-high Indirect Within Segment 11111111 mod 010 rim Direct lntersegment 10011010 offset-low offset-high seg-low seg-high 76543210 76543210 76543210 Indirect lntersegment 11111111 mod 011 rim JMP = Unconditional Jump: Direct Within Segment 11101001 disp-low disp-high Direct Within Segment-short 11101011 disp Indirect Within Segment 11111111 mod 100 rim Direct lntersegment 11101010 offset-low offset-high seg-low seg-high Indirect lntersegment 11111111 mod 101 rim RET = Return from CALL: Within Segment 11000011 Within Seg Adding Immediate to SP 11000010 data-low data-high lntersegment 11001011 lntersegment Adding Immediate to SP 11001010 data-low data-high JE/JZ = Jump on Equal/Zero 01110100 disp JL/JNGE = Jump on Less/Not 011111100 disp Greater or Equal JLE/JNG = Jump on Less or 01111110 disp Equal/Not Greater JB/JNAE = Jump on Below/Not Above 01110010 disp or Equal JBE/JNA = Jump on Below or 01110110 disp Equal/Not Above JP/JPE = Jump on Parity/Parity Even 01111010 disp JO = Jump on Overflow 01110000 disp JS= Jump on Sign 01111000 disp JNE/JNZ = Jump on Not Equal/Not 01110101 disp Zero JNL/JGE = Jump on Not Less/Greater 01111101 disp or Equal JNLE/JG = Jump on Not Less or 01111111 disp Equal/Greater JNB/JAE = Jump on Not Below/Above 01110011 disp or Equal JNBE/JA = Jump on Not Below or 01110111 disp Equal/Above JNP/JPO = Jump on Not Par/Par Odd 01111011 disp JNO = Jump on Not Overflow 01110001 disp JNS = Jump on Not Sign 01111001 disp LOOP = Loop ex Times 11100010 disp LOOPZ/LOOPE = Loop While Zero/ 11100001 disp 50 Advanced Microprocessors and Peripherals Mnemonics & Description Instruction Code Equal LOOPNZ/LOOPNE = Loop While Not 11100000 disp Zero/Equal JCXZ = Jump on CX Zero 11100011 disp INT= Interrupt Type Specified 11001101 type Type 3 11001100 INTO= Interrupt on Overflow 11001110 IRET = Interrupt Return 11001111 76543210 76543210 PROCESSOR CONTROL CLC = Clear Carry 11111000 CMC = Complement Carry 11110101 STC = Set Carry 11111001 CLD = Clear Direction 11111100 STD = Set Direction 11111101 CU = Clear Interrupt 11111010 STI = Set Interrupt 11111011 HLT= Halt 11110100 WAIT=Wait 10011011 ESC = Escape (to External Device) 11011xxx mod xxx r/m LOCK = Bus Lock Prefix 11110000 *The v, w, d, sand z bits and the mod, reg, rim fields are discussed in the addressing modes' section. Fig. 2.4 8086/8088 Instruction Set Summary LEA: Load Effective Address The load effective address instruction loads the effective address formed by destination operand into the specified source register. This instruction is more useful for assembly lan- guage rather than for machine language. The examples are given below. Example 2.23 LEA BX,ADR Effective address of Label ADR i.e. offset of ADR will be transferred to Reg ; BX. LEA SI, ADR[BxJ; offsetofLabelADRwillbeaddedtocontentofBxtoformeffective address and it will be loaded in SI LDS/LES: Load Pointer to DS/ES This instruction loads the DS or ES register and the specified des- tination register in the instruction with the content of memory location specified as source in the instruction. The example in Fig. 2.5 explains the operation. LDS BX, 5000H/LES BX, 5000H 15 8 7 0 7 0 BX YY XX xx 5000 yy 5001 DS/ES nn mm ,----------< mm 5002 nn 5003 Fig. 2.5 LDS/LES Instruction Execution  8086/8088 Instruction Set and Assembler Directives 51 LAHF: Load AH from Lower Byte of Flag This instruction loads the AH register with the lower byte of the flag register. This command may be used to observe the status of all the condition code flags (except over flow) at a time. SAHF: Store AH to Lower Byte of Flag Register This instruction sets or resets the condition code flags (except overflow) in the lower byte of the flag register depending upon the corresponding bit positions in AH. If a bit in AH is 1, the flag corresponding to the bit position is set, else it is reset. PUSHF: Push Flags to Stack The push flag instruction pushes the flag register on to the stack; first the upper byte and then the lower byte is pushed on to it. The SP is decremented by 2, for each push operation. The general operation of this instruction is similar to the PUSH operation. POPF: Pop Flags from Stack The pop flags instruction loads the flag register completely (both bytes) from the word contents of the memory location currently addressed by SP and SS. The SP is incremented by 2 for each pop operation. Figure 2.4 shows the data sheet for the hand coding of all the 8086 instructions. The MOD and RIM fields are to be decided as already described in this chapter. This type of instructions do not affect any flags. 2.3.2 Arithmetic Instructions These instructions perform the arithmetic operations, like addition, subtraction, multiplication and division along with the respective ASCII and decimal adjust instructions. The increment and decrement operations also belong to this type of instructions. The 8086/8088 instructions falling under this category are discussed below in significant details. The arithmetic instructions affect all the condition code flags. The operands are either the registers or memory locations or immediate data depending upon the addressing mode. ADD: Add This instruction adds an immediate data or contents of a memory location specified in the instruction or a register (source) to the contents of another register (destination) or memory location. The result is in the destination operand. However, both the source and destination operands cannot be memory operands. That means memory to memory addition is not possible. Also the contents of the segment registers cannot be added using this instruction. All the condition code flags are affected, depending upon the result. The examples of this instruction are given along with the corresponding modes. Example 2.24 l.ADD AX, OlOOH Immediate 2.ADD AX, BX Register 3.ADD AX, [SI] Register indirect 4.ADD AX, [5000HJ Direct 5.ADD [5000HJ, OlOOH Immediate 6.ADD OlOOH Destination AX (implicit) ADC: Add with Carry This instruction performs the same operation as ADD instruction, but adds the carry flag bit (which may be set as a result of the previous calculations) to the result. All the condition code flags are affected by this instruction. The examples of this instruction along with the modes are as follows: Example 2.25 1. ADC OlOOH Immediate (AX implicit) 2.ADC AX, BX Register 3.ADC AX, [SI] Register indirect 4.ADC AX, [5000HJ Direct 5.ADC [5000HJ, OlOOH Immediate 52 Advanced Microprocessors and Peripherals INC: Increment This instruction increases the contents of the specified register or memory location by 1. All the condition code flags are affected except the carry flag CF. This instruction adds I to the contents of the operand. Immediate data cannot be operand of this instruction. The examples of this instruction are as follows: Example 2.26 1. INC AX Register 2. INC [BX] Register indirect 3. INC [5000HJ Direct DEC: Decrement The decrement instruction subtracts I from the contents of the specified register or memory location. All the condition code flags, except the carry flag, are affected depending upon the result. Immediate data cannot be operand of the instruction. The examples ofthis instruction are as follows: Example 2.27 1.DEC AX Register 2.DEC [5000HJ Direct SUB: Subtract The subtract instruction subtracts the source operand from the destination operand and the result is left in the destination operand. Source operand may be a register, memory location or immediate data and the destination operand may be a register or a memory location, but source and destination operands both must not be memory operands. Destination operand can not be an immediate data. All the condition code flags are affected by this instruction. The examples of this instruction along with the addressing modes are as follows: Example 2.28 l.SUB AX, OlOOH Immediate [destination AX] 2.SUB AX, BX Register 3.SUB AX, [5000HJ Direct 4.SUB [5000HJ, 0100 Immediate SBB: Subtract with Borrow The subtract with borrow instruction subtracts the source operand and the borrow flag (CF) which may reflect the result of the previous calculations, from the destination operand. Subtraction with borrow, here means subtracting 1 from the subtraction obtained by SUB, if carry (borrow) flag is set. The result is stored in the destination operand. All the flags are affected (Condition code) by this instruction. The examples of this instruction are as follows: Example 2.29 1. SBB AX. OlOOH Immediate [destination AX] 2.SBB AX, BX Register 3.SBB AX, [5000HJ Direct 4.SBB [5000HJ, 0100 Immediate CMP: Compare This instruction compares the source operand, which may be a register or an im- mediate data or a memory location, with a destination operand that may be a register or a memory location.  8086/8088 Instruction Set and Assembler Directives 53 For comparison, it subtracts the source operand from the destination operand but does not store the result anywhere. The flags are affected depending upon the result of the subtraction. If both of the operands are equal, zero flag is set. If the source operand is greater than the destination operand, carry flag is set or else, carry flag is reset. The examples of this instruction are as follows: Example 2.30 l.CMP BX, OlOOH Immediate 2.CMP AX, OlOOH Immediate 3.CMP [5000HJ, OlOOH Direct 4.CMP BX, [SI] Register indirect 5.CMP BX. ex Register AAA: ASCII Adjust After Addition The AAA instruction is executed after an ADD instruction that adds two ASCII coded operands to give a byte of result in AL. The AAA instruction converts the resulting contents of AL to unpacked decimal digits. After the addition, the AAA instruction examines the lower 4 bits of AL to check whether it contains a valid BCD number in the range O to 9. If it is between O to 9 and AF is zero, AAA sets the 4 high order bits of AL to 0. The AH must be cleared before addition. If the lower digit of AL is between Oto 9 and AF is set, 06 is added to AL.The upper 4 bits of AL are cleared and AH is incremented by one. If the value in the lower nibble of AL is greater than 9 then the AL is incremented by 06, AH is incremented by 1, the AF and CF flags are set to 1, and the higher 4 bits of AL are cleared to 0. The remaining flags are unaffected. The AH is modified as sum of previous contents (usually 00) and the carry from the adjustment, as shown in Fig. 2.6. This instruction does not give exact ASCII codes of the sum, but they can be obtained by adding 3030H to AX. 1. AL - Before to AAA AL - After AAA execution 2.AL[3}- Previous to AAA AH A>9, henceA+6= 1010+0110 = 10000 B = 1 0 H AF Set to 1 I I AX O O 6 A - Previous to AAA w AX O 1 I O O I - After AAA execution Fig. 2.6 ASCII Adjust after Addition Instruction AAS: ASCII Adjust AL after Subtraction AAS instruction corrects the result in AL register after subtracting two unpacked ASCII operands. The result is in unpacked decimal format. If the lower 4 bits of AL register are greater than 9 or if the AF flag is 1, the AL is decremented by 6 and AH register is decre- mented by 1, the CF and AF are set to 1. Otherwise, the CF and AF are set to 0, the result needs no correction. As a result, the upper nibble of AL is 00 and the lower nibble may be any number from Oto 9. The procedure is similar to the AAA instruction except for the subtraction of 06 from AL. AH is modified as difference of the previous contents (usually zero) of AH and the borrow for adjustment. 54 Advanced Microprocessors and Peripherals AAM : ASCII Adjust after Multiplication This instruction, after execution, converts the product available in AL into unpacked BCD format. The AAM-ASCII Adjust After Multiplication-instruction follows a multiplication instruction that multiplies two unpacked BCD operands, i.e. higher nibbles of the multiplication operands should be 0. The multiplication of such operands is carried out using MUI instruction. Obviously the result of multiplication is available in AX. The following AAM instruction replaces content of AH by tens of the decimal multiplication and AL by singles of the decimal multiplication. Example 2.31 MOV AL, 04 AL f- 04 MOV BL, 09 BL f- 09 MU L BL AH-AL f- 24H (9 x 4) AAM AH f- 03 AL f- 06 AAD: ASCII Adjust before Division Though the names of these two instructions (AAM and AAD) appear to be similar, there is a lot of difference between their functions. The AAD instruction con- verts two unpacked BCD digits in AH and AL to the equivalent binary number in AL. This adjustment must be made before dividing the two unpacked BCD digits in AX by an unpacked BCD byte. PF, SF, ZF are modified while AF, CF, OF are undefined, after the execution of the instruction AAD. The example explains the execution of the instruction. In the instruction sequence, this instruction appears before DIV instruction unlike AAM appears after MUL. Let AX contains 0508 unpacked BCD for 5 8 decimal, and DH contains 02H. Example 2.32 AX lo5I 08! AAD result in AL l oo I 3A I 580 = 3A Hin AL The result of AAD execution will give the hexadecimal number 3A in AL and 00 in AH. Note that 3A is the hexadecimal equivalent of 58 (decimal). Now, instruction DIV DH may be executed. So rather than ASCII adjust for division, it is ASCII adjust before division. All the ASCII adjust instructions are also called as unpacked BCD arithmetic instructions. Now, we will consider the two instructions related to packed BCD arithmetic. DAA: Decimal Adjust Accumulator This instruction is used to convert the result of the addition of two packed BCD numbers to a valid BCD number. The result has to be only in AL. If the lower nibble is greater than 9, after addition or if AF is set, it will add 06 to the lower nibble in AL. After adding 06 in the lower nibble of AL, if the upper nibble of AL is greater than 9 or if carry flag is set, DAA instruction adds 60H to AL. The examples given below explain the instruction. Example 2.33 ( i ) AL= 53 CL = 29 ADD AL, CL AL f- (AL) + (CL) AL f- 53 + 29 AL f- 7C DAA AL f- 7C + 06 (as C>9) AL f- 82  8086/8088 Instruction Set and Assembler Directives 55 (ii) AL= 73 CL= 29 ADD AL, CL AL t- AL+ CL AL t- 73 + 29 AL t- 9C DAA AL t- 02 and CF 1 AL 7 3 + CL = 2 9 9 C + 6 A 2 + 6 0 CF = 1 0 2 in AL The instruction DAA affects AF, CF, PF, and ZF flags. The OF is undefined. DAS: Decimal Adjust after Subtraction This instruction converts the result of subtraction of two packed BCD numbers to a valid BCD number. The subtraction has to be in AL only. If the lower nibble of AL is greater than 9, this instruction will subtract 06 from lower nibble of AL. If the result of subtraction sets the carry flag or if upper nibble is greater than 9, it subtracts 60H from AL. This instruction modifies the AF, CF, SF, PF and ZF flags. The OF is undefined after DAS instruction. The examples are as follows: Example 2.34 ( i ) AL= 75 BH = 46 SUB AL, BH AL t- 2 F = (AL) - (BH) ; AF = 1 DAS ; AL t- 2 9 (as F > 9, F - 6 9) (ii ) AL = 38 CH= 6 1 SUB AL, CH AL t- D 7 CF = 1 (borrow) DAS AL t- 7 7 (as D > 9, D - 6 7) CF = 1 (borrow) DAA and DAS instructions are also called packed BCD arithmetic instructions. NEG: Negate The negate instruction forms 2's complement of the specified destination in the instruction. For obtaining 2's complement, it subtracts the contents of destination from zero. The result is stored back in the destination operand which may be a register or a memory location. If OF is set, it indicates that the operation could not be completed successfully. This instruction affects all the condition code flags. MUL: Unsigned Multiplication Byte or Word This instruction multiplies an unsigned byte or word by the contents of AL. The unsigned byte or word may be in any one of the general purpose registers or memory locations. The most significant word of the result is stored in DX, while the least significant word of the result is stored in AX. All the flags are modified depending upon the result. The example instructions are as shown. Immediate operand is not allowed in this instruction. If the most significant byte or word of the result is 'O' CF and OF both will be set. 56 Advanced Microprocessors and Peripherals Example 2.35 1. MUL BH (AX) (AL) x (BH) 2. MUL ex (DX) (AX) (AX) x (CX) 3. MUL WORD PTR [SI] (DX) (AX) (AX) x([SIJ) IMUL: Signed Multiplication This instruction multiplies a signed byte in source operand by a signed byte in AL or a signed word in source operand by a signed word in AX. The source can be a general purpose register, memory operand, index register or base register, but it cannot be an immediate data. In case of32-bit results, the higher order word (MSW) is stored in DX and the lower order word is stored in AX. The AF, PF, SF, and ZF flags are undefined after IMUL. If AH and DX contain parts of 16 and 32-bit result respectively, CF and OF both will be set. The AL and AX are the implicit operands in case of 8 bits and 16 bits multipli- cations respectively. The unused higher bits of the result are filled by sign bit and CF, AF are cleared. The example instructions are given as follows: Example 2.36 l.IMUL BH 2.IMUL ex 3. IMUL [SI] CBW: Convert Signed Byte to Word This instruction converts a signed byte to a signed word. In other words, it copies the sign bit of a byte to be converted to all the bits in the higher byte of the result word. The byte to be converted must be in AL. The result will be in AX. It does not affect any flag. CWD: Convert Signed Word to Double Word This instruction copies the sign bit of AX to all the bits of the DX register. This operation is to be done before signed division. It does not affect any flag. DIV: Unsigned Division This instruction performs unsigned division. It divides an unsigned word or double word by a 16-bit or 8-bit operand. The dividend must be in AX for 16-bit operation and divisor may be specified using any one of the addressing modes except immediate. The result will be in AL (quotient) while AH will contain the remainder. If the result is too big to fit in AL, type O (divide by zero) and an interrupt is generated. In case of a double word dividend (32-bit), the higher word should be in DX and lower word should be in AX. The divisor may be specified as already explained. The quotient and the remainder, in this case, will be in AX and DX respectively. This instruction does not affect any flag. IDIV: Signed Division This instruction performs the same operation as the DIV instruction, but with signed operands. The results are stored similarly as in case of DIV instruction in both cases of word and double word divisions. The results will also be signed numbers. The operands are also specified in the same way as DIV instruction. Divide by O interrupt is generated, if the result is too big to fit in AX (16-bit dividend operation) or AX and DX (32-bit dividend operation). All the flags are undefined after IDIV instruction. 2.3.3 Logical Instructions These type of instructions are used for carrying out the bit by bit shift, rotate, or basic logical operations. All the condition code flags are affected depending upon the result. Basic logical operations available with 8086 instruction set are AND, OR, NOT, and XOR. The instruction for each of these operations are discussed as follows.  8086/8088 Instruction Set and Assembler Directives 57 AND: Logical AND This instruction bit by bit ANDs the source operand that may be an immediate, a register or a memory location to the destination operand that may be a register or a memory location. The result is stored in the destination operand. At least one of the operands should be a register or a memory operand. Both the operands cannot be memory locations or immediate operands. An immediate operand can- not be a destination operand. The examples of this instruction are as follows: Example 2.37 l.AND AX, 0008H 2.AND AX, BX 3.AND AX, [5000HJ 4.AND [5000HJ. DX If the content of AX is 3FOFH, the first example instruction will carry out the operation as given below. The result 3F9FH will be stored in the AX register. 0011 1111 0000 1 1 1 1 = 3FOF H [AX] J, J, J, J, J, J, J, J, J, J, J, J, J, J, J, J, AND 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 = 0008 H 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 = 0008 H [AX] The result 0008H will be in AX. OR: Logical OR The OR instruction carries out the OR operation in the same way as described in case of the AND operation. The limitations on source and destination operands are also the same as in case of AND operation. The examples are as follows: Example 2.38 1. OR AX, 0098H 2.0R AX, BX 3.0R AX, [5000HJ 4.0R [5000HJ, 0008H The contents of AX are say 3FOFH, then the first example instruction will be carried out as given below. 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 = 3 FO F H J, J, J, J, J, J, J, J, J, J, J, J, J, J, J, J, OR 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 = 0098 H 0 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 = 3 F9 F H Thus the result 3F9FH will be stored in the AX register. NOT: Logical Invert The NOT instruction complements (inverts) the contents of an operand register or a memory location, bit by bit. The examples are as follows: Example 2.39 NOT AX NOT [ 5000H J If the content of AX is 200FH, the first example instruction will be executed as shown. AX 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 invert J, J, J, J, J, J, J, J, J, J, J, J, J, J, J, J, 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 58 Advanced Microprocessors and Peripherals Result in AX = D F F 0 The result DFFOH will be stored in the destination register AX. XOR: Logical Exclusive OR The XOR operation is again carried out in a similar way to the AND and OR operation. The constraints on the operands are also similar. The XOR operation gives a high output, when the 2 input bits are dissimilar. Otherwise, the output is zero. The example instructions are as follows: Example 2.40 l.XOR AX, 0098H 2.XOR AX, BX 3.XOR AX, [5000HJ If the content of AX is 3FOFH, then the first example instruction will be executed as explained. The result 3F97H will be stored in AX. AX = 3 FO FH = 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 XOR J, J, J, J, J, J, J, J, J, J, J, J, J, J, J, J, 0098H = 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 AX Result= 0 0 1 1 1 1 1 1 1 0 0 1 0 1 1 1 3 F97H TEST: Logical Compare Instruction The TEST instruction performs a bit by bit logical AND op- eration on the two operands. Each bit of the result is then set to 1, if the corresponding bits of both operands are 1, else the result bit is reset to 0. The result of this ANDing operation is not available for further use, but flags are affected. The affected flags are OF, CF, SF, ZF and PF. The operands may be registers, memory or immediate data. The examples of this instruction are as follows: Example 2.41 1. TEST AX, BX 2.TEST , 06H 3.TEST [BX] [DI], ex SHUSAL: Shift Logical/Arithmetic Left These instructions shift the operand word or byte bit by bit to the left and insert zeros in the newly introduced least significant bits. In case of all the SHIFT and ROTA TE instructions, the count is either 1 or specified by register CL. The operand may reside in a register or a memory location but cannot be an immediate data. All flags are affected depending upon the result. Figure 2.7 explains the execution of this instruction. It is to be noted here that the shift operation is through carry flag. BIT POSITIONS CF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 OPERAND 1010 1 1 0 0 10100101 / /----------------------------/ / SHL RESULT 1st 1 o 1 o 1 1 o o 1 o 1 o o 1 o 1 o / /----------------------------/ / Inserted SHL RESULT 2nd o 1 o 1 1 o o 1 o 1 o o 1 o 1 o o Inserted Fig. 2. 7 Execution of SHL/SAL Instruction  8086/8088 Instruction Set and Assembler Directives 59 SHR: Shift Logical Right This instruction performs bit-wise right shifts on the operand word or byte that may reside in a register or a memory location, by the specified count in the instruction and inserts zeros in the shifted positions. The result is stored in the destination operand. Figure 2.8 explains execution of this instruction. This instruction shifts the operand through the carry flag. BIT POSITIONS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 O CF OPERAND 1010 1100 10100101 "x ----------------------------- Count= 1 ,-o 1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 1 Inserted ""'--- - -- -- - -- - -- --- -- - - - -- -- -- - -- Count= 2 ,-o O 1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 Inserted Fig. 2.8 Execution of SHR Instruction SAR: Shift Arithmetic Right This instruction performs right shifts on the operand word or byte, that may be a register or a memory location by the specified count in the instruction. It inserts the most significant bit of the operand in the newly inserted positions. The result is stored in the destination operand. Figure 2.9 explains execution of the instruction. All the condition code flags are affected. This shift operation shifts the operand through the carry flag. BIT POSITIONS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 O CF OPERAND 1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 1 "x ----------------------------- Count= 1 r----1 1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 1 Inserted MSB = 1 - - ----------- -------------- - Count = 2 r---- 1 1 O 1 0 1 1 0 0 1 0 1 O O 1 0 Inserted MSB = 1 Fig. 2.9 Execution of SAR Instruction Immediate operand is not allowed in any of the shift instructions. ROR: Rotate Right without Carry This instruction rotates the contents of the destination operand to the right (bit-wise) either by one or by the count specified in CL, excluding carry. The least significant bit is pushed into the carry flag and simultaneously it is transferred into the most significant bit position at each operation. The remaining bits are shifted right by the specified positions. The PF, SF, and ZF flags are left unchanged by the rotate operation. The operand may be a register or a memory location but it cannot be an immediate operand. Figure 2.10 explains the operation. The destination operand may be a register ( except a segment register) or a memory location. BIT POSITIONS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 O CF OPERAND 1010 111101011101 x "x --------------------------- Count= 1 11010111101 0 1 1 1 0 Count= 2 0 0 0 0 0 Fig. 2.10 Execution of ROR Instruction 60 Advanced Microprocessors and Peripherals ROL: Rotate Left without Carry This instruction rotates the content of the destination operand to the left by the specified count (bit-wise) excluding carry. The most significant bit is pushed into the carry flag as well as the least significant bit position at each operation. The remaining bits are shifted left subsequently by the specified count positions. The PF, SF, and ZF flags are left unchanged in this rotate operation. The operand may be a register or a memory location. Figure 2.11 explains the operation. BIT POSITIONS CF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 OPERAND 1 0 1 1 1 1 0 1 0 1 1 1 0 1 ---------------------------;/ _/' SHL RESULT 1st 0 1 1 1 1 0 1 0 1 1 1 0 1 1 SHL RESULT 2nd 0 0 0 0 0 0 Fig. 2.11 Execution of ROL Instruction RCR: Rotate Right through Carry This instruction rotates the contents (bit-wise) of the destination operand right by the specified count through carry flag (CF). For each operation, the carry flag is pushed into the MSB of the operand, and the LSB is pushed into carry flag. The remaining bits are shifted right by the specified count positions. The SF, PF, ZF are left unchanged. The operand may be a register or a memory location. Figure 2.12 explains the operation. BIT POSITIONS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 CF (arbitrary) OPERAND Count= 1 +"'- 0 0 \-----0----------- --- -------- 0 0 01 o\ 0 J Fig. 2.12 Execution of RCR Instruction RCL: Rotate Left through Carry This instruction rotates (bit-wise) the contents of the destination operand left by the specified count through the carry flag (CF). For each operation, the carry flag is pushed into LSB and the MSB of the operand is pushed into carry flag. The remaining bits are shifted left by the specified positions. The SF, PF, ZF are left unchanged. The operand may be a register or a memory location. Figure 2.13 explains the operation. BIT POSITIONS CF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 [>: (arbitrary) OPERAND 0 0 0 0 0 0 Count= 1 / 0 0 0 0 0 0 t Fig. 2.13 Execution of RCL Instruction The count for rotation or shifting is either 1 or is specified using register CL, in case of all the shift and rotate instructions.  8086/8088 Instruction Set and Assembler Directives 61 2.3.4 String Manipulation Instructions A series of data bytes or words available in memory at consecutive locations, to be referred to collectively or individually, are called as byte strings or word strings. For example, a string of characters may be located in consecutive memory locations, where each character may be represented by its ASCII equivalent. For referring to a string, two parameters are required, (a) starting or end address of the string and (b) length of the string. The length of a string is usually stored as count in the CX register. In case of 8085, similar struc- tures can be set up by the pointer and counter arrangements which may be modified at each iteration, till the required condition for proceeding further is satisfied. On the other hand, the 8086 supports a set of more powerful instructions for string manipulations. The incrementing or decrementing of the pointer, in case of 8086 string instructions, depends upon the Direction Flag (DF) status. If it is a byte string operation, the index registers are updated by one. On the other hand, if it is a word string operation, the index registers are updated by two. The counter in both the cases, is decremented by one. REP: Repeat Instruction Prefix This instruction is used as a prefix to other instructions. The in- struction to which the REP prefix is provided, is executed repeatedly until the CX register becomes zero (at each iteration CX is automatically decremented by one). When CX becomes zero, the execution proceeds to the next instruction in sequence. There are two more options of the REP instruction. The first is REPEi REPZ, i.e. repeat operation while equal/zero. The second is REPNE/REPNZ allows for repeating the op- eration while not equal/not zero. These options are used for CMPS, SCAS instructions only, as instruction prefixes. MOVSB/MOVSW: Move String Byte or String Word Suppose a string of bytes stored in a set of consecutive memory locations is to be moved to another set of destination locations. The starting byte of the source string is located in the memory location whose address may be computed using SI (Source Index) and DS (Data Segment) contents. The starting address of the destination locations where this string has to be relo- cated is given by DI (Destination Index) and ES (Extra Segment) contents. The starting address of the source string is IOH*DS+[SI], while the starting address of the destination string is IOH*ES+[DI]. The MOVSB/ MOVSW instruction thus, moves a string of bytes/words pointed to by DS: SI pair (source) to the memory location pointed to by ES: DI pair (destination). The REP instruction prefix is used with MOVS instruction to repeat it by a value given in the counter (CX). The length of the byte string or word string must be stored in CX register. No flags are affected by this instruction. After the MOVS instruction is executed once, the index registers are automatically updated and CX is decre- mented. The incrementing or decrementing of the pointers, i.e. SI and DI depend upon the direction flag DF. IfDF is 0, the index registers are incremented, otherwise, they are decremented, in case of all the string manipulation instructions. The following string of instructions explain the execution of the MOVS instruction. Example 2.42 MOV AX, 5000H Source segment address is 5000h MOV OS, AX Load it to OS MOV AX, 6000H Destination segment address is 6000h MOVES, AX Load it to ES MOV ex. OFFH Move length of the string to counter register CX MOV SI, lOOOH Source index address lOOOH is moved to SI MOV DI, 2000H Destination index address 2000H is moved to DI CLO Clear OF, i.e. set autoincrement mode REP MOVSB Move OFFH string bytes from source address to destination 62 Advanced Microprocessors and Peripherals CMPS: Compare String Byte or String Word The eMPS instruction can be used to compare two strings of bytes or words. The length of the string must be stored in the register ex. If both the byte or word strings are equal, zero flag is set. The flags are affected in the same way as eMP instruction. The DS:SI and ES:DI point to the two strings.The REP instruction prefix is used to repeat the operation till eX(counter) becomes zero or the condition specified by the REP prefix is false. The following string of instructions explain the instruction. The comparison of the string starts from initial byte or word of the string, after each comparison the index registers are updated depending upon the direction flag and the counter is decremented. This byte by byte or word by word comparison continues till a mismatch is found. When, a mismatch is found, the carry and zero flags are modified appropriately and the execution proceeds further. Example 2.43 MOV AX, SEGl Segment address of STRINGl, i. e. SEGl is moved to AX MOV OS, AX Load it to OS MOV AX, SEG2 Segment address of STRING2, i. e. SEG2 is moved to AX MOV ES, AX Load it to ES MOV SI, OFFSET STRINGl Offset of STRINGl is moved to SI MOV DI, OFFSET STRING2 Offset of STRING2 is moved to DI MOV ex. OlOH Length of the string is moved to CX CLO Clear OF, i.e. set autoincrement mode REPE CMPSW Compare OlOH words of STRINGl and STRING2, while they are equal, If a mismatch is found, modify the flags and proceed with further execution If both strings are completely equal, i.e. CX becomes zero, the ZF is set, otherwise, ZF is reset. SCAS: Scan String Byte or String Word This instruction scans a string of bytes or words for an operand byte or word specified in the register AL or AX. The string is pointed to by ES:DI register pair. The length of the string is stored in ex. The DF controls the mode for scanning of the string, as stated in case of MOVSB instruction. Whenever a match to the specified operand, is found in the string, execution stops and the zero flag is set. If no match is found, the zero flag is reset. The REPNE prefix is used with the Se AS instruction. The pointers and counters are updated automatically, till a match is found. The following string of instructions elaborates the use of SeAS instruction. Example 2.44 MOV AX,SEG Segment address of the string, i.e. SEG is moved to AX MOVES.AX Load it to ES MOV DI.OFFSET String offset, i.e. OFFSET is moved to DI MOV CX,OlOH Length of the string is moved to ex MOV AX.WORD The word to be scanned for, i.e. WORD is in AL CLO Clear OF REPNE SCASW Scan the OlOH bytes of the string, till a match to WORD is found This string of instructions finds out, if it contains WORD. If the WORD is found in the word string, before ex becomes zero, the ZF is set, otherwise the ZF is reset. The scanning will continue till a match is found. Once a match is found the execution of the programme proceeds further.  8086/8088 Instruction Set and Assembler Directives 63 LODS: Load String Byte or String Word The LODS instruction loads the AL/AX register by the content of a string pointed to by DS: SI register pair. The SI is modified automatically depending upon DF. The DF plays exactly the same role as in case of MOVSB/MOVSW instruction. If it is a byte transfer(LODSB), the SI is modified by one and if it is a word transfer(LODSW), the SI is modified by two. No other flags are affected by this instruction. STOS: Store String Byte or String Word The STOS instruction stores the AL/AX register con- tents to a location in the string pointed by ES: DI register pair. The DI is modified accordingly. No flags are affected by this instruction. The direction flag controls the string instruction execution. The source index SI and destination index DI are modified after each iteration automatically. If DF = 1, then the execution follows autodecrement mode. In this mode, SI and DI are decremented automatically after each iteration (by 1 or 2 depending upon byte or word operations). Hence, in autodecrementing mode, the strings are referred to by their ending addresses. If DF = 0, then the execution follows autoincrement mode. In this mode, SI and DI are incremented automati- cally (by 1 or 2 depending upon byte or word operation) after each iteration, hence the strings, in this case, are referred to by their starting addresses. Chapter 3 on assembly language programming explains the use of some of these instructions in assembly language programs. 2.3.5 Control Transfer or Branching Instructions The control transfer instructions transfer the flow of execution of the program to a new address specified in the instruction directly or indirectly. When this type of instruction is executed, the CS and IP registers get loaded with new values of CS and IP corresponding to the location where the flow of execution is going to be transferred. Depending upon the addressing modes specified in Chapter 1, the CS may or may not be modi- fied. This type of instructions are classified in two types: Unconditional Control Transfer (Branch) Instructions In case of unconditional control transfer instructions, the execution control is transferred to the specified location independent of any status or condi- tion. The CS and IP are unconditionally modified to the new CS and IP. Conditional Control Transfer (Branch) Instructions In the conditional control transfer instruc- tions, the control is transferred to the specified location provided the result of the previous operation satisfies a particular condition, otherwise, the execution continues in normal flow sequence. The results of the previ- ous operations are replicated by condition code flags. In other words, using this type of instruction the control will be transferred to a particular specified location, if a particular flag satisfies the condition. 2.3.6 Unconditional Branch Instructions CALL: Unconditional Call This instruction is used to call a subroutine from a main program. In case of assembly language programming, the term procedure is used interchangeably with subroutine. The ad- dress of the procedure may be specified directly or indirectly depending upon the addressing mode. There are again two types of procedures depending upon whether it is available in the same segment (Near CALL, i.e. ±32K displacement) or in another segment (FAR CALL, i.e. anywhere outside the segment). The modes for them are called as intrasegment and intersegment addressing modes respectively. This instruction comes un- der unconditional branch instructions and can be described as shown with the coding formats. On execution, this instruction stores the incremented IP (i.e. address of the next instruction) and CS onto the stack and loads the CS and IP registers, respectively, with the segment and offset addresses of the procedure to be called. In case of NEAR CALL it pushes only IP register and in case of FAR CALL it pushes IP and CS both onto the stack. The NEAR and FAR CALLS are discriminated using opcode. 64 Advanced Microprocessors and Peripherals D1 Do D1 Do D7 D1 Do Direct Near I OPCODE I DI SP.LB I I DISP.HB I D1 Do D1 Do D1 D6 Ds D4 D3 D2 D1 Do Indirect Near I OPCODE I OPCODE I I MOD I 0 0 I rim I D1 Do D1 DoD1 Do D1 Do D1 Do Direct Far I OPCODE I I LB I HB I I LB I HB I OFFSET SEGMENT D1 Do D1 Do D1 D6 Ds D4 D3 D2 D1 Do Indirect Far I OPCODE I I OPCODE I I MOD 0 0 I rim I RET: Return from the Procedure At each CALL instruction, the IP and CS of the next instruction is pushed onto stack, before the control is transferred to the procedure. At the end of the procedure, the RET instruction must be executed. When it is executed, the previously stored content of IP and CS along with flags are retrieved into the CS, IP and flag registers from the stack and the execution of the main program continues further. The procedure may be a near or a far procedure. In case of a FAR procedure, the current contents of SP points to IP and CS at the time of return. While in case of a NEAR procedure, it points to only IP. Depend- ing upon the type of procedure and the SP contents, the RET instruction is of four types. 1. Return within segment 2. Return within segment adding 16-bit immediate displacement to the SP contents. 3. Return interse gment 4. Return intersegment adding 16-bit immediate displacement to the SP contents. INT N: Interrupt Type N In the interrupt structure of 8086/8088, 256 interrupts are defined corre- sponding to the types from OOH to FFH. When an INT N instruction is executed, the TYPE byte N is multi- plied by 4 and the contents of IP and CS of the interrupt service routine will be taken from the hexadecimal multiplication (N'4) as offset address and 0000 as segment address. In other words, the multiplication of type N by 4 (offset) points to a memory block in 0000 segment, which contains the IP and CS values of the interrupt service routine. For the execution of this instruction, the IF must be enabled. Example 2.45 Thus the instruction INT 20H will find out the address of the interrupt service routine as follows: I NT 20H Type* 4 = 20 * 4 = 80H Pointer to IP and CS of the ISR is 0000 : 0080 H  8086/8088 Instruction Set and Assembler Directives 65 Figure 2.14 shows the arrangement of CS and IP addresses of the ISR in the interrupt vector table. Memory Contents 15 8 7 0 15 8 7 0 _c_s_H I _i g- S L_o_w : I IP h -C-_ High I IP Low I CS High 0000: 0083 CS Low 0000: 0082 IP High 0000: 0081 IP Low 0000: 0080 Fig. 2.14 Contents of /VT INTO: Interrupt on Overflow This command is executed, when the overflow flag OF is set. The new contents ofIP and CS are taken from the address 0000:0010 as explained in INT type instruction. This is equivalent to a Type 4 interrupt instruction. JMP: Unconditional Jump This instruction unconditionally transfers the control of execution to the specified address using an 8-bit or 16-bit displacement (intrasegment relative, short or long) or CS: IP (in- tersegment direct far). No flags are affected by this instruction. Corresponding to the methods of specifying jump addresses, the JUMP instruction may have the following three formats. For other JMP types the reader may refer to the following datasheet. JUMP DISP 8-bit Intrasegment, relative, short jump JUMP I DISP.16-bit ( LB) I DISP.16-bit ( H B) Intra segment, relative, short jump JUMP I Ip (LB) lrP (HB) les (LB) Is (HB)I Intrasegment, direct, far jump IRET: Retum from ISR When an interrupt service routine is to be called, before transferring control to it, the IP, CS and flag register are stored on to the stack to indicate the location from where the execution is to be con- tinued, after the ISR is executed. So, at the end of each ISR, when IRET is executed, the values ofIP, CS and flags are retrieved from the stack to continue the execution of the main program. The stack is modified accordingly. LOOP: Loop Unconditionally This instruction executes the part of the program from the label or address specified in the instruction up to the loop instruction, CX number of times. The following sequence explains the execution. At each iteration, CX is decremented automatically. In other words, this instruction implements DECREMENT COUNTER and JUMP IF NOT ZERO structure. Example 2.46 MOV ex. 0005 Number of times in ex MOV BX, OFF?H Data to BX Label MOV AX, eODEl OR BX, AX AND DX, AX Loop Label 66 Advanced Microprocessors and Peripherals The execution proceeds in sequence, after the loop is executed, CX number of times. If CX is already OOH, the execution continues sequentially. No flags are affected by this instruction. 2.3. 7 Conditional Branch Instructions When these instructions are executed, execution control is transferred to the address specified relatively in the instruction, provided the condition implicit in the opcode is satisfied. If not the execution continues sequen- tially. The conditions, here, means the status of condition code flags. These type of instructions do not affect any flag. The address has to be specified in the instruction relatively in terms of displacement which must lie within -80H to 7FH (or -128 to 127) bytes from the address of the branch instruction. In other words, only short jumps can be implemented using conditional branch instructions. A label may represent the displace- ment, if it lies within the above specified range. The different 8086/8088 conditional branch instructions and their operations are listed in Table 2.3. Table 2.3 Conditional Branch Instructions Mnemonic Displacement Operation 1. JZ/JE Label Transfer execution control to address 'Label', if ZF=l. 2. JNZ/JNE Label Transfer execution control to address 'Label', if ZF=O. 3. JS Label Transfer execution control to address 'Label', if Sf= l. 4. JNS Label Transfer execution control to address 'Label', if SF=O. 5. JO Label Transfer execution control to address 'Label', if Ole= l. 6. JNO Label Transfer execution control to address 'Label', if OF=O. 7. JP/JPE Label Transfer execution control to address 'Label', if PF=l. 8. JNP Label Transfer execution control to address 'Label', if PF=O. 9. JB/JNAE/JC Label Transfer execution control to address 'Label', if CF=l. 10. JNB/JAE/JNC Label Transfer execution control to address 'Label', if CF=O. 11. JBE/JNA Label Transfer execution control to address 'Label', ifCF=l or ZF=l. 12. JNBE/JA Label Transfer execution control to address 'Label', if CF=O or ZF=O. 13. JL/JNGE Label Transfer execution control to address 'Label', if neither SF=l nor OF=l. 14. JNL/JGE Label Transfer execution control to address 'Label', if neither SF=O nor OF=O. 15. JLE/JNC Label Transfer execution control to address 'Label', if ZF=l or neither SF nor OF is 1. 16. JNLE/JE Label Transfer execution control to address 'Label', if ZF=O or at least any one of SF and OF is l(Both SF and OF are not 0). While the remaining instructions can be used for unsigned binary operations, the last four instructions are used in case of decisions based on signed binary number operations. The terms above and below are generally used for unsigned numbers, while the terms less and greater are used for signed numbers. A conditional jump instruction, that does not check status flags for condition testing, is given as follows: JCXZ 'Label' Transfer execution control to address 'Label', if CX=O. The conditional LOOP instructions are given in Table 2.4 with their meanings. These instructions may be used for implementing structures like DO_WHILE, REPEAT_UNTIL, etc.  8086/8088 Instruction Set and Assembler Directives 67 Table 2.4 Conditional Loop Instructions Mnemonic Displacement Operation LOOPZ/LOOPE Label Loop through a sequence of (Loop while ZF = 1; equal) instructions from 'Label' while ZF=l and ex 1 0. LOOPNZ/LOOPENE Label Loop through a sequence of (Loop while ZF = O; not equal) instructions from 'Label' while ZF=O and ex 1 0. These instructions will be clear with programming practice. This topic aims at introducing them to the readers. Of course, examples are quoted wherever possible, but the JUMP and the LOOP instructions require a sequence of instructions for explanations and they will be emphasized more in Chapter 3. 2.3.8 Flag Manipulation and Processor Control Instructions These instructions control the functioning of the available hardware inside the processor chip. These are categorized into two types; (a) flag manipulation instructions and (b) machine control instructions. The fl.ag manipulation instructions directly modify some of the flags of 8086. The machine control instructions control the bus usage and execution. The flag manipulation instructions and their functions are listed in Table 2.5. Table 2.5 Flag Manipulation Instructions CLC Clear carry flag CMC Complement carry flag STC Set carry flag CLO Clear direction flag STD Set direction flag CLI Clear interrupt flag STI Set interrupt flag These instructions modify the Carry (CF), Direction (DF) and Interrupt (IF) flags directly. The DF and IF, which may be modified using the flag manipulation instructions, further control the processor operation; like interrupt responses and autoincrement or autodecrement modes. Thus, the respective instructions may also be called machine or processor control instructions. The other flags can be modified using POPF and SAHF instructions, which are termed as data transfer instructions, in this text. No direct instructions, are available for modifying the status flags except carry flag. The machine control instructions supported by 8086 and 8088 are listed in Table 2.6 along with their func- tions. They do not require any operand. Table 2.6 Machine Control Instructions WAIT Wait for Test input pin to go low HLT Halt the processor NOP No operation ESC Escape to external device like NDP (numeric co-processor) LOCK Bus lock instruction prefix. 68 Advanced Microprocessors and Peripherals As explained in Chapter 1, after executing the HLT instruction, the processor enters the halt state. The two ways to pull it out of the halt state are to reset the processor or to interrupt it. When NOP instruction is executed, the processor does not perform any operation till 4 clock cycles, except for incrementing the IP by one. It then continues with further execution after 4 clock cycles. ESC instruction when executed, frees the bus for an external master like a coprocessor or peripheral devices. The LOCK prefix may appear with another instruction. When it is executed, the bus access is not allowed for another master till the lock pre- fixed instruction is executed completely. This instruction is used in case of programming for multiprocessor systems. The WAIT instruction when executed, holds the operation of processor with the current status till the logic level on the TE ST pin goes low. The processor goes on inserting WAIT states in the instruction cycle, till the TEST pin goes low. Once the TEST pin goes low, it continues further execution. 2.4 ASSEMBLER DIRECTIVES AND OPERATORS The main advantage of machine language programming is that the memory control is directly in the hands of the programmer enabling him to manage the memory of the system more efficiently. However, there are more disadvantages. The programming, coding and resource management techniques are tedious. As the program- mer has to consider all these functions, the chances of human errors are more. To understand the programs one has to have a thorough technical knowledge of the processor architecture and instruction set. The assembly language programming is simpler as compared to the machine language programming. The instruction mnemonics are directly written in the assembly language programs. The programs are now more readable than that of machine language programs. The advantage that assembly language has over machine language is that now the address values and the constants can be identified by labels. If the labels are clear then certainly the program will become more understandable, and each time the pro- grammer will not have to remember the different constants and the addresses at which they are stored, throughout the programs. Due to this facility, the tedious byte handling and manipulations are got rid of. Similarly, now different logical segments and routines may be assigned with the labels rather than the different addresses. The memory control feature of machine language programming is left unchanged by providing storage define facilities in assembly language programming. The documentation facility which was not possible with machine language programming is now available in assembly language. Readers will get a better glimpse of the different features of assembly language, when we discuss assembly lan- guage programming in the next chapter. An assembler is a program used to convert an assembly language program into the equivalent machine code modules which may further be converted to executable codes. It decides the address of each label and substitutes the values for each of the constants and variables. It then forms the machine code for the mnemon- ics and data in the assembly language program. While doing these things, the assembler may find out syntax errors.The logical errors or other programming errors are not found out by the assembler. For completing all these tasks, an assembler needs some hints from the programmer, i.e. the required storage for a particular constant or a variable, logical names of the segments, types of the different routines and modules, end of file, etc. These types of hints are given to the assembler using some predefined alphabetical strings called assembler directives, which help the assembler to correctly understand the assembly language programs to prepare the codes. Another type of hint which helps the assembler to assign a particular constant with a label or initialise particular memory locations or labels with constants is an operator. In fact, the operators perform the arith- metic and logical tasks unlike directives that just direct the assembler to correctly interpret the program to code it appropriately. The following directives are commonly used in the assembly language programming practice using Microsoft Macro Assembler or Turbo Assembler. The directives and operators are discussed here but their meanings and uses will be more clear in Chapter 3 on assembly language programming techniques.  8086/8088 Instruction Set and Assembler Directives 69 DB: Define Byte The DB directive is used to reserve byte or bytes of memory locations in the available memory. While preparing the EXE file, this directive directs the assembler to allocate the specified number of memory bytes to the said data type that may be a constant, variable, string, etc. Another option of this directive also initialises the reserved memory bytes with the ASCII codes of the characters specified as a string. The fol- lowing examples show how the DB directive is used for different purposes. Example 2.47 RANKS DB OlH. 02H. 03H, 04H This statement directs the assembler to reserve four memory locations for a list named RANKS and initialise them with the above specified four values. MESSAGE DB 'GOOD MORNING' This makes the assembler reserve the number of bytes of memory equal to the number of char- acters in the string named MESSAGE and initialise those locations by the ASCII equivalent of these characters. VALUE DB 50H This statement directs the assembler to reserve 50H memory bytes and leave them uninitialised for the variable named VALUE. DW: Define Word The DW directive serves the same purposes as the DB directive, but it now makes the assembler reserve the number of memory words (16-bit) instead of bytes. Some examples are given to explain this directive. Example 2.48 WORDS OW 1234H, 4567H, 78ABH, 045CH, This makes the assembler reserve four words in memory (8 bytes), and initialize the words with the specified values in the statements. During initialisation, the lower bytes are stored at the lower memory addresses, while the upper bytes are stored at the higher addresses. Another option of the DW directive is explained with the DUP operator. WDATA OW 5 DUP (6666H) This statement reserves five words, i.e. 10-bytes of memory for a word lable WDATA and initia- lises all the word locations with 6666H. DQ: Define Quadword This directive is used to direct the assembler to reserve 4 words (8 bytes) of memory for the specified variable and may initialise it with the specified values. DT: Define Ten Bytes The DT directive directs the assembler to define the specified variable requiring IO-bytes for its storage and initialise the IO-bytes with the specified values. The directive may be used in case of variables facing heavy numerical calculations, generally processed by numerical processors. ASSUME: Assume Logical Segment Name The ASSUME directive is used to inform the as- semble, the names of the logicals segments to be assumed for different segments used in the program. In the assembly language program, each segment is given a name. For example, the code segment may be given the name CODE, data segment may be given the name DATA etc. The statement ASSUME CS : CODE directs the assembler that the machine codes are available in a segment named CODE, and hence the CS register is to be loaded with the address (segment) allotted by the operating system for the label CODE, while loading. Similary, ASSUME DS : DATA indicates to the assembler that the data items related to the program, are available in a logical segment named DA TA, and the DS register is to be initialised by the segment address 70 Advanced Microprocessors and Peripherals value decided by the operating system for the data segment, while loading. It then considers the segment DAT A as a default data segment for each memory operation, related to the data and the segment CODE as a source segment for the machine codes of the program. The ASSUME statement is a must at the starting of each assembly language program, without which a message 'CODE/DATA EMITTED WITHOUT SEG- MENT' may be issued by an assembler. END: END of Program The END directive marks the end of an assembly language program. When the assembler comes across this END directive, it ignores the source lines available later on. Hence, it should be ensured that the END statement should be the last statement in the file and should not appear in between. Also, no useful program statement should lie in the file, after the END statement. ENDP: END of Procedure In assembly language programming, the subroutines are called proce- dures. They may be independent program modules which return particular results or values to the calling programs. The ENDP directive is used to indicate the end of a procedure. A procedure is usually assigned a name, i.e. label. To mark the end of a particular procedure, the name of the procedure, i.e. label may appear as a prefix with the directive ENDP. The statements, appearing in the same module but after the ENDP direc- tive, are neglected from that procedure. The structure given below explains the use ofENDP. P ROC EDU RE ST AR STAR ENDP ENDS: END of Segment This directive marks the end of a logical segment. The logical segments are assigned with the names using the ASSUME directive. The names appear with the ENDS directive as prefixes to mark the end of those particular segments. Whatever are the contents of the segments, they should appear in the program before ENDS. Any statement appearing after ENDS will be neglected from the segment. The structure shown below explains the fact more clearly. DATA SEGMENT DATA ENDS ASSUME CS: CODE, OS DATA CODE SEGMENT CODE ENDS END The above structure represents a simple program containing two segments named DATA and CODE. The data related to the program must lie between the DATA SEGMENT and DATA ENDS statements. Similary, all the executable instructions must lie between CODE SEGMENT and CODE ENDS statements. EVEN: Align on Even Memory Address The assembler, while starting the assembling procedure of any program, initialises a location counter and goes on updating it, as the assembly proceeds. It goes on assigning the available addresses, i.e. the contents of the location counter, sequentially to the program vari- ables, constants and modules as per their requirements, in the sequence in which they appear in the program. The EVEN directive updates the location counter to the next even address, if the current location counter contents are not even, and assigns the following routine or variable or constant to that address. The structure given below explains the directive.  8086/8088 Instruction Set and Assembler Directives 71 EVEN PROCEDURE ROOT ROOT ENDP The above structure shows a procedure ROOT that is to be aligned at an even address. The assembler will start assembling the main program calling ROOT. When the assembler comes across the directive EVEN, it checks the contents of the location counter. If it is odd, it is updated to the next even value and then the ROOT procedure is assigned to that address, i.e. the updated contents of the location counter. If the content of the location counter is already even, then the ROOT procedure will be assigned with the same address. EQU: Equate The directive EQU is used to assign a label with a value or a symbol. The use of this di- rective is just to reduce the recurrence of the numerical values or constants in a program code. The recurring value is assigned with a label, and that label is used in place of that numerical value, throughout the program. While assembling, whenever the assembler comes across the label, it substitutes the numerical value for that label and finds out the equivalent code. Using the EQU directive, even an instruction mnemonic can be assigned with a label, which can then be used in the program in place of that mnemonic. Suppose, a numeri- cal constant which appears in a program ten times. If that constant is to be changed at a later time, one will have to make the correction 10 times. This may lead to human errors, because it is possible that a human programmer may miss one of those corrections. This will result in the generation of wrong codes. If the EQU directive is used to assign the value with a label that can be used in place of each recurrence of that constant, only one change in the EQU statement will give the correct and modified code. The examples given below show the syntax. Example 2.49 LABEL EQU 0500H ADDITION EQU ADD The first statement assigns the constant SOOH with the label LABEL, while the second statement assigns another label ADDITION with mnemonic ADD. EXTRN: External and PUBLIC: Public The directive EXTRN informs the assembler that the names, procedures and labels declared after this directive have already been defined in some other assembly language modules. While in the other module, where the names, procedures and labels actually appear, they must be declared public, using the PUBLIC directive. If one wants to call a procedure FACTORIAL ap- pearing in MODULE! from MODULE 2; in MODULE!, it must be declared PUBLIC using the statement PUBLIC FACTORIAL and in module 2, it must be declared external using the declaration EXTRN FACTO- RIAL. The statement of declaration EXTRN must be accompained by the SEGMENT and ENDS directives of the MODULE 1, before it is called in MOBULE 2. Thus the MODULE I and MO