Chapter 5- Interruptsx.pdf

Chapter 5 Interrupt Interface of the 8088 and 8086 Microprocessors µProcessors & Assembly Language Dr. Bassel Soudan & ١ Dr. Ali El-Moursy  Interrupt Mechanism, Types, and Priority Quickly chan...

Chapter 5 Interrupt Interface of the 8088 and 8086 Microprocessors µProcessors & Assembly Language Dr. Bassel Soudan & ١ Dr. Ali El-Moursy  Interrupt Mechanism, Types, and Priority Quickly changing the program environment Either interrupt from within the processor or from an external device. Processor suspend what it is doing in the main part of the program and passes control to a special routine. Interrupt service routine. µProcessors & Assembly Language Dr. Bassel Soudan & ٢ Dr. Ali El-Moursy  Interrupt Mechanism Interrupt 32 occurs during execution of Main Program instruction N in the Instruction N main Program Instruction N+1 : : End of Program Service Subroutine Service routine for interrupt 32 Return µProcessors & Assembly Language Dr. Bassel Soudan & ٣ Dr. Ali El-Moursy  Interrupt Priority Priority is set as below Reset Increasing Internal interrupts & Exceptions Priority Software interrupts Nonmaskable interrupts External interrupts µProcessors & Assembly Language Dr. Bassel Soudan & ٤ Dr. Ali El-Moursy  Interrupt Priority Cont. Lower priority has to wait. Example 1, – If the 8088/8086 is servicing interrupt 50 of the External Hardware. What other interrupts can be serviced: Answer µProcessors & Assembly Language Dr. Bassel Soudan & ٥ Dr. Ali El-Moursy  Interrupt Activation Mechanism Up to 256 interrupts Divided into five groups: – External Hardware interrupts
INTR – Nonmaskable
NMI – Software interrupt
INT n instruction – Internal interrupt
Internal signals / TEST – Reset
RESET µProcessors & Assembly Language Dr. Bassel Soudan & ٦ Dr. Ali El-Moursy  The 8088/8086 Pin Layout µProcessors & Assembly Language Dr. Bassel Soudan & ٧ Dr. Ali El-Moursy  The Status Register A 16 bit register to hold indicator bits. Not all bits are used. 11 10 9 8 7 6 4 2 0 OF DF IF TF SF ZF AF PF CF Carry Flag Parity Flag Auxiliary Carry Zero Sign Flag Trap Flag Interrupt Enable Direction Flag Overflow Flag µProcessors & Assembly Language Dr. Bassel Soudan & 8 Dr. Ali El-Moursy  Steps to Serve an Interrupt On interrupt: 1. Old flags are saved on the stack. 2. Then IF & TF are cleared. 3. Old CS & IP pushed onto the stack. 4. New CS & IP read from memory 5. Program execution resumes at CSnew:IPnew µProcessors & Assembly Language Dr. Bassel Soudan & ٩ Dr. Ali El-Moursy  Interrupt Vector Table Address Pointer Table 3FE Vector 3 – Breakpoint Vector 2 – NMI 1Kbyte ROM 06 CS1 Vector 1 – Single Step 04 IP1 02 CS0 – Base Vector 0 – Divide Error 00 IP0 – offset µProcessors & Assembly Language Dr. Bassel Soudan & ١٠ Dr. Ali El-Moursy  Interrupt Vector Table Example 2, – What is the address of the interrupt INT 50, find the CS and IP address Answer: µProcessors & Assembly Language Dr. Bassel Soudan & ١١ Dr. Ali El-Moursy  Software Interrupts Service subroutines are initiated in response to the execution of a software interrupts instructions. Not an event in external hardware. INT n initiate a software interrupt Software interrupts are of a higher priority than external interrupts. µProcessors & Assembly Language Dr. Bassel Soudan & ١٢ Dr. Ali El-Moursy  Software Interrupt Instructions INT n: – Software interrupt instruction. – Program will transfer the the subroutine pointed to by vectors. Steps for INT n: 1. MPU saves old flags onto stack. 2. Clears TF, IF. 3. Saves CS & IP. 4. Reads IP50 & CS50 from address 000C8H & 000CAH. 5. CS:IP starts to fetch. µProcessors & Assembly Language Dr. Bassel Soudan & ١٣ Dr. Ali El-Moursy  Software Interrupt Instructions Cont. IRET – Interrupt Return – Must be used at the end of each ISR – Causes old value of flags to be popped – CS & IP are popped µProcessors & Assembly Language Dr. Bassel Soudan & ١٤ Dr. Ali El-Moursy  External Hardware Interrupts Interrupt-enable Flag bit IF: affects only the external hardware interrupts to Enable/Disable them. External input = INTR During execution of interrupt, the Processor clears IF µProcessors & Assembly Language Dr. Bassel Soudan & ١٥ Dr. Ali El-Moursy  The Status Register A 16 bit register to hold indicator bits. Not all bits are used. 11 10 9 8 7 6 4 2 0 OF DF IF TF SF ZF AF PF CF Carry Flag Parity Flag Auxiliary Carry Zero Sign Flag Trap Flag Interrupt Enable Direction Flag Overflow Flag µProcessors & Assembly Language Dr. Bassel Soudan & 16 Dr. Ali El-Moursy  External Hardware Interrupt Instructions CLI & STI: – Manipulate the interrupt flag through software – STI enables the external interrupt request (INTR) – CLI disables the external interrupt request (INTR) µProcessors & Assembly Language Dr. Bassel Soudan & ١٧ Dr. Ali El-Moursy  Nonmaskable Interrupt NMI: 1. Cannot be masked out with the interrupt flag 2. Apply logic 1 at the NMI input, not INTR input. 3. NMI input is positive edge-triggered µProcessors & Assembly Language Dr. Bassel Soudan & ١٨ Dr. Ali El-Moursy  Nonemaskable Interrupts Cont. 0  1 on NMI input, NMI flip-flop MPU is set Must be active two consecutive clock cycles Current flags, CS & IP pushes into stack NMI vectors from type 2 NMI type of interrupts must respond to immediately (power failure & memory-read error) µProcessors & Assembly Language Dr. Bassel Soudan & ١٩ Dr. Ali El-Moursy  Reset Interrupt Reset: hardware means of initializing the MPU. Happens at power up, but PC allow time for warm up This will synchronize the Reset with the clock. MPU when it sees RESET, terminates operations, Bus = Z state µProcessors & Assembly Language Dr. Bassel Soudan & ٢٠ Dr. Ali El-Moursy  Internal Interrupts Functions Divide Error: – IDIV or DIV larger than specified destination – Type 0 interrupt Overflow Error: – Results of any arithmetic operation – Not like Divide error, transfer is not automatic – INT 0 after arithmetic instruction – Type 4 – Could cause a message to be displayed µProcessors & Assembly Language Dr. Bassel Soudan & ٢١ Dr. Ali El-Moursy  Internal Interrupt Instructions INTO – Interrupt-on-overflow – Must be included after arithmetic instructions – Type 4 interrupt – IP at 0010H & CS at 00012H µProcessors & Assembly Language Dr. Bassel Soudan & ٢٢ Dr. Ali El-Moursy  Internal Interrupts Functions Cont. Single Step: – TF is set, the single step operation is enabled – Software control – Type 1 – Program can be executed one instruction at a time-debugging – Could include WAIT inside the subroutine Breakpoint: – CC instructions – Cause execution to stop at a certain location µProcessors & Assembly Language Dr. Bassel Soudan & ٢٣ Dr. Ali El-Moursy  The Status Register A 16 bit register to hold indicator bits. Not all bits are used. 11 10 9 8 7 6 4 2 0 OF DF IF TF SF ZF AF PF CF Carry Flag Parity Flag Auxiliary Carry Zero Sign Flag Trap Flag Interrupt Enable Direction Flag Overflow Flag µProcessors & Assembly Language Dr. Bassel Soudan & 24 Dr. Ali El-Moursy  Interrupt Instructions Cont. HLT & Wait: – Halt: Processor suspends operation & initiates idle states – Wait: Processor checks the logic level of TEST input prior to going to idle state only if TEST = 1 Processor will go idle state. While in idle state, Processor checks the login level at TEST it goes to zero execution resumes. µProcessors & Assembly Language Dr. Bassel Soudan & ٢٥ Dr. Ali El-Moursy  Interrupt Instructions Symbol Meaning Format Operation Flags affected CLI Clear interrupt flag CLI 0  (IF) IF STI Set interrupt flag STI 1  (IF) IF INT n Type n software INT n Flag  ((SP)-2) TF, IF interrupt 0  TF, IF CS  ((SP)-4) (2 + 4.n)  (CS) (IP)  ((SP) –6) (4.n)  (IP) IRET Interrupt Return IRET (SP)  (IP) All ((SP) + 2 )  (CS) ((SP) + 4 )  (Flags) ((SP) + 6 )  (SP) INTO Interrupt on overflow INTO INT 4 steps TF, IF HLT Halt HLT Wait for external interrupt or None reset to occur WAIT Wait WAIT Wait for TEST input to go active None µProcessors & Assembly Language Dr. Bassel Soudan & ٢٦ Dr. Ali El-Moursy