Lec13-4471029-ISA (MIPS Case Study) 5th PDF

ISA : MIPS Case Study (Misc.) 471029: Introduction to Computer Architecture 13th Lecture Disclaimer: Slides are mainly based on COD 5th textbook and also developed in part by Profs. Dohyung Kim @ KNU and Computer architecture course @ KAIST and SKKU...

ISA : MIPS Case Study (Misc.) 471029: Introduction to Computer Architecture 13th Lecture Disclaimer: Slides are mainly based on COD 5th textbook and also developed in part by Profs. Dohyung Kim @ KNU and Computer architecture course @ KAIST and SKKU 1 Character Data  Byte-encoded character sets  ASCII: 128 characters  95 graphic, 33 control  Latin-1: 256 characters  ASCII, +96 more graphic characters  Unicode: 32-bit character set  Used in Java, C++ wide characters, …  Most of the world’s alphabets, plus symbols  UTF-8, UTF-16: variable-length encodings  Keeps ASCII subset as 8 bits and uses 16 or 32 bits for other characters 2 Byte/Halfword Operations  Could use bitwise operations  MIPS byte/halfword load/store  String processing is a common case lb rt, offset(rs) lh rt, offset(rs)  Sign extend to 32 bits in rt (load byte/halfword) lbu rt, offset(rs) lhu rt, offset(rs)  Zero extend to 32 bits in rt sb rt, offset(rs) sh rt, offset(rs)  Store just rightmost byte/halfword 3 4 Loading a 32-Bit Constant  Most constants are small I-format op rs rt constant or address  16-bit immediate is sufficient 6 bits 5 bits 5 bits 16 bits  Occasionally 32-bit constant used 0000 0000 0011 1101 0000 1001 0000 0000  Compiled MIPS code: lui $s0, 61 // 61 = 0000 0000 0011 11012  the value of $s0 : 0000 0000 0011 1101 0000 0000 0000 0000 ori $s0, $s0, 2304 // 2304 = 0000 1001 0000 00002  the value of $s0 : 0000 0000 0011 1101 0000 1001 0000 0000 5 Branch Addressing  Instructions:  bne $s0, $s1, L1  beq $s0, $s1, L2  Branch instruction I format op rs rt constant or address 6 bits 5 bits 5 bits 16 bits  Most branch targets are near branch  Forward or backward  PC-relative addressing  Target address = Register + Branch address  PC = PC + (offset x 4)  PC already incremented by 4 by this time 6 Jump Addressing  Instructions  j L1  jal L2  Jump targets could be anywhere in text segment  Encode full address in instruction op address 6 bits 26 bits  Direct jump addressing  Target address = PC31…28 : (address x 4) 7  Pseudo-direct Jump  Example 0x12345678: j L2 00010 00 0001 0000 0000 0000 0000 0000 0x2 0x100000 0001 0010 0011 0100 0101 0110 0111 1000 0001 0000 0100 0000 0000 0000 0000 0000 0x10400000 8  Target Addressing Example  Loop code from earlier example  Assume loop at location 80000 Loop: sll $t1, $s3, 2 80000 0 0 19 9 2 0 add $t1, $t1, $s6 80004 0 9 22 9 0 32 lw $t0, 0($t1) 80008 35 9 8 0 bne $t0, $s5, Exit 80012 5 8 21 2=(80012+4) + 2*4 addi $s3, $s3, 1 80016 8 19 19 1 j Loop 80020 2 20000 Exit: … 80024 9 Branching Far Away  What if the branch destination is further away than can be captured in 16 bits?  The assmebler comes to the rescue  It inserts an unconditional jump to the branch target and inverts the condition beq $s0, $s1, L1 Not satisfied bne $s0, $s1, L2 J L1 L2: 10 MIPS Addressing Modes 11 MIPS Multiplication  Two 32-bit registers for product  HI: most-significant 32 bits  LO: least-significant 32-bits  Instructions  64-bit product in HI/LO mult rs, rt / multu rs, rt  Move from HI/LO to rd  Can test HI value to see if product overflows 32 bits mfhi rd / mflo rd  Least-significant 32 bits of product  rd mul rd, rs, rt 12 MIPS Multiplication (cont’d)  Two 32-bit registers for product  HI: most-significant 32 bits  LO: least-significant 32-bits  Instructions li $a0 5 li $a1 3 mult $a0 $a1 mfhi $a2  32 most significant bits of multiplication to $a2 mflo $v0  32 least significant bits of multiplication to $v0 13 MIPS Division  Use HI/LO registers for result  HI: 32-bit remainder  LO: 32-bit quotient  Instructions div rs, rt / divu rs, rt LO = quotient of “rs / rt”;  HI = remainder of “rs / rt”;  No overflow or divide-by-0 checking  Software must perform checks if required  Use mfhi, mflo to access result 14 MIPS Division (cont’d)  Use HI/LO registers for result  HI: 32-bit remainder  LO: 32-bit quotient  Instructions div $a0, $a1 mfhi $a2  Remainder to $a2 mflo $v0  Quotient to $v0 15 Reading Recommended  Chapter 3  3.2 Addition and Subtraction  3.3 Multiplication  3.4 Division  3.5 Floating Point 16