MIPS Case Study Lecture Notes PDF

ISA : MIPS Case Study 471029: Introduction to Computer Architecture 9th Lecture Disclaimer: Slides are mainly based on COD 5th textbook and also developed in part by Profs. Dohyung Kim @ KNU and Computer architecture course @ KAIST and SKKU...

ISA : MIPS Case Study 471029: Introduction to Computer Architecture 9th Lecture Disclaimer: Slides are mainly based on COD 5th textbook and also developed in part by Profs. Dohyung Kim @ KNU and Computer architecture course @ KAIST and SKKU 1 Data Format ¢ Assume MIPS-32 ¢ Most things are 32 bits § Instruction and data addresses § signed and unsigned integers ¢ Also 16-bit word and 8-bit word (aka byte) ¢ Floating-point numbers § IEEE standard 754 § Single precision(e.g., float): 8-bit exponent(E), 23-bit significand(F) §(-1)S x F x 2(exponent) ß Not exactly this though § Fraction(aka significand) § Double precision(e.g., double): 11-bit exponent, 52-bit significand 2 MIPS-32 ISA ¢ Instruction categories § Computational § Load/Store § Jump and Branch § Floating point § Memory Management § Special 3 MIPS-32 ISA (cont’d) ¢ Three Instruction Format § R-type, 3 register operands 0 rs rt rd shamt funct R-type 6-bit 5-bit 5-bit 5-bit 5-bit 6-bit § I-type, 2 register operands and 16-bit immediate opcode rs rt immediate I-type 6-bit 5-bit 5-bit 16-bit § J-type, 26-bit immediate operand opcode immediate J-type 6-bit 26-bit ¢ Simple Decoding § 4 bytes per instruction, regardless of format § must be 4-byte aligned § format and fields readibly extractable 4 MIPS Design Principles ¢ Simplicity favors regularity § Fixed size instructions § Small number of instruction formats § Opcode always the first 6 bits ¢ Smaller is faster § Limited instruction set § Limited number of registers in register file § Limited number of addressing modes ¢ Make the common case fast § Arithmetic operands from the register file § Allow instructions to contain immediate operands 5 MIPS Arthmetic Instructions ¢ Arithmetic operations § Add and subtract, three operands § Two sources and one destination add a, b, c # a = b + c sub a, b, c # a = b - c § All arithmetic operations have this form § Design Principle 1: Simplicity favors regularity – Regularity makes implementation simpler – Simplicity enables higher performance at lower cost 6 MIPS Register Operands ¢ Arithmetic instructions use register operands ¢ MIPS has a 32 x 32-bit register file § Use for frequently accessed data § Numbered 0 to 31 § 32-bit data called a “word” ¢ Assembler names § $t0, $t1, …, $t9 for temporary values § $s0, $s1, …, $s7 for saved variables ¢ Design Principle 2: Smaller is faster § (cf.) Main memory: millions of locations 7 MIPS Register Operand Example ¢ C code: f = (g + h) – (i + j); * Assume f, g, h, i, j in $s0, $s1, $s2, $s3, $s4 ¢ Compiled MIPS code: add $t0, $s1, $s2 add $t1, $s3, $s4 sub $s0, $t0, $t1 8 MIPS Register Operand Example ¢ C code: f = (g + h) – (i + j); * Assume f, g, h, i, j in $s0, $s1, $s2, $s3, $s4 ¢ Compiled MIPS code: add $t0, $s1, $s2 add $t1, $s3, $s4 sub $s0, $t0, $t1 9 MIPS Register Operand Example ¢ C code: f = (g + h) – (i + j); * Assume f, g, h, i, j in $s0, $s1, $s2, $s3, $s4 ¢ Compiled MIPS code: add $t0, $s1, $s2 add $t1, $s3, $s4 sub $s0, $t0, $t1 10 MIPS Register Operand Example ¢ C code: f = (g + h) – (i + j); * Assume f, g, h, i, j in $s0, $s1, $s2, $s3, $s4 ¢ Compiled MIPS code: add $t0, $s1, $s2 add $t1, $s3, $s4 sub $s0, $t0, $t1 11 MIPS Register Convention Register 1 ($at) reserved for assembler, 26-27 for operating system 12 MIPS Memory Operands ¢ Main memory used for composite data § Arrays, structures, dynamic data ¢ To apply arithmetic operations § Load values from memory into registers § Store result from register to memory ¢ Memory is byte addressed § Each address identifies an 8-bit(byte) ¢ Words are aligned in memory § Address must be a multiple of 4 ¢ MIPS is Big Endian § Most-significant byte at least address of a word 13  Aside: Big Endian vs. Little Endian ¢ 32-bit signed or unsigned integer comprises 4 bytes MSB LSB (most significant) 8-bit 8-bit 8-bit 8-bit (least significant) ¢ On a byte-addressable machine… Big Endian Little Endian MSB LSB MSB LSB byte 0 byte 1 byte 2 byte 3 byte 3 byte 2 byte 1 byte 0 byte 4 byte 5 byte 6 byte 7 byte 7 byte 6 byte 5 byte 4 byte 8 byte 9 byte 10 byte 11 byte 11 byte 10 byte 9 byte 8 byte 12 byte 13 byte 14 byte 15 byte 15 byte 14 byte 13 byte 12 byte 16 byte 17 byte 18 byte 19 byte 19 byte 18 byte 17 byte 16 pointer points to the big end pointer points to the little end ¢ What difference does it make? 14 MIPS Memory Operand Example (1) ¢ C code: g = h + A; * Assume g in $s1, h in $s2, base address of A in $s3 ¢ Compiled MIPS code: § 4 bytes per word § Index 8 requires offset of 32 lw $t0, 32($s3) // load word add $s1, $s2, $t0 15 MIPS Memory Operand Example (1) ¢ C code: g = h + A; * Assume g in $s1, h in $s2, base address of A in $s3 ¢ Compiled MIPS code: § 4 bytes per word § Index 8 requires offset of 32 lw $t0, 32($s3) // load word add $s1, $s2, $t0 offset base register 16 MIPS Memory Operand Example (1) ¢ C code: g = h + A; * Assume g in $s1, h in $s2, base address of A in $s3 ¢ Compiled MIPS code: § 4 bytes per word § Index 8 requires offset of 32 lw $t0, 32($s3) // load word add $s1, $s2, $t0 17 Register vs. Memory ¢ Registers are faster to access than memory ¢ Operating on memory data requires loads and stores § More instructions to be executed ¢ Compiler must use registers for variables as much as possible § Only spill to memory for less frequently used variables § Register optimization is important 18 MIPS Immediate Instructions ¢ Constant data specified in an instruction addi $s3, $s3, 4 ¢ No subtract immediate instruction § Just use a negative constant addi $s2, $s2, -1 ¢ Design Principle 3: Make the common cast fast § Small constants are common § Immediate operand avoids a load instruction 19 MIPS Constant ¢ The constant zero § MIPS register 0($zero) is the constant 0 § Cannot be overwritten § Useful for common operations § E.g., move between registers add $t2, $s1, $zero 20