Lec10-4471029 (MIPS Case Study) 2nd PDF

ISA : Preliminary for Representing Instructions 471029: Introduction to Computer Architecture 10th Lecture Disclaimer: Slides are mainly based on COD 5th textbook and also developed in part by Profs. Dohyung Kim @ KNU and Computer architecture course @ KAIST and SKKU...

ISA : Preliminary for Representing Instructions 471029: Introduction to Computer Architecture 10th Lecture Disclaimer: Slides are mainly based on COD 5th textbook and also developed in part by Profs. Dohyung Kim @ KNU and Computer architecture course @ KAIST and SKKU 1 Unsigned binary integers  Given an n-bit number x  x n1 2n1  x n2 2n2    x1 21  x 0 20  Range: 0 to + 2n – 1  Example  0000 0000 0000 0000 0000 0000 0000 10112 = 0 + … + 1x23 + 0x22 + 1x21 + 1x20 = 0 + … + 8 + 0 + 2 + 1 = 1110  Using 32 bits  0 to +4,294,967,295 2 2s-Complement Signed Integers  Given an n-bit number x   x n1 2n1  x n2 2n2    x1 21  x 0 20  Range: -2n-1 to + 2n-1 – 1  Example  1111 1111 1111 1111 1111 1111 1111 11002 = -1x231 + 1x230 + … + 1x22 + 0x21 + 0x20 = -2,147,483,648 + 2,147,483,644 = -410  Using 32 bits  -2,147,483,648 to +2,147,483,647 3 2s-Complement Signed Integers  Bit 32 is sign bit  1 for negative numbers  0 for non-negative numbers  Non-negative numbers have the same unsigned and 2s- complement representation  But not vice-versa…  Some specific numbers  0: 0000 0000 …. 0000  -1: 1111 1111 …. 1111  Most-negative: 1000 0000 …. 0000  Most-positive: 0111 1111 …. 1111 4 Signed Negation  Complement and add 1  Complement means 1  0, 0  1 x  x  1111...1112  1 x  1  x  Example: negate + 1  +2 = 0000 0000 … 00102  –2 = 1111 1111 … 11012 + 1 = 1111 1111 … 11102 5  [Remind] Integer C Puzzles x < 0  ((x*2) < 0) ux >= 0 x & 7 == 7  (x y  -x < -y x * x >= 0 Initialization x > 0 && y > 0  x + y > 0 x >= 0  -x >31 == -1 unsigned ux = x; x & (x-1) != 0 unsigned uy = y; 6 Sign Extension  Representing a number using more bits  Preserve the numeric value  Replicate the sign bit to the left  c.f. unsigned values: extend with 0s  Examples: 8-bit to 16-bit  +2: 0000 0010 => 0000 0000 0000 0010  –2: 1111 1110 => 1111 1111 1111 1110  In MIPS instruction set  addi: extend immediate value  lb, lh: extend loaded byte/halfword  beq, bne: extend the displacement 7 ISA : Representing Instructions 471029: Introduction to Computer Architecture 10th Lecture Disclaimer: Slides are mainly based on COD 5th textbook and also developed in part by Profs. Dohyung Kim @ KNU and Computer architecture course @ KAIST and SKKU 8 Representing Instructions  Instructions are encoded in binary  Called machine code  MIPS instructions  Encoded as 32-bit instruction words  Small number of formats encoding operation code(opcode), register numbers, …  Regularity!  Register numbers  $t0 ~ $t7 are registers 8 ~ 15  $t8 ~ $t9 are registers 24 ~ 25  $s0 ~ $s7 are registers 16 ~ 23 9  Instruction Sets: A Thin Interface Syntax : ADD t0,t1,t2 (ADD $8 $9 $10) Semantics : $8 = $9 + $10 : register operands In Hexadecimal : 012A4020 10 MIPS R-format Instructions  opcode:  Basic operation of the instruction, typically called the opcode  Several related instructions can have the same opcode  rs(register source), rt(register target), rd(register destination)  Numeric representation of the source & destination registers  shamt(shift amount)  Used with shift/rotate instruction  funct(function)  Differentiate the different functions that share an opcode  e.g., 0x00  ALU, funct selects which ALU function to use (func=32)  add; (func=34)  sub; 11 MIPS R-format Instructions (cont’d) Syntax: ADD $8 $9 $10 Semantics: $8 = $9 + $10 12 MIPS R-format Example op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add $t0, $s1, $s2 special $s1 $s2 $t0 0 add 0 17 18 8 0 32 000000 10001 10010 01000 00000 100000 000000100011001001000000001000002 = 0x02324020 13 MIPS I-format Instructions op rs rt constant or address 6 bits 5 bits 5 bits 16 bits  Immediate arithmetic and load/store instructions  rt: destination or source register number  constant: -215 to + 215 – 1  address: offset added to base address in rs  Design Principle 4: Good design demands good compromises  Different formats complicate decoding, but allow 32-bit instructions uniformly  Keep formats as similar as possible 14 MIPS I-format Instructions (cont’d) Syntax: BEQ $1, $2, 25 Action : If ($1 != $2), PC = PC + 4 If ($1 == $2), PC = PC + 4 + 4*25 15 Immediate Addressing on MIPS  Useful for loading constants  li $7, 12 # load constant 12 into reg $7  Opcode determines the format  or, and, xor, and add instructions have immediate forms (ori, andi, xori, and addi), e.g.,  ori $8, $0, 0x123 # puts 0x0000 0123 into reg $8 (note: zero extension…)  ori $9, $0, -6 # puts 0x0000 fffa into reg $9  addi $10, $0, 0x123 # puts 0x0000 0123 into reg $10  addi $11, $0, -6 # puts 0xffff fffa into reg $11 (note: sign extension…)  lui instruction loads upper 16 bits with constant and sets LS 16 bits to zero  lui $8, 0xabcd # puts 0xabcd 0000 into reg $8  ori $0, $8, 0x123 # sets ls bits; (reg $0 = 0xabcd 0123) 16 MIPS J-format Instructions  Only used by unconditional jumps, e.g.,  j dest_addr # jump to (target > srl Bitwise AND & & and, andi Bitwise OR | | or, ori Bitwise NOT ~ ~ nor 19 MIPS Shift Operations  shamt: how many position to shift  Shift left logical  Shift left and fill with 0 bits  sll by i bits multiples by 2i  Shift right logical  Shift right and fill with 0 bits  srl by i bits devides by 2i (unsigned only)  (cf.,) sra: shift right arithmetic 20 [Aside] SHL : Logical Shift Left on x86 & M1  Intel datasheet  “Intel 64 and IA-32 Architecture Software Developer’s Manual” says….  So thus, “1