Lec 21 MIPS Pipelining (Cont'd) PDF

PCSrc 0 M u x 1 IF/ID ID/EX EX/MEM MEM/WB...

PCSrc 0 M u x 1 IF/ID ID/EX EX/MEM MEM/WB Add Add 4 Add result Branch Shift RegWrite left 2 Read MemWrite Instruction PC Address register 1 Read data 1 Read ALUSrc Zero Zero MemtoReg Instruction register 2 Registers Read ALU ALU memory Write 0 Read data 2 result Address 1 register M data u M Data u Write x memory data x 1 0 Write data Instruction [15– 0] 16 32 6 Sign ALU extend control MemRead Instruction [20– 16] 0 M ALUOp Instruction u [15– 11] x 1 RegDst 1 Pipelining : Data Dependence Handling 471029: Introduction to Computer Architecture 21th Lecture Disclaimer: Slides are mainly based on COD 5th textbook and also developed in part by Profs. Dohyung Kim @ KNU and Computer architecture course @ KAIST and SKKU 2 Readings for Next Few Lectures  Smith and Sohi, “The Microarchitecture of Superscalar Processors”, Proceedings of the IEEE, 1995  More advanced pipelining  Interrupt and exception handling  Out-of-order and superscalar execution concepts 3 How to Handle Data Dependences  Anti and output dependences are easier to handle  write to the destination in one stage and in program order  Flow dependences are more interesting  Five fundamental ways of handling flow dependences  Detect and wait until value is available in register file  Detect and forward/bypass data to dependent instruction  Detect and eliminate the dependence at the software level  No need for the hardware to detect dependence  Predict the needed value(s), execute “speculatively”, and verify  Do something else (fine-grained multithreading)  No need to detect 4 Interlocking  Detection of dependence between instructions in a pipelined processor to guarantee correct execution  Software based interlocking vs.  Hardware based interlocking  MIPS acronym? 5 Approaches to Dependence Detection (I)  Scoreboarding  Each register in register file has a Valid bit associated with it  An instruction that is writing to the register resets the Valid bit  An instruction in Decode stage checks if all its source and destination registers are Valid  Yes: No need to stall.. No dependence  No: Stall the instruction  Advantage:  Simple. 1 bit per register  Disadvantage:  Need to stall for all types of dependences, not only flow dep. 6 Approaches to Dependence Detection (II)  Combinational dependence check logic  Special logic that checks if any instruction in later stages is supposed to write to any source register of the instruction that is being decoded  Yes: stall the instruction/pipeline  No: no need to stall … no flow dependence  Advantage:  No need to stall on anti and output dependences  Disadvantage:  Logic is more complex than a scoreboard  Logic becomes more complex as we make the pipeline deeper and wider (flash-forward: think superscalar execution) 7 Once You Detect the Dependence in Hardware  What do you do afterwards?  Observation: Dependence between two instructions is detected before the communicated data value becomes available  Option 1: Stall the dependent instruction right away  Option 2: Stall the dependent instruction only when necessary  data forwarding/bypassing  Option 3: … 8