Digital Electronics Lab Experiment 1 PDF

Military Institute of Science and Technology Department of Electrical Electronics & communication Engineering Course Code: EECE-304 (Digital Electronics Lab) Experiment No: 01 INTRODUCTION TO BASIC GATES AND LOGIC SIMPLIFICATION TECHNIQUES WITH DISCR...

Military Institute of Science and Technology Department of Electrical Electronics & communication Engineering Course Code: EECE-304 (Digital Electronics Lab) Experiment No: 01 INTRODUCTION TO BASIC GATES AND LOGIC SIMPLIFICATION TECHNIQUES WITH DISCRETE LOGIC. BRIEF FOLLOW UP ON BOOLEAN ALGEBRA AND K-MAP AND GRAY CODE-BINARY CODE CONVERSION. 1 What is Digital Electronics? Digital electronics is the branch of electronics that deals with the study of digital signals and the components that use or create them. Components of Digital Electronics: Active components Passive components The active components are the transistors and diodes, while passive components are the capacitors, resistors, inductors, etc. 2 Logic Gates Logic gates are the basic components of the digital circuit with one output and more than one input. 3 Basic Logic Gates – There are three basic logic gates: AND Gate OR Gate NOT Gate Universal Logic Gates – In digital electronics, the following two logic gates are considered as universal logic gates: NOR Gate NAND Gate Derived Logic Gates – The following two are the derived logic gates used in digital systems: XOR Gate XNOR Gate 4 AND Gate It generates a high or logic 1 output, only when all the inputs applied to it are high or logic 1. Otherwise, the output of the AND gate is low or logic 0. Properties of AND Gate: AND gate can accept two or more than two input values at a time. When all the inputs are logic 1, the output of this gate is logic 1. For two-input AND gate, the Boolean expression is given by, Z=A.B We can extend this expression to any number of input variables, such as, Z=A.B.C.D…Z=A.B.C.D… 5  TRUTH TABLE OF AND GATE: 6 OR Gate It produces a low or logic 0 output only when it’s all inputs are low or logic 0. For all other input combinations, the output of the OR gate is high or logic 1. § An OR gate can be designed to have two or more inputs but only one output. § The primary function of the OR gate is to perform the logical sum operation. Properties of OR Gate: It can have two or more input lines at a time. When all of the inputs to the OR gate are low or logic 0, the output of it is low or logic 0. The boolean expression for a two input OR gate is given by, Z=A+B The boolean expression for a three-input OR gate is, Z=A+B+C 7 TRUTH TABLE OF OR GATE: 8 NOT Gate or Inverter Used to perform compliment of an input. § It takes only one input and one output. § The output of the NOT gate is complement of the input applied to it. § Therefore, if we apply a low or logic 0 output to the NOT gate is gives a high or logic 1 output and vice-versa. § The NOT gate is also known as inverter, as it performs the inversion operation. § The logical operation of the NOT gate is described by its boolean expression, which is given below. Z=A’ 9 TRUTH TABLE OF NOT GATE: 10 NOR Gate It can take two or more inputs but one output. It is basically a combination of two basic logic gates i.e., OR gate and NOT gate. A NOR gate gives a high or logic 1 output only when its all inputs are low or logic 0. Thus, it can be expressed as, NOR Gate = OR Gate + NOT Gate The boolean expression of a two input NOR gate is given below: C=(A+B)’ In the above boolean expressions, the variables A and B are called input variables while the variable C is called the output variable. 11 TRUTH TABLE OF NOR GATE: 12 NAND Gate The NAND gate performs the inverted operation of the AND gate. NAND gate can also have two or more input lines but only one output line. NAND gate produces a low or logic 0 output only when its all inputs are high or logic 1. The NAND gate is also represented as a combination of two basic logic gates namely, AND gate and NOT gate. Hence, it can be expressed as NAND Gate = AND Gate + NOT Gate Here is the boolean expression of a two input NAND gate. C=(AB)’ In this expression, A and B are the input variables and C is the output variable. We can extend this relation to any number of input variables like three, four, or more. 13 TRUTH TABLE OF NAND GATE: 14 Exclusive OR- Gate (XOR Gate) XOR gate is used in digital circuits to perform modulo sum. It is also referred to as Exclusive OR gate or Ex-OR gate. The XOR gate can take only two inputs at a time and give an output. The output of the XOR gate is high or logic 1 only when its two inputs are dissimilar. The following is the boolean expression for the output of the XOR gate. Z=A⊕B Here, Z is the output variable, and A and B are the input variables. This expression can also be written as follows: Z=(A’B)+(AB’) 15  Truth Table of XOR Gate: 16  All theorems maintain duality. Replace + with. and replace 1 with 0 BOOLEAN ALGEBRA 1 7 Axioms Single Variable Thm. Two/Three Variable Thm.  SUM OF PRODUCTS For a function of n variables, a product term in which each of the n variables appears once is called a minterm. The variables may appear in a minterm either in uncomplemented or complemented form.  SUM OF PRODUCTS Any function f can be represented by a sum of minterms that correspond to the rows in the truth table for which f = 1 The resulting implementation is functionally correct and unique, but it is not necessarily the lowest-cost implementation of f. If each product term in a sum of 𝒇 𝒙 𝟏 , 𝒙𝟐 , 𝒙𝟑 = 𝒎 𝟏 + 𝒎 𝟒 + 𝒎 𝟓 + 𝒎 𝟔 products expression, f is a minterm, 1 then the expression is called a 9 canonical sum-of-products for the function f.  PRODUCT OF SUMS It is also possible to synthesize f by considering the rows for which f = 0. (from Principle of duality) This alternative approach uses the complements of minterms, which are called maxterms. KARNAUGH MAPS Two variable map Three variable map Four variable map The adjacent combinations cannot differ by more than 1 bit, i.e. gray coding Karnaugh map minimization (SOP) Steps: Draw the K-map and place the 1’s according to the defined function.  KARNAUGH MAP MINIMIZATION (SOP) Find the largest groups of 1’s that is a power of 2 (2,4,8,16 etc). You need to make sure that the 1’s are adjacent to each other. Once you have found a group, you will need to write the minterm for it. Of x1, x2, x3 etc. some will remain constant within the group and some will change. Only those that remain constant within the group 23 will appear in the minterm in either complemented or uncomplemented form. KARNAUGH MAP MINIMIZATION (SOP) Continue doing this for all groups of 4 24  KARNAUGH MAP MINIMIZATION (SOP) Once groups of 4 are finished, look for groups of 2 Remember that for a group to be valid, there needs to be at least 1 non-common one inside it Once all one’s have been covered, just sum up the minterms and you have the 25 minimum cost SOP  KARNAUGH MAP MINIMIZATION (POS) Most rules are same except now instead of minterms we will have maxterms and instead of grouping ones, we will group zeros Eventually, we will multiply all the maxterms to get minimum cost POS Remember that now if xn is 0, we will take the uncomplemented form (different from SOP) 26  KARNAUGH MAP MINIMIZATION (DON’T CARE TERMS) Class work: Don’t care terms can be taken as 0 or 1 depending on SOP or POS minimization Thank You 28