Chapter 9 Input/Output Computer Hardware PDF

CHAPTER 9 INPUT / OUTPUT The Architecture of Computer Hardware, Systems Software & Networking: An Information Technology Approach 6th Edition, Irv Englander and Wilson Wong COPYRIGHT 2021 JOHN WILEY & SONS, INC OVERVIEW  Characteristics o...

CHAPTER 9 INPUT / OUTPUT The Architecture of Computer Hardware, Systems Software & Networking: An Information Technology Approach 6th Edition, Irv Englander and Wilson Wong COPYRIGHT 2021 JOHN WILEY & SONS, INC OVERVIEW  Characteristics of Typical I/O Devices  Programmed I/O  Interrupts  Direct Memory Address  I/O Controllers  Buses COPYRIGHT 2021 JOHN WILEY & SONS, INC 2 BASIC MODEL  Processing speed or program execution  Determined primarily by ability of I/O operations to stay ahead of processor Input Process Output COPYRIGHT 2021 JOHN WILEY & SONS, INC 3 I/O REQUIREMENTS 1. Means for addressing different peripheral devices 2. A way for peripheral devices to initiate communication with the CPU 3. An efficient means of transferring data directly between I/O and memory for large data transfers since programmed I/O is suitable only for slow devices and individual word transfers 4. Buses that interconnect high-speed I/O devices with the computer must support high data transfer rates 5. Capability of handling devices operating at varying speeds with varying delays 6. Means for handling devices with extremely different control requirements COPYRIGHT 2021 JOHN WILEY & SONS, INC 4 I/O INTERFACES  Are necessary because of  Different formats required by the devices  Incompatibilities in speed between the devices and the CPU that make synchronization difficult  Bursts of data vs. streaming data  Device control requirements that would tie up too much CPU time COPYRIGHT 2021 JOHN WILEY & SONS, INC 5 CHARACTERISTICS OF TYPICAL I/O DEVICES COPYRIGHT 2021 JOHN WILEY & SONS, INC 6 SIMPLE I/O CONFIGURATION COPYRIGHT 2021 JOHN WILEY & SONS, INC 7 MORE COMPLEX I/O MODULE COPYRIGHT 2021 JOHN WILEY & SONS, INC 8 ADVANCED I/O TECHNIQUES  Programmed I/O  CPU controlled I/O  Interrupt Driven I/O  External input controls  Direct Memory Access Controllers  Method for transferring data between main memory and a device that bypasses the CPU COPYRIGHT 2021 JOHN WILEY & SONS, INC 9 PROGRAMMED I/O  Simplest method for performing I/O  I/O data and address registers in CPU  One word transfer per I/O instruction  Address information for each I/O device  LMC I/O capability for 100 devices  Full instruction fetch/execute cycle  Primary use:  Keyboards  Communication with I/O controllers (see DMA) COPYRIGHT 2021 JOHN WILEY & SONS, INC 10 PROGRAMMED I/O EXAMPLE COPYRIGHT 2021 JOHN WILEY & SONS, INC 11 PROGRAMMED I/O EXAMPLE COPYRIGHT 2021 JOHN WILEY & SONS, INC 12 INTERRUPTS  Signal that causes the CPU to alter its normal flow of instruction execution  Frees CPU from waiting for events  Provides control for external I/O initiation  Examples  unexpected input  abnormal situation  illegal instructions  multitasking, multiprocessing COPYRIGHT 2021 JOHN WILEY & SONS, INC 13 INTERRUPT TERMINOLOGY  Interrupt lines (hardware)  One or more special control lines to the CPU  Interrupt request  Interrupt handlers  Program that services the interrupt  Also known as an interrupt routine or device driver  Context  Saved registers of a program before control is transferred to the interrupt handler  Allows program to resume exactly where it left off when control returns to interrupted program COPYRIGHT 2021 JOHN WILEY & SONS, INC 14 USE OF INTERRUPTS  Notify that an external event has occurred  Real-time or time-sensitive  Signal completion  Printer ready or buffer full  Allocate CPU time  Time sharing  Indicate abnormal event (CPU originates for notification and recovery)  Illegal operation, hardware error  Software interrupts COPYRIGHT 2021 JOHN WILEY & SONS, INC 15 THE CPU – THE INTERRUPT CYCLE ▪ Fetch / Execute cycle START ▪ Interrupt cycle Fetch Next Instruction Execute HALT Instruction Interrupts Disabled Process Check for Interrupt Interrupt COPYRIGHT 2021 JOHN WILEY & SONS, INC 16 SERVICING THE INTERRUPT 1. Lower priority interrupts are held until higher priority interrupts are complete 2. Suspend program in progress 3. Save context, including last instruction executed and data values in registers, in the PCB or the stack area in memory 4. Branch to interrupt handler program COPYRIGHT 2021 JOHN WILEY & SONS, INC 17 SERVICING AN INTERRUPT COPYRIGHT 2021 JOHN WILEY & SONS, INC 18 PRINT HANDLER INTERRUPT COPYRIGHT 2021 JOHN WILEY & SONS, INC 19 USING AN INTERRUPT FOR TIME SHARING COPYRIGHT 2021 JOHN WILEY & SONS, INC 20 INTERRUPT PROCESSING METHODS  Vectored interrupt  Address of interrupting device is included in the interrupt  Requires additional hardware to implement  Polling  Identifies interrupting device by polling each device  General interrupt is shared by all devices COPYRIGHT 2021 JOHN WILEY & SONS, INC 21 VECTORED INTERRUPTS COPYRIGHT 2021 JOHN WILEY & SONS, INC 22 POLLED INTERRUPTS COPYRIGHT 2021 JOHN WILEY & SONS, INC 23 MULTIPLE INTERRUPTS EXAMPLE COPYRIGHT 2021 JOHN WILEY & SONS, INC 24 DIRECT MEMORY ACCESS  Transferring large blocks of data  Direct transfer to and from memory  CPU not actively involved in transfer itself  Required conditions for DMA  The I/O interface and memory must be connected  The I/O controller must be capable of reading and writing to memory  Conflicts between the CPU and the I/O controller must be avoided  Interrupt required for completion COPYRIGHT 2021 JOHN WILEY & SONS, INC 25 DMA INSTRUCTIONS  Application program requests I/O service from operating system  Privileged programmed I/O instructions  To initiate DMA, programmed I/O is used to send the following information: 1. Location of data on I/O device 2. Starting location in memory 3. Size of the block 4. Direction of transfer: read or write  Interrupt to CPU upon completion of DMA COPYRIGHT 2021 JOHN WILEY & SONS, INC 26 DMA INITIATION AND CONTROL COPYRIGHT 2021 JOHN WILEY & SONS, INC 27 I/O CONTROLLER FUNCTIONS  Recognizes messages from device(s) addressed to it and accepts commands from the CPU  Provides a buffer where the data from memory can be held until it can be transferred to the device  Provides the necessary registers and controls to perform a direct memory transfer  Physically controls the device  Copies data from its buffer to the device/from the CPU to its buffer  Communicates with CPU COPYRIGHT 2021 JOHN WILEY & SONS, INC 28 I/O CONTROLLER INTERFACES COPYRIGHT 2021 JOHN WILEY & SONS, INC 29 ADVANTAGES OF SEPARATE I/O CONTROLLERS  Controller can be designed to provide specialized control for a device  Control of several different I/O devices can occur simultaneously  The CPU is freed to perform other tasks while much slower I/O operations are taking place.  Processor-based controllers can offload time-consuming CPU-intensive work. Examples:  High-end graphics display controller  Mainframe channel subsystems (see Chapter 10) COPYRIGHT 2021 JOHN WILEY & SONS, INC 30 BUS The physical connection that makes it possible to transfer data from one location in the computer system to another Group of electrical or optical conductors for carrying signals from one location to another  Wires or conductors printed on a circuit board  Line: each conductor in the bus 4 kinds of signals 1. Data 2. Addressing 3. Control signals 4. Power (sometimes) COPYRIGHT 2021 JOHN WILEY & SONS, INC 31 BUS CHARACTERISTICS  Number of separate wires or conductors  Data width in bits carried simultaneously  Addressing capacity  Lines on the bus are for a single type of signal or shared  Throughput – data transfer rate in bits per second  Distance between two endpoints  Number and type of attachments supported  Type of control required  Defined purpose  Features and capabilities COPYRIGHT 2021 JOHN WILEY & SONS, INC 32 BUS CATEGORIZATIONS  Parallel vs. serial buses  Direction of transmission  Simplex – unidirectional  Half duplex – bidirectional, one direction at a time  Full duplex – bidirectional simultaneously  Method of interconnection  Point-to-point – single source to single destination  Cables – point-to-point buses that connect to an external device  Multipoint bus – also broadcast bus or multidrop bus  Connect multiple points to one another COPYRIGHT 2021 JOHN WILEY & SONS, INC 33 PARALLEL VS. SERIAL BUSES  Parallel  High throughput because all bits of a word are transmitted simultaneously  Expensive and require a lot of space  Subject to radio-generated electrical interference, which limits their speed and length  Generally used for short distances such as CPU buses and on computer motherboards  Serial  1 bit transmitted at a time  Single data line pair and a few control lines  For many applications, throughput is higher than for parallel because of the lack of electrical interference COPYRIGHT 2021 JOHN WILEY & SONS, INC 34 POINT-TO-POINT VS. MULTIPOINT Plug-in device Broadcast bus Example: Ethernet Shared among multiple devices COPYRIGHT 2021 JOHN WILEY & SONS, INC 35 COPYRIGHT 2021 JOHN WILEY & SONS All rights reserved. Reproduction or translation of this work beyond that permitted in section 117 of the 1976 United States Copyright Act without express permission of the copyright owner is unlawful. Request for further information should be addressed to the Permissions Department, John Wiley & Sons, Inc. The purchaser may make back-up copies for his/her own use only and not for distribution or resale. The Publisher assumes no responsibility for errors, omissions, or damages caused by the use of these programs or from the use of the information contained herein. COPYRIGHT 2021 JOHN WILEY & SONS, INC 36