Computer Hardware Chapter 9: Input/Output

Overview of Input/Output (I/O)

• I/O operations are crucial in computer systems, as they determine the processing speed or program execution
• The basic model of I/O involves input, processing, and output

I/O Requirements

• Means for addressing different peripheral devices
• A way for peripheral devices to initiate communication with the CPU
• Efficient means of transferring data directly between I/O and memory for large data transfers
• Buses that interconnect high-speed I/O devices with the computer must support high data transfer rates
• Capability of handling devices operating at varying speeds with varying delays
• Means for handling devices with extremely different control requirements

I/O Interfaces

• Necessary due to different formats required by devices, incompatibilities in speed, and bursts of data vs. streaming data
• Device control requirements that would tie up too much CPU time

Characteristics of Typical I/O Devices

• (No specific details provided in the text)

I/O Techniques

• Programmed I/O: CPU controlled I/O, where the CPU performs I/O operations using I/O instructions
• Interrupt Driven I/O: external input controls, where the CPU is interrupted by an I/O device to perform an I/O operation
• Direct Memory Access (DMA) Controllers: a method for transferring data between main memory and a device that bypasses the CPU

Programmed I/O

• Simplest method for performing I/O
• I/O data and address registers are in the CPU
• One word transfer per I/O instruction
• Address information is required for each I/O device
• Primary use: keyboards, communication with I/O controllers (see DMA)

Interrupts

• Signals that cause the CPU to alter its normal flow of instruction execution
• Frees the CPU from waiting for events
• Provides control for external I/O initiation
• Examples: unexpected input, abnormal situation, illegal instructions, multitasking, and multiprocessing

Interrupt Terminology

• Interrupt lines: special control lines to the CPU
• Interrupt request: a signal sent to the CPU to request an interrupt
• Interrupt handlers: programs that service interrupts, also known as interrupt routines or device drivers
• Context: saved registers of a program before control is transferred to the interrupt handler

Use of Interrupts

• Notify that an external event has occurred (real-time or time-sensitive)
• Signal completion (e.g., printer ready or buffer full)
• Allocate CPU time (time sharing)
• Indicate abnormal events (CPU originates for notification and recovery)
• Software interrupts

Servicing an Interrupt

• Lower priority interrupts are held until higher priority interrupts are complete
• Suspend program in progress
• Save context, including last instruction executed and data values in registers, in the PCB or the stack area in memory
• Branch to interrupt handler program

Direct Memory Access (DMA)

• Transferring large blocks of data
• Direct transfer to and from memory
• CPU not actively involved in transfer itself
• Required conditions for DMA: I/O interface and memory must be connected, I/O controller must be capable of reading and writing to memory, and conflicts between the CPU and I/O controller must be avoided

I/O Controllers

• Recognize messages from devices and accept commands from the CPU
• Provide a buffer for data transfer
• Provide necessary registers and controls for direct memory transfer
• Physically control the device
• Communicate with the CPU

Bus

• Physical connection for transferring data between locations in the computer system
• Group of electrical or optical conductors for carrying signals
• 4 kinds of signals: data, addressing, control signals, and power (sometimes)

Bus Characteristics

• Number of separate wires or conductors
• Data width in bits carried simultaneously
• Addressing capacity
• Lines on the bus are for a single type of signal or shared
• Throughput – data transfer rate in bits per second
• Distance between two endpoints
• Number and type of attachments supported
• Type of control required
• Defined purpose
• Features and capabilities