Document Details

Uploaded by Deleted User

Iowa State University

Mohamed Selim

Tags

digital logic computer engineering electronics lecture notes

Summary

These lecture notes cover digital logic concepts, including topics like binary numbers, hexadecimal numbers, multiplexers, and flip-flops. The notes contain diagrams and tables.

Full Transcript

CprE 281: Digital Logic Instructor: Mohamed Selim CprE 281: Digital Logic Iowa State University, Ames, IA Copyright © Alexander Stoytchev Announcements HW 07 is due March 19th @ 11:59 PM Fr...

CprE 281: Digital Logic Instructor: Mohamed Selim CprE 281: Digital Logic Iowa State University, Ames, IA Copyright © Alexander Stoytchev Announcements HW 07 is due March 19th @ 11:59 PM Friday (after Spring Break – 3/22) Quiz 03 Friday After (3/29) Midterm Exam 2  Where: In-class  What: Chapters 1, 2, 3, 4 and 5.1-5.8 2 Announcements Binary Numbers and Hexadecimal Numbers  1’s complement and 2’s complement representation  Addition and subtraction of binary numbers  Circuits for adders and fast adders Single and Double precision IEEE floating point formats  Converting a real number to the IEEE format  Converting a floating point number to decimal Multiplexers (circuits and function)  Synthesis of logic functions using multiplexers  Shannon’s Expansion Theorem 3 Announcements Decoders (circuits and function)  Demultiplexers  Encoders (binary and priority)  Code Converters Synthesis of logic circuits using adders, multiplexers, encoders, decoders, and basic logic gates  given constraints on the available building blocks that you can use Latches (circuits, behavior, timing diagrams) Flip-Flops (circuits, behavior, timing diagrams) Registers and Register Files 4 Quick Review A simple memory element with NOT Gates x x x A simple memory element with NOR Gates Set Reset Basic Latch Basic Latch (with NOR Gates) (with NAND Gates) S R Qa Qb S R Qa Qb 0 0 0/1 1/0 (no change) Latch 0 0 0/1 1/0 (no change) Latch 0 1 0 1 Reset 0 1 0 1 Reset 1 0 1 0 Set 1 0 1 0 Set 1 1 0 0 Undesirable 1 1 1 1 Undesirable 8 Gated SR Latch Motivation The basic latch changes its state when the input signals change It is hard to control when these input signals will change and thus it is hard to know when the latch may change its state. We want to have something like an Enable input. In this case it is called the “Clock” input because it is desirable for the state changes to be synchronized. Circuit Diagram for the Gated SR Latch This is the “gate” of the gated latch Circuit Diagram and Characteristic Table for the Gated SR Latch [ Figure 5.5a-b from the textbook ] Circuit Diagram and Graphical Symbol for the Gated SR Latch [ Figure 5.5a,c from the textbook ] Timing Diagram for the Gated SR Latch [ Figure 5.5c from the textbook ] Timing Diagram for the Gated SR Latch [ Figure 5.5c from the textbook ] Gated SR latch with NAND gates S Q Clk Q R [ Figure 5.6 from the textbook ] Gated SR latch with NAND gates S Q Clk Q R In this case the “gate” is constructed using NAND gates! Not AND gates. Gated SR latch with NAND gates S S 1 Q Clk = 1 1 Q R R Finally, notice that when Clk=1 this turns into the basic latch with NAND gates, i.e., the SR Latch. Gated SR latch with NOR gates (undesirable) Gated SR latch with NAND gates S Q Clk Q (undesirable) R Characteristic tables are the same Gated D Latch Motivation Dealing with two inputs (S and R) could be messy. For example, we may have to reset the latch before some operations in order to store a specific value but the reset may not be necessary depending on the current state of the latch. Why not just have one input and call it D. The D latch can be constructed using a simple modification of the SR latch. Circuit Diagram for the Gated D Latch [ Figure 5.7a from the textbook ] Circuit Diagram for the Gated D Latch This is the only new thing here. [ Figure 5.7a from the textbook ] Circuit Diagram for the Gated D Latch 0 0 0 [ Figure 5.7a from the textbook ] Circuit Diagram for the Gated D Latch 1 0 0 0 1 S R Qa Qb 0 0 1 1 0 1 1 0 1 0 0 1 1 1 0/1 1/0 (no change) [ Figure 5.7a from the textbook ] Circuit Diagram for the Gated D Latch 1 1 1 [ Figure 5.7a from the textbook ] Circuit Diagram for the Gated D Latch 0 0 1 1 1 1 [ Figure 5.7a from the textbook ] Circuit Diagram for the Gated D Latch 0 0 1 1 1 1 0 1 S R Qa Qb 0 0 1 1 0 1 1 0 1 0 0 1 1 1 0/1 1/0 (no change) [ Figure 5.7a from the textbook ] Circuit Diagram for the Gated D Latch 0 0 1 0 1 1 1 0 1 1 S R Qa Qb 0 0 1 1 0 1 1 0 1 0 0 1 1 1 0/1 1/0 (no change) [ Figure 5.7a from the textbook ] Circuit Diagram for the Gated D Latch 1 1 0 1 1 1 1 1 0 0 S R Qa Qb 0 0 1 1 0 1 1 0 1 0 0 1 1 1 0/1 1/0 (no change) [ Figure 5.7a from the textbook ] Circuit Diagram and Characteristic Table for the Gated D Latch Note that it is now impossible to have S=R=1. [ Figure 5.7a,b from the textbook ] Circuit Diagram and Characteristic Table for the Gated D Latch When Clk=1 the output follows the D input. When Clk=0 the output cannot be changed. [ Figure 5.7a,b from the textbook ] Circuit Diagram and Graphical Symbol for the Gated D Latch [ Figure 5.7a,c from the textbook ] Timing Diagram for the Gated D Latch [ Figure 5.7d from the textbook ] Timing Diagram for the Gated D Latch [ Figure 5.7d from the textbook ] Setup and hold times t su th Clk D Q Setup time (tsu) – the minimum time that the D signal must be stable prior to the the negative edge of the Clock signal. Hold time (th) – the minimum time that the D signal must remain stable after the the negative edge of the Clock signal. [ Figure 5.8 from the textbook ] Master-Slave D Flip-Flop Constructing a Master-Slave D Flip-Flop From Two D Latches Master Slave Constructing a Master-Slave D Flip-Flop From Two D Latches Master Slave Constructing a Master-Slave D Flip-Flop From Two D Latches Master Slave Constructing a Master-Slave D Flip-Flop From Two D Latches [ Figure 5.9a from the textbook ] Constructing a Master-Slave D Flip-Flop From one D Latch and one Gated SR Latch (This version uses one less NOT gate) Master Slave Constructing a Master-Slave D Flip-Flop From Two D Latches Master Slave Constructing a Master-Slave D Flip-Flop From one D Latch and one Gated SR Latch (This version uses one less NOT gate) Master Slave Edge-Triggered D Flip-Flops Motivation In some cases we need to use a memory storage device that can change its state no more than once during each clock cycle. Master-Slave D Flip-Flop Master Slave Qm Qs D D Q D Q Q Clock Clk Q Clk Q Q (a) Circuit [ Figure 5.9a from the textbook ] Timing Diagram for the Master-Slave D Flip-Flop Master Slave Qm Qs D D Q D Q Q Clock Clk Q Clk Q Q Clock D Qm Q = Qs [ Figure 5.9a,b from the textbook ] Timing Diagram for the Master-Slave D Flip-Flop Master Slave Qm Qs D D Q D Q Q Clock Clk Q Clk Q Q Clock D Qm Q = Qs [ Figure 5.9a,b from the textbook ] Graphical Symbol for the Master-Slave D Flip-Flop D Q Q [ Figure 5.9c from the textbook ] Graphical Symbol for the Master-Slave D Flip-Flop D Q Q The > means that this is edge-triggered The small circle means that is is the negative edge [ Figure 5.9c from the textbook ] Negative-Edge-Triggered Master-Slave D Flip-Flop Master Slave Qm Qs D D Q D Q Q Clock Clk Q Clk Q Q Positive-Edge-Triggered Master-Slave D Flip-Flop Master Slave Qm Qs D D Q D Q Q Clock Clk Q Clk Q Q Negative-Edge-Triggered Master-Slave D Flip-Flop D Q Q Positive-Edge-Triggered Master-Slave D Flip-Flop D Q Q D Flip-Flop: A Double Door Analogy Positive-Edge-Triggered Master-Slave D Flip-Flop Master Slave Qm Qs D D Q D Q Q Clock Clk Q Clk Q Q Clock Positive-Edge-Triggered Master-Slave D Flip-Flop Master Slave Qm Qs D D Q D Q Q Clock Clk Q Clk Q Q Clock Positive-Edge-Triggered Master-Slave D Flip-Flop Master Slave Qm Qs D D Q D Q Q Clock Clk Q Clk Q Q Clock Positive-Edge-Triggered Master-Slave D Flip-Flop Master Slave Qm Qs D D Q D Q Q Clock Clk Q Clk Q Q Clock Other Types of Edge-Triggered D Flip-Flops D D Q Qa Comparison of level-sensitive and Clock Clk Q Qa edge-triggered D storage elements D Q Qb Q Qb D Q Qc Q Qc Clock D Qa Qb Qc D D Q Qa Comparison of level-sensitive and Clock Clk Q Qa edge-triggered D storage elements D Q Qb Q Qb Level-sensitive (the output mirrors the D input when Clk=1) D Q Qc Q Qc Clock D Qa Qb Qc D D Q Qa Comparison of level-sensitive and Clock Clk Q Qa edge-triggered D storage elements D Q Qb Q Qb Positive-edge-triggered D Q Qc Q Qc Clock D Qa Qb Qc D D Q Qa Comparison of level-sensitive and Clock Clk Q Qa edge-triggered D storage elements D Q Qb Q Qb Negative-edge-triggered D Q Qc Q Qc Clock D Qa Qb Qc A positive-edge-triggered D flip-flop 1 P3 P1 2 5 Q Clock P2 6 Q 3 D Q Clock Q 4 P4 D (a) Circuit (b) Graphical symbol [ Figure 5.11 from the textbook ] A positive-edge-triggered D flip-flop This circuit behaves like a positive-edge-triggered D flip-flop, but it uses only 6 NAND gates. 1 P3 Thus, it can be implemented with fewer transistors than the master-slave D flip-flop. P1 2 5 Q Clock P2 6 Q 3 D Q Clock Q 4 P4 D (a) Circuit (b) Graphical symbol [ Figure 5.11 from the textbook ] Questions?

Use Quizgecko on...
Browser
Browser