Sequential Logic Circuit PDF

Combinational vs. Sequential Logic/Field ProgrammableGate Arrays (FPGAS) Sequential Logic  Sequential Logic Circuits ❑ The sequential circuit is a special type of circuit that has a series of inputs and outputs. ❑ The outputs of the sequential circuits depend on both the combination of pres...

Combinational vs. Sequential Logic/Field ProgrammableGate Arrays (FPGAS) Sequential Logic  Sequential Logic Circuits ❑ The sequential circuit is a special type of circuit that has a series of inputs and outputs. ❑ The outputs of the sequential circuits depend on both the combination of present inputs and previous outputs. ❑ The previous output is treated as the present state. ❑ Use flip-flops as memory elements and in which their output is dependent on the input state. Sequential Logic Circuits  Sequential Logic Circuits ❑ Stores and processes digital information in a sequential manner as it has an additional element called memory which enables it to consider not only the present but also the past inputs or states. ❑ This memory element plays a vital role as it enables the processing of streams of data. ❑ Able to take into account their previous input state as well as those actually present, a sort of “before” and “after” effect is involved with sequential circuits.  Sequential Logic Circuits ❑ Generally termed as two state or Bistable devices which can have their output or output sets in one of two basic states: 1. a logic level “1” 2. a logic level “0” and will remain “latched” (hence the name latch) indefinitely in this current state or condition until some other input trigger pulse or signal is applied which will cause the bistable to change its state once again.  Types of Sequential Circuits Synchronous Sequential Circuit ❑ Synchronize with either positive edge or negative edge of the clock signal, that means, the outputs of synchronous sequential circuits change or affect at the same time. ❑ These circuits use clock signal and level input (or pulsed with restrictions on pulse width and circuit propagation).  Types of Sequential Circuits Synchronous Sequential Circuit ❑ Since they wait for the next clock pulse to arrive to perform the next operation, so these circuits are a bit slower compared to asynchronous. ❑ Level output changes state at the start of an input pulse and remains in that until the next input or clock pulse. ❑ The synchronous sequential circuit can be locked or unlocked (or pulsed).  Types of Sequential Circuits Synchronous Sequential Circuit  Types of Sequential Circuits Asynchronous Sequential Circuit ❑ Do not synchronize with positive edge or negative edge of the clock signal, that means, the outputs of asynchronous sequential circuits do not change or affect at the same time and change their state immediately when there is a change in the input signal. ❑ These circuits are faster and independent of the internal clock pulses. But these circuits have uncertainty in the outputs and are difficult to design.  Types of Sequential Circuits Asynchronous Sequential Circuit Classification of Sequential Logic ❑ Bistable latches and flip-flops are the basic building blocks of sequential logic circuits. ❑ Sequential logic circuits can be constructed to produce either simple edge-triggered flip- flops or more complex sequential circuits such as storage registers, shift registers, memory devices or counters. Classification of Sequential Logic Classification of Sequential Logic ❑ Either way sequential logic circuits can be divided into the following three main categories: 1. Event Driven – asynchronous circuits that change state immediately when enabled. 2. Clock Driven – synchronous circuits that are synchronized to a specific clock signal. 3. Pulse Driven – which is a combination of the two that responds to triggering pulses. Applications of Sequential Circuit ❑ Computer Processors: Most of the modern CPUs contain sequential circuits to fetch instructions, decode data and execute processes. The reason of sequential circuits within CPU is to maintain the flow of work or operations of CPU in sequential manner(one after another to avoid overlapping). ❑ Memory Systems: RAM and ROM are the backbone of memory of computer. And both of these contains sequential circuits for better utilization during storing and retrieving data. ❑ Communication Systems: All communication system consists of sequential circuit for data encoding, decoding and synchronization and ensures secure data transmission and better quality error detection. Sequential Logic Circuits Basics of Flip Flops  Flip Flop ❑ A circuit that has two stable states is treated as a flip flop. ❑ These stable states are used to store binary data that can be changed by applying varying inputs. ❑ The flip flops are the fundamental building blocks of the digital system.  Flip Flop ❑ Flip flops and latches are examples of data storage elements. ❑ In the sequential logical circuit, the flip flop is the basic storage element. ❑ The latches and flip flops are the basic storage elements but different in working. Sequential Logic Circuits Types of Flip Flops  SR Flip Flop ❑ The most common flip flop used in the digital system. ❑ The most basic sequential logic circuit possible. ❑ Also known as a SR Latch ❑ This simple flip-flop is basically a one-bit memory bistable device that has two inputs: 1. one which will “SET” the device (meaning the output = “1”), and is labelled S 2. one which will “RESET” the device (meaning the output = “0”), labelled R.  SR Flip Flop ❑ Then the SR description stands for “Set-Reset”. The reset input resets the flip-flop back to its original state with an output Q that will be either at a logic level “1” or logic “0” depending upon this set/reset condition.  SR Flip Flop The Set State ❑ If the input R is at logic level “0” (R = 0) and input S is at logic level “1” (S = 1), the NAND gate Y has at least one of its inputs at logic “0” therefore, its output Q’ must be at a logic level “1” (NAND Gate principles). ❑ Output Q’ is also fed back to input “A” and so both inputs to NAND gate X are at logic level “1”, and therefore its output Q must be at logic level “0”.  SR Flip Flop The Set State ❑ Again NAND gate principals. If the reset input R changes state, and goes HIGH to logic “1” with S remaining HIGH also at logic level “1”, NAND gate Y inputs are now R = “1” and B = “0”. ❑ Since one of its inputs is still at logic level “0” the output at Q’ still remains HIGH at logic level “1” and there is no change of state. ❑ Therefore, the flip-flop circuit is said to be “Latched” or “Set” with Q’ = “1” and Q = “0”.  SR Flip Flop Reset State ❑ In this second stable state, Q’ is at logic level “0”, (not Q = “0”) its inverse output at Q is at logic level “1”, (Q = “1”), and is given by R = “1” and S = “0”. ❑ As gate X has one of its inputs at logic “0” its output Q must equal logic level “1” (again NAND gate principles). Output Q is fed back to input “B”, so both inputs to NAND gate Y are at logic “1”, therefore, Q’ = “0”.  SR Flip Flop Reset State ❑ If the set input, S now changes state to logic “1” with input R remaining at logic “1”, output Q’ still remains LOW at logic level “0” and there is no change of state. Therefore, the flip- flop circuits “Reset” state has also been latched.  SR Flip Flop Truth Table for this Set-Reset Function  SR Flip Flop Positive NAND Gate SR Flip-flop ▪ To change the basic flip-flop circuit to one that changes state by the application of positive going input signals with the addition of two extra NAND gates connected as inverters to the S and R inputs.  SR Flip Flop The NOR Gate SR Flip-flop ▪ It is also possible to construct simple one-bit SR Flip-flops using two cross-coupled NOR gates connected in the same configuration. ▪ The circuit will work in a similar way to the NAND gate circuit above, except that the inputs are active HIGH and the invalid condition exists when both its inputs are at logic level “1”.  SR Flip Flop Gated SR Flip-flop ▪ Gated Bistable SR Flip-flop operates as a standard bistable latch but the outputs are only activated when a logic “1” is applied to its EN input and deactivated by a logic “0”.  JK Flip Flop ❑ The JK Flip-flop is similar to the SR Flip-flop but there is no change in state when the J and K inputs are both LOW. ❑ Unlike the JK Flip-flop, the basic S-R NAND flip-flop circuit has many advantages and uses in sequential logic circuits but it suffers from two basic switching problems. 1. the Set = 0 and Reset = 0 condition (S = R = 0) must always be avoided 2. if Set or Reset change state while the enable (EN) input is high the correct latching action may not occur ❑ Then to overcome these two fundamental design problems with the SR flip-flop design, the JK flip Flop was developed.  JK Flip Flop ❑ JK flip Flop is the most widely used of all the flip-flop designs and is considered to be a universal flip-flop circuit. ❑ The two inputs labelled “J” and “K” are not shortened abbreviated letters of other words, such as “S” for Set and “R” for Reset, but are themselves autonomous letters chosen by its inventor Jack Kilby to distinguish the flip-flop design from other types.  JK Flip Flop ❑ The sequential operation of the JK flip flop is exactly the same as for the previous SR flip-flop with the same “Set” and “Reset” inputs. ❑ The difference this time is that the “JK flip flop” has no invalid or forbidden input states of the SR Latch even when S and R are both at logic “1”. ❑ The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that prevents the illegal or invalid output condition that can occur when both inputs S and R are equal to logic level “1”.  JK Flip Flop The Basic JK Flip-flop ▪ Both the S and the R inputs of the previous SR bistable have now been replaced by two inputs called the J and K inputs, respectively after its inventor Jack Kilby. Then this equates to: J = S and K = R.  JK Flip Flop The Basic JK Flip-flop ▪ The two 2-input AND gates of the gated SR bistable have now been replaced by two 3-input NAND gates with the third input of each gate connected to the outputs at Q and Q’. This cross coupling of the SR flip- flop allows the previously invalid condition of S = “1” and R = “1” state to be used to produce a “toggle action” as the two inputs are now interlocked.  JK Flip Flop The Basic JK Flip-flop ▪ If the circuit is now “SET” the J input is inhibited by the “0” status of Q through the lower NAND gate. If the circuit is “RESET” the K input is inhibited by the “0” status of Q through the upper NAND gate. As Q and Q’ are always different we can use them to control the input.  JK Flip Flop The Truth Table for the JK Function JK flip-flop is basically an SR flip flop with feedback which enables only one of its two input terminals, either SET or RESET to be active at any one time under normal switching thereby eliminating the invalid condition seen previously in the SR flip flop circuit.  JK Flip Flop Other Popular JK Flip-flop ICs  JK Flip Flop ❑ Basically two gated SR flip-flops connected together in a series configuration with the slave having an inverted clock pulse. The outputs from Q and Q’ from the “Slave” flip- flop are fed back to the inputs of the “Master” with the outputs of the “Master” flip flop being connected to the two inputs of the “Slave” flip flop.  JK Flip Flop The Master-Slave Configuration ▪ The input signals J and K are connected to the gated “master” SR flip flop which “locks” the input condition while the clock (Clk) input is “HIGH” at logic level “1”. As the clock input of the “slave” flip flop is the inverse (complement) of the “master” clock input, the “slave” SR flip flop does not toggle. The outputs from the “master” flip flop are only “seen” by the gated “slave” flip flop when the clock input goes “LOW” to logic level “0”.  JK Flip Flop The Master-Slave Configuration ▪ When the clock is “LOW”, the outputs from the “master” flip flop are latched and any additional changes to its inputs are ignored. The gated “slave” flip flop now responds to the state of its inputs passed over by the “master” section.  JK Flip Flop The Master-Slave Configuration ▪ Then on the “Low-to-High” transition of the clock pulse the inputs of the “master” flip flop are fed through to the gated inputs of the “slave” flip flop and on the “High-to-Low” transition the same inputs are reflected on the output of the “slave” making this type of flip flop edge or pulse- triggered.  JK Flip Flop The Master-Slave Configuration ▪ Then, the circuit accepts input data when the clock signal is “HIGH”, and passes the data to the output on the falling-edge of the clock signal. In other words, the Master-Slave JK Flip flop is a “Synchronous” device as it only passes data with the timing of the clock signal.  T Flip Flop ❑ A variation of the clocked JK flip-flop. ❑ The toggle or T-type flip-flop gets its name from the fact that its two outputs Q and Q’ invert from their previous state as it toggles back and forth every time it is triggered (T = 1). ❑ That is, the Q and Q’ outputs change to a “1” if it was “0”, and “0” if it was previously a “1” but only when the “T” input changes HIGH, otherwise they do not change, and its this asynchronous toggling action we are interested in here.  T Flip Flop ❑ Suppose that initially CLK and input T are both LOW (CLK = T = 0), and that output Q is HIGH (Q = 1). At the rising edge or falling edge of a CLK pulse, the logic “0” condition present at T prevents the output at Q from changing state. Thus the output remains unchanged when T = 0.  T Flip Flop ❑ Suppose that input T is HIGH (T = 1) and CLK is LOW (CLK = 0). At the rising edge (assuming positive transistion) of a CLK pulse at time t1, the output at Q changes state and becomes LOW, making Q’ HIGH. The negative transistion of the clock pulse from HIGH to LOW at time t2 has no effect on the output at Q as the flip-flop is reset into one stable state.  T Flip Flop ❑ At the next rising edge of the clock signal at time t3, the logic “1” at T passes to Q, changing its state making output Q HIGH again. The negative transistion of the CLK pulse at time t4 from HIGH to LOW once again has no effect on the output. Thus the Q output of the flip- flop “toggles” at each positive going edge (for this example) of the CLK pulse.  T Flip Flop Characteristics Table for the Toggle Function Then we can define the switching action of the toggle flip-flop in Boolean form as being: Q+1 = T.Q’ + T’.Q Where: Q represents the present steady state of the flip-flop and Q+1 is the next switching state.  T Flip Flop Characteristics Table for the Toggle Flip-flop Here, “T” becomes one of the inputs of a 2-input exclusive- OR gate while output Q is fed back to become the other. Thus T and Q are both inputs to the Ex-OR gate to produce the required Boolean expression to drive the D input. If T = 0, the output of the exclusive-OR gate which is Q ⊕ T will also be LOW (0), so the D-type flip-flop stays fixed in one stable state.  T Flip Flop Characteristics Table for the Toggle Flip-flop However, when T = 1, the exclusive-OR produces a change of state at D every time the D-type flip-flop is clocked as the output Q which is fed back to the gate toggles between HIGH and LOW on every clock pulse, making it very useful as a bistable element when a single data bit is to be stored.  T Flip Flop Characteristics Table for the Toggle Flip-flop As this configuration can only hold its unchanged state, or the complement its state, there is no way to establish an initial output state either HIGH or LOW when power is first applied without adding additional Preset (Pre) or Clear (Clr) inputs or external circuitry to initialise or set the output Q to a known state.  T Flip Flop Characteristics Table for the Toggle Flip-flop Also, since the output at Q changes state on the rising edge of each and every clock pulse, the time period of the output at Q will be equal to half the frequency of the clock pulse. In other words, the T- type flip-flop’s toggling action can create a divide-by-two circuit who’s output will have a 1:1 (50%) Mark-to-Space ratio, since the LOW period and the HIGH period of the Q output are of equal length.  D Flip Flop ❑ The D-type flip-flop is a modified Set-Reset flip-flop with the addition of an inverter to prevent the S and R inputs from being at the same logic level.  D Flip Flop ❑ The D-type Flip-flop overcomes one of the main disadvantages of the basic SR NAND Gate Bistable circuit in that the indeterminate input condition of SET = “0” and RESET = “0” is forbidden. ❑ This state will force both outputs to be at logic “1”, over-riding the feedback latching action and whichever input goes to logic level “1” first will lose control, while the other input still at logic “0” controls the resulting state of the latch.  D Flip Flop ❑ But in order to prevent this from happening an inverter can be connected between the “SET” and the “RESET” inputs to produce another type of flip flop circuit known as a Data Latch, Delay flip flop, D-type Bistable, D-type Flip Flop or just simply a D Flip Flop as it is more generally called. ❑ The D Flip Flop is by far the most important of all the clocked flip-flops.  D Flip Flop D-type Flip-Flop Circuit ▪ A simple SR flip-flop requires two inputs, one to “SET” the output and one to “RESET” the output. By connecting an inverter (NOT gate) to the SR flip-flop we can “SET” and “RESET” the flip-flop using just one input as now the two input signals are complements of each other. This complement avoids the ambiguity inherent in the SR latch when both inputs are LOW, since that state is no longer possible.  D Flip Flop D-type Flip-Flop Circuit ▪ This single input is called the “DATA” input. If this data input is held HIGH the flip flop would be “SET” and when it is LOW the flip flop would change and become “RESET”. However, this would be rather pointless since the output of the flip flop would always change on every pulse applied to this data input.  D Flip Flop D-type Flip-Flop Circuit ▪ To avoid this an additional input called the “CLOCK” or “ENABLE” input is used to isolate the data input from the flip flop’s latching circuitry after the desired data has been stored. The effect is that D input condition is only copied to the output Q when the clock input is active. This then forms the basis of another sequential device called a D Flip Flop.  D Flip Flop D-type Flip-Flop Circuit ▪ The “D flip flop” will store and output whatever logic level is applied to its data terminal so long as the clock input is HIGH. Once the clock input goes LOW the “set” and “reset” inputs of the flip-flop are both held at logic level “1” so it will not change state and store whatever data was present on its output before the clock transition occurred. In other words the output is “latched” at either logic “0” or logic “1”.  D Flip Flop Truth Table for the D-type Flip Flop