CprP:QUZ:DTL:Chptr:Chpt:QTQZ:Chptr:Chpt:QUZ

A method of representing negative numbers in binary by inverting all the bits of the positive version.

A method of representing negative numbers in binary by adding 1 to the 1's complement of the positive version.

Adding two binary numbers bit-by-bit, carrying over any '1' results to the next column.

Subtracting two binary numbers by converting them to 2's Complement and performing binary addition.

A standard format for representing real numbers in computers using a sign bit, exponent, and mantissa.

A combinational circuit that selects one of multiple input lines based on a control signal.

A combinational circuit that converts a binary code into a unique output line corresponding to the input.

A basic memory element that stores a single bit of data, but its state depends on the level of the input signals.

A type of latch that uses a gate signal to control data transfer. When the gate is active, the latch updates its output to match the input. When the gate is inactive, the latch holds its current output value.

An input signal that enables or disables data transfer in a gated latch. It determines whether the latch is active or inactive.

The 'Set' input of a D latch, which sets the latch's output to a '1' when asserted.

The 'Reset' input of a D latch, which resets the latch's output to a '0' when asserted.

The primary output of a D latch, representing the stored data value.

The complementary output of a D latch, representing the inverse of the stored data value.

The data input of a D latch, which provides the data to be stored when the gate is active.

The state of a D latch when the gate signal is enabled, allowing data transfer. The latch updates its output to match the D input.

The minimum amount of time that the data input (D) must be stable before the clock edge arrives. This ensures the data is properly captured.

The minimum amount of time that the data input (D) must remain stable after the clock edge occurs. This maintains data integrity.

A type of flip-flop constructed using two D latches. The first latch (master) receives the data input when the clock is high, while the second latch (slave) transfers the data to the output when the clock is low.

A flip-flop that changes its state only at the edge of the clock signal. Either the rising edge (positive) or the falling edge (negative) is used.

Edge-triggered D flip-flops ensure data changes only once per clock cycle, preventing race conditions and ensuring reliable operation.

While both achieve the same goal of single data change per clock, the master-slave design uses two latches with a clock signal, while the edge-triggered design only needs a single latch with a sensitive edge.

The gated SR latch is enabled when the Clk input is high (logical 1). This allows the latch to change its state based on the values of S and R.

The gated SR latch is disabled when the Clk input is low (logical 0). This prevents the latch from changing its state, even if S and R are changing.

A gated SR latch can be constructed using two NAND gates, one for the output Q and another for the inverting output Q'. The clock signal is applied to the input of both NAND gates.

Although possible, a Gated SR latch with NOR gates leads to an undesirable characteristic that makes it less practical.

The Gated D latch simplifies latch control as it uses a single data input (D) instead of two (S and R). This makes it easier to handle different data values and eliminates the need for resetting the latch before storing a desired value.

The Gated D latch is constructed by modifying an SR latch, where the R input is tied to the inverse of the D input. When Clk is high, the D input is passed to the output Q.

The two parts are the Master and the Slave latches. The Master latch receives data when the clock is high, while the Slave latch transfers it to the output when the clock goes low.

A flip-flop that changes its state on the falling edge of the clock signal (when it transitions from high to low).

A flip-flop that changes its state on the rising edge of the clock signal (when it transitions from low to high).

Comparing a D flip-flop to a double door system: the first door (Master) accepts data when open, and the second door (Slave) transfers it when closed.

Level-sensitive means the output continuously mirrors the input while the clock is high, while edge-triggered means the output changes only at the clock's edge (rising or falling).

A storage element where the output mirrors the D input as long as the clock is high.

A storage element where the output changes only at the rising edge of the clock signal.

A storage element where the output changes only at the falling edge of the clock signal.

Master-slave uses two latches and a clock, while edge-triggered relies on a single latch and a sensitive clock edge, both achieving single data change per clock cycle but with different mechanisms.

A flip-flop that changes its state at the rising edge of the clock signal, it uses a single latch and a sensitive edge for efficient operation.

A graphical representation of a D flip-flop using a box with input D, output Q, and a clock symbol. A small triangle indicates positive edge-triggered operation.

The triangle means it's edge-triggered, and the circle represents a negative-edge trigger.