Computer Architecture PDF

Computer Architecture Eng. Mohammad N. Olaimat Unit-02: Computer Engineering & Interfaces 1. Computer Components Modern computer designs are based on the von Neumann architecture whose principal concepts are the following:  Data and ins...

Computer Architecture Eng. Mohammad N. Olaimat Unit-02: Computer Engineering & Interfaces 1. Computer Components Modern computer designs are based on the von Neumann architecture whose principal concepts are the following:  Data and instructions are stored in the same read–write memory device;  Data and instructions are addressable by unique locations in the memory device;  Execution of instructions occurs in a sequential pattern from one instruction to the next unless explicitly altered by a generated system control-signal. There is a limited set of basic digital-logic components that can be configured in various organizations to store data & instructions and perform arithmetic and logical operations on that data. There are two system configurations to achieve output (data or events): Hardwired Programming: If a particular operation to be performed, a configuration of the logic components designed specifically for that task could be constructed. The resulting “program” is in the form of hardware and is termed a hardwired program. This system accepts data and produces output as depicted in Figure-1. General-Purpose Programming: A hardware organization that performs various functions on data depending on control signals applied to its components. This system accepts data and control signals and produces output. Hence, instead of rewiring the hardware components for each new operation, the programmer supplies only a new set of control signals to the computer components, as depicted in Figure-2. Any computing operation consists of a sequence of mini-steps. At each step, a set of arithmetic and/or logical operations are performed on data; therefore, a new set of control signals is needed. Each set of control signals is programmed in hardware by a unique code. Programming is now configurable, as a new sequence of codes are provided instead of rewiring the hardware electronic circuits for each new operation. Each code is practically an instruction; a sequence of codes (or instructions) is called software. A computer designer should now add to the system a device that accepts a sequence of codes (instructions) and accordingly generates control signals: Instruction Interpreter. The two major components: an Instruction Interpreter and a module of arithmetic & logic functions are integrated into the computer CPU. 1  Figure-1 Figure-2 A computer requires reading data and instructions and producing an output (data or event). An input subsystem is needed that contains components for reading data and instructions, in any form, and converting them into an internal form of computer signals. Likewise, an output module is required. Both modules are referred to as I/O Module (or, I/O components). Lookup Figure-3. An I/O device reads and writes instructions and data serially. However, a program control may not follow instructions sequentially. In addition, operations on data may require access to more than one data-element at a time in a predetermined sequence of events. Thus, there must be a location to temporarily store both instructions and data: That module is called Main Memory. Lookup Figure-3. The computer CPU must interact with other computer components to perform computational operations. The CPU fetches instructions and exchanges data with the Main Memory: It employs two internal registers to achieve this task: a Memory Address Register (MAR), which specifies the address in memory for the next read or write operation, and a Memory Buffer Register (MBR), which contains the data to be written into memory or the data to be read from it. Each memory address contains a binary number that can be interpreted as either an instruction or data. Lookup Figure-3. The CPU must communicate with the I/O Subsystem to read and write data from/to external I/O devices. It employs an I/O Address Register (I/OAR) to identify a particular I/O device and an I/O Buffer Register (I/OBR) as a storage for data exchanged between an I/O module and the CPU. An I/O module also transfers data from external devices to the Main Memory, and vice versa. Lookup Figure-3. 2  Figure-3 2. Computer Function The principal function performed by a computer is the execution of a program, which is decomposed of a set of instructions read from Main Memory. The processing operation of an instruction is called an Instruction Cycle which consists of the Fetching Cycle and the Execution Cycle. Program execution may halt only if a program instruction terminates it or unrecoverable error occurs. Instruction Cycle An Outline of the Computer Instruction Cycle At the beginning of each instruction cycle, the processor fetches an instruction from the Main Memory. In a typical processor, a register called the Program Counter (PC) holds the address of the instruction to be fetched next. Unless controlled otherwise, the processor sequentially increments the PC after each instruction fetching so that it will fetch the next instruction in sequence. The fetched instruction is subsequently loaded into a register in the processor known as the Instruction Register (IR). This instruction is represented by a set of digital bits that encode the operation the processor should perform. The microprocessor interprets that instruction and performs the required task in coordination with the computer components aided by the operating system. Categories of a Computer Instruction In general, a computer operation may involve one or a combination of the following basic functional categories:  Processor-Memory: Data may be transferred from processor to memory or from memory to processor.  Processor-I/O: Data may be transferred to or from a peripheral device by transferring between the processor and an I/O module.  Data processing: The microprocessor may perform arithmetic or logic operation on data.  Control: An instruction may signal that the sequence of execution be altered. 3 A detailed Instruction Cycle States (Figure-4):  Instruction address calculation (iac): Determining the address of the next instruction to be executed.  Instruction fetch (if): Reading the instruction from the system memory into the microprocessor.  Instruction operation decoding (iod): Analyzing the instruction to determine type of the operation to be performed and specifying the required operand(s).  Operand address calculation (oac): If the operation involves a reference to an operand in memory, determining its memory location. If the required operand resides in an I/O device, identifying the I/O device and determining the address of the operand in cooperation with the I/O Subsystem.  Operand fetch (of): Fetching the operand from memory or the I/O device.  Data operation (do): Performing the operation indicated by the instruction.  Operand store (os): Writing the result into the system-memory or an I/O device. Figure-4: Instruction Cycle States Remarks about Computer Instructions  Execution cycle of an instruction may require multiple references to the system-memory.  Instead of memory references, an instruction may specify an I/O operation.  For an instruction cycle, some states may be null and others may be repeated.  An instruction may require multiple operands (multiple reads) and produce multiple results (multiple writes). Computer Interrupt Signals Is the previous illustration of the Instruction Cycle precise? Computer hardware, such as the memory-controller & I/O subsystems, and software may produce control signals to intercommunicate with the microprocessor for the objective of interrupting the normal sequence of the current Instruction Cycle. Interrupts are primarily generated to alleviate the severity of the disparity in operational speed between the microprocessor and the other computer’s hardware components. Interrupt generation and processing technologies are NOT of our concern for now; instead, we would focus on the implications of interrupts on the Instruction Cycle and the computer’s associated interconnection structures. However, we should be aware of the following events as an interrupt occurs: 4   The microprocessor (MP) suspends execution of the current program and saves its state, such as saving the address of the next instruction to be executed and any other data relevant to the MP’s current activity;  The MP sets the program counter to the starting address of an interrupt handler routine. Interrupts are classified into various classes, depending on their sources, and each of which has its own particular operational context. Table-1 summarizes these facts. Table-1 Impact of Interrupts upon Instruction Cycle A. Program Execution Cycle without an Interrupt Signaling (Figure-5) Objective: A user program performs a series of WRITE system calls interleaved with logical processing. The program’s code segments 1, 2, and 3 refer to sequences of instructions that do not involve I/O processing. The WRITE calls are issued to an I/O program that performs the I/O processing. Since the I/O operation may consume a relatively long time to complete, the user program (the microprocessor) is stopped at the point of the WRITE call for a considerable period of time. The I/O program consists of three sections:  A sequence of I/O instructions, labeled as 4, to prepare for the I/O operation, such as buffering the data into an I/O buffer first and constructing the parameters for the I.O device;  I/O command. This command trigger the data transfer operation. The program must wait for the I/O device to perform the requested task. The program should periodically poll the device to determine if the I/O operation is complete.  A sequence of instructions, labeled as 5, to complete the operation. This may include setting a flag on the I/O device indicating the success or failure of the operation. B. Program Execution Cycle with an Interrupt - Short I/O operation (Figure-6)  The user program executes normally until it makes a WRITE system call.  In consequence, the operating system’s I/O program prepares and commands the I/O device to process the data. At this instance the processing control returns to the user program to resume normal execution. The I/O operation is conducted in parallel time along with the execution of the logical instructions of the main user program by the CPU.  As the I/O device completes the current I/O operation or it becomes ready to be serviced again, [when it is ready to accept more data from the processor] the I/O controller for that I/O device transmits an interrupt signal to the microprocessor (MP). The MP responds by suspending execution of the current program, branching off to an operating-system subprogram to service that particular I/O device that is called the Interrupt Service Routine. The main program resumes execution after the Service Routine has completed servicing the I/O device. C. Program Execution Cycle with an Interrupt - Long I/O operation In this case, the user program reaches the second WRITE call before the I/O operation spawned by the previous call is complete. The result is that the user program hangs at this point. When the first I/O operation is complete, the second WRITE call may be processed and a new I/O operation may be started (Figure-7). 5 Alert: The interrupt-processing cycle is handled concurrently by both the MP and the OS; our emphasis has been on the MP! Figure-5 Figure-6 Figure-7 Program Timing Cycles (Figure-8) Figure-8-A : Program Timing: Short I/O waiting without interrupts Figure-8-B : Program Timing: Short I/O waiting with interrupts Figure-8-C : Program Timing: Long I/O waiting without interrupts Figure-8-D : Program Timing: Long I/O waiting with interrupts 6  Figure-8 Multiple Interrupts Processing Is it probable for multiple interrupts to occur? How so? Multiple interrupts may occur whose sources are different. For instance, a program may be reading data from an I/O device in blocks and yet another program is writing blocks of data structures into a database. Each of the programs would normally generate multiple interrupts in sequence or in parallel with one another during data transfer of the data blocks. Two management approaches of multiple interrupts are present: A. Sequential Interrupt Management Scheme This scheme disables the interrupt engine while an interrupt is being processed. A disabled interrupt is placed in pending state by the Interrupt Controller and will be serviced by the MP after it will have enabled interrupts. After the Interrupt Service Routine completes, interrupts are immediately enabled before resuming an interrupted user program and the processor subsequently determines if additional interrupts have been generated. This approach indicates that interrupts are handled in strict sequential order. What is the problem with this scheme? Lookup Figure-9. 7  Figure-9 Figure-10 B. Nested Interrupt Management Scheme This scheme defines priorities of interrupts and it enables an interrupt of higher priority to interrupt the interrupt-handler of a lower-priority interrupt. Consider a system with three I/O devices: a printer, a disk, and a communications line, with increasing priorities of 2, 4, and 5, respectively. Examine Figure-10 closely to validate the interrupts handling priorities and trace the execution pipeline. The Instruction Cycle States diagram (Figure-4) has been updated by Figure-11 to reflect introducing interrupt occurrence in the computer system. Figure-11 8 I/O Function An I/O hardware module can exchange data directly with the microprocessor. The microprocessor can read data from or write data to that I/O module. Therefore, the MP should be equipped with the technology to enable it to identify a specific I/O device that is controlled by a particular I/O module. Thus, an I/O instruction sequence similar in form to that of instructions referencing system-memory are employed. However, in some cases, the MP grants an I/O module the authority to exchange data with the system-memory directly; hence, the I/O module issues read or write commands to memory by relieving the MP of the responsibility of managing and tracking the subtasks of the I/O operation. 3. Computer Network (Interconnection Structure) The computer is a network of hardware components; thus, there must exist pathways for interconnecting those modules. Figure-12 depicts the types of input and output applicable to each module type of the computer basic network: A. Memory: A word of data can be read from or written into the system-memory. The nature of the operation is defined by read and write control signals. The location for the operation is specified by an address. B. I/O Module: Internally, an I/O module is functionally almost identical to the system-memory. In addition, an I/O module may control more than one external I/O device via its I/O ports. There must exist external data paths for the input and output of data with an external device. An I/O module should be able to dispatch interrupt signals to the MP. C. Microprocessor (MP): The MP reads instructions and data and stores data after processing. It should leverage control signals to manage the operation of the computer system. It should also be able to receive interrupt signals. Figure-12 4. Computer Bus Interconnection The bus was the primary technology utilized for computer-system's component interconnection in general-purpose computers and embedded systems (microcontrollers). A bus is a communication pathway connecting two or more devices. It is a shared transmission medium among multiple devices; thus, only one device at a time can transmit on the 9 bus. A bus consists of multiple communication pathways, or lines. Several lines of a bus can be used to transmit binary digits simultaneously (in parallel). Computer systems are equipped with a number of different buses that provide pathways between components at various levels of the computer system hierarchy. The bus types are the following: System Bus: It is the bus that interconnects the major computer components (MP, System-Memory, I/O modules). A system bus consists typically of fifty to hundreds of separate lines. Each line is assigned a particular function; Data Bus: It consists of the hardware data lines that are used to transport data among the components of the system. The data bus may consist of 32, 64, 128, or more separate parallel lines; this is technically called the bus width; Address Bus: The lines of the address bus are employed to determine the source or destination of the data being transported by the data bus. Also, the address lines are used to address the I/O ports; Control Bus: The control lines are utilized to control the access to and the use of the data and address buses. The Control Bus transmits command and timing information to system modules. Timing signals indicate the validity of data and address information; the command signals specify the type of the operations to be performed. The types of the control signals include: Memory Write: It causes data on the data bus to be written into the addressed location. Memory Read: It causes data from the addressed location to be placed on the data bus. I/O Write: It causes data on the data bus to be output to the addressed I/O port. I/O Read: It causes data from the addressed I/O port to be placed on the data bus. Transfer ACK: It indicates that data have been read from or written into the data bus. Bus Request: It indicates that a module has requested control of the bus. Bus Grant: It indicates that a requesting module has been approved to gain access of the bus. Interrupt Request: It indicates that an interrupt is currently pending. Interrupt ACK: It acknowledges that the pending interrupt has been recognized. Clock: It is used to synchronize operations of the various computer components. Reset: It initializes all modules. Are there any more types of buses or interconnection organizations? 10