Computer Components and Programming Basics

The number of parallel lines in a data bus, typically 32, 64, 128, or more.

Lines used to specify the location (memory address or I/O port) for data transfer.

Lines controlling access and use of data and address buses, including timing and commands.

Command to store data at a specific memory location.

Command to retrieve data from a specific memory location.

Confirmation that data transfer was successful.

Module requests and gains access to the bus.

Commands like Memory Write, Memory Read, I/O Write, I/O Read, Bus Request/Grant, Transfer ACK, Interrupt Request, Interrupt ACK, Clock, and Reset.

To execute a program, which is a set of instructions read from Main Memory.

The Fetching Cycle (retrieving instructions) and the Execution Cycle (carrying out the instructions).

It reads and writes data and instructions to and from external devices.

It temporarily stores instructions and data needed for the CPU to work.

Using the Memory Address Register (MAR) to identify a location, and the Memory Buffer Register (MBR) to hold the data.

Using the I/O Address Register (I/OAR) to identify the device and the I/O Buffer Register (I/OBR) for data transfer.

Program execution halts.

To fetch an instruction from Main Memory and then execute it.

It stores the address in memory of the next piece of data the CPU needs.

It holds the actual data that is being read from or written to memory.

A technique where an I/O module can directly access system memory without involving the microprocessor (MP). This allows the I/O module to handle data transfers independently, freeing up the MP for other tasks.

The interconnected arrangement of hardware components within a computer system, enabling data transfer between different modules like memory, I/O modules, and the microprocessor.

The process of reading data from or writing data into the system memory.

I/O modules act as intermediaries between the computer and external devices. They control data transfer, manage I/O ports, and can generate interrupt signals for the MP.

The MP is the control center of the computer. It reads instructions and data, processes them, and manages the system's operation. It can receive interrupt signals from I/O modules.

A shared communication pathway connecting multiple devices within a computer system.

The main bus connecting the central components of a computer: the microprocessor (MP), system memory, and I/O modules.

The lines within a bus responsible for transmitting data between computer components.

The ability of a bus to transmit multiple binary digits (bits) at the same time, improving data transfer speed.

Different types of buses exist within a computer system, each tailored for specific communication needs and levels of the system hierarchy.

A signal from a device or program, interrupting the CPU's current task to handle an urgent request.

A specific program within the operating system dedicated to handling a specific type of interrupt.

An I/O operation where the CPU continues execution while the device handles the operation, interrupting only when completed.

Interrupts allow the CPU to efficiently handle I/O operations concurrently with other tasks, increasing overall system performance.

Multiple interrupts allow the system to handle various devices and tasks simultaneously, further enhancing efficiency.

A register that holds the memory address of the next instruction to be executed. It's incremented after each instruction fetch if not otherwise controlled.

A register that temporarily stores the fetched instruction before it's decoded and executed.

A sequence of steps a processor takes to execute a single instruction. This cycle involves fetching, decoding, and executing the instruction.

A category of computer instructions that involve transferring data between the processor and main memory.

A category of instructions that transfer data between the processor and peripheral devices.

A category of instructions that perform arithmetic or logical operations on data.

An instruction that modifies the normal execution sequence of other instructions.

The step in the instruction cycle where the address of the next instruction is determined.

The step where the memory location of the operand is determined if the instruction needs data from memory.

The stage where the actual instruction execution happens, processing the data according to the instruction's command.