Control Processing Unit PDF

# Introduction - Performs bulk of data processing operations. A diagram of a central processing unit (CPU) is included. The CPU is composed of three sections: Control, Register set, and Arithmetic logic unit (ALU). - Register set stores the immediate data used during the execution of the instruc...

# Introduction - Performs bulk of data processing operations. A diagram of a central processing unit (CPU) is included. The CPU is composed of three sections: Control, Register set, and Arithmetic logic unit (ALU). - Register set stores the immediate data used during the execution of the instruction. - The ALU performs the required microoperations for executing the instructions. - Control unit supervises the transfer of information among the registers and instruct the ALU as to which operation to perform. - Computer architecture includes the instruction formats, addressing modes, instruction set and general organization of CPU registers. # Types of architecture - Computer architecture includes the instruction formats, addressing modes, instruction set and general organization of CPU registers. - Two computer architectures according to CPU registers - RISC and CISC (RISC- Reduced Instruction Set Computer, CISC- Complex Instruction Set Computer) - According to memory usage for programs and data, there are again two architectures- embedded (Harvard computer architecture) and nonembedded (stored program computer SPC). # General register organization - Intermediate values are stored in processor registers to make CPU tasks more efficient and convenient. - CPU registers are efficiently connected through a common bus system. - The registers communicate with each other not only for direct data transfers, but also while performing various microoperations. - Hence, it is necessary to provide a common unit that can perform all the arithmetic, logic, and shift microoperations in the processor. # Bus system A diagram of a bus system is included. Here, a processor is composed of the following parts: - Clock - R1 through R7 registers - Load - SELA - MUX - 3x8 decoder - SELD - Arithmetic logic unit (ALU) - Input - Output - (a) Block diagram - (b) Control word # Encoding of Register Selection Fields | Binary Code | SELA | SELB | SELD | |---|---|---|---| | 000 | Input | Input | None | | 001 | R1 | R1 | R1 | | 010 | R2 | R2 | R2 | | 011 | R3 | R3 | R3 | | 100 | R4 | R4 | R4 | | 101 | R5 | R5 | R5 | | 110 | R6 | R6 | R6 | | 111 | R7 | R7 | R7 | # Encoding of ALU Operations | OPR Select | Operation | Symbol | |---|---|---| | 00000 | Transfer A | TSFA | | 00001 | Increment A | INCA | | 00010 | Add A + B | ADD | | 00101 | Subtract A - B | SUB | | 00110 | Decrement A | DECA | | 01000 | AND A and B | AND | | 01010 | OR A and B | OR | | 01100 | XOR A and B | XOR | | 01110 | Complement A | COMA | | 10000 | Shift right A | SHRA | | 11000 | Shift left A | SHLA | # Examples of Microoperations for the CPU | Microoperation | SELA | SELB | SELD | OPR | Control Word | |---|---|---|---|---|---| | R1<-R2-R3 | R2 | R3 | R1 | SUB | 010 011 001 00101 | | R4<-R4\/R5 | R4 | R5 | R4 | OR | 100 101 100 01010 | | R6<-R6+1 | R6 | - | R6 | INCA | 110 000 110 00001 | | R7<-R1 | R1 | - | R7 | TSFA | 001 000 111 00000 | | Output<-R2 | R2 | - | None | TSFA | 010 000 000 00000 | | Output<-Input | Input | - | None | TSFA | 000 000 000 00000 | | R4<-sh1 R4 | R4 | - | R4 | SHLA | 100 000 100 11000 | | R5<-0 | R5 | R5 | R5 | XOR | 101 101 101 01100 |