Computer Architecture Lecture Notes PDF

Computer Science Dep. MET 2024-2025 Computer Architecture 2024/2025 Lecture 1 Assis. Prof. Dr. Elmahdy Maree CH1: Computer Architecture and Organization Learning Objectives Upon completion of this lectu...

Computer Science Dep. MET 2024-2025 Computer Architecture 2024/2025 Lecture 1 Assis. Prof. Dr. Elmahdy Maree CH1: Computer Architecture and Organization Learning Objectives Upon completion of this lecture, you will be able to: ◆ Describe the design of digital basic building blocks Assis. Prof. Dr. Elmahdy Maree  Intrduction to Computer Architecture and Organization * Computer architecture Refers to those attributes of a system visible to a programmer or those attributes that have a direct impact on the logical execution of a program. Examples of architectural attributes Includes the instruction set, the number of bits used to represent various data types (e.g., numbers, characters), I/O mechanisms, and techniques for addressing memory. * Computer organization; Refers to the operational units and their interconnections that realize the architectural specifications. Organizational attributes Includes those hardware details transparent to the programmer, such as control signals; interfaces between the computer and peripherals; and the memory technology used. Lecture 2: Comp. Org. and Arch. CH 1: Digital Building Blocks (Registers, Counters,.) A Top-Level View of Computer Function and Interconnection Lecture 2: Comp. Org. and Arch.  Structure of IAS Computer A Top-Level View of Computer Interconnection IAS stands for Princeton Institute for Advanced Studies. (Von Neumann)  Computer Components: Top-Level View IAS stands for Princeton Institute for Advanced Studies. (Von Neumann)  Computer Components: Top-Level View IAS stands for Princeton Institute for Advanced Studies. (Von Neumann)  Computer Components: Top-Level View IAS stands for Princeton Institute for Advanced Studies. (Von Neumann)  Computer Components: Top-Level View IAS stands for Princeton Institute for Advanced Studies. (Von Neumann) CH 1: Digital Building Blocks (Registers, Counters,.) Digital Building Blocks 1. Registers 2. COUNTERS 3. BUS 4. RAMS Lecture 2: Comp. Arch. and Org. Digital Logic and Computer Architecture MET 2024-2025 Lecture 2: Flip Flops Digital Logic and Computer Architecture MET 2024-2025 D Flip flop Function Table Symbol : Equations Lecture 1: Flip Flops Digital Logic and Computer Architecture MET 2024-2025 T Flip flop Function Table Symbol : Lecture 1: Flip Flops Digital Logic and Computer Architecture MET 2024-2025 JK Flip flop Function Table Symbol : Lecture 12: Flip Flops CH 1: Digital Building Blocks (Registers, Counters,.) Registers REGISTERS  CH 1: Digital Building Blocks (Registers, Counters,.) Buffer Registers Registers are a type of computer memory built directly into the processor or CPU (Central Processing Unit) that is used to store and manipulate data during the execution of instructions. A register may hold an instruction, a storage address, or any kind of data BUFFER REGISTERS  BUFFER REGISTERS Buffer register. Symbol : BUFFER REGISTERS  BUFFER REGISTERS Controlled buffer register with parallel load. Symbol : Assis. Prof. Dr. El Mahdy Maree Controlled Buffer Registers  BUFFER REGISTERS Controlled buffer register. Hardware Implementation : Controlled Buffer Registers  Three-State Registers NORMALLY OPEN Normally open switch NORMALLY CLOSED Normally closed switch. Three-state buffer register  Three-State Registers The main application of three-state switches is to convert the two-state output of a register to a three-state output. Symbol : Three-state buffer register  Shift Registers Shift-left register. Symbol : Shift-right register. Shift Shift Registers -left timing diagram.  CH 1: Digital Building Blocks (Registers, Counters,.) BUS-ORGANIZED COMPUTERS Lecture 2: Comp. Arch. and Org.  Bus-Organized Computers A bus is a group of wires that transmit a binary word Bus An abbreviated form of the bus example Bus Assis. Prof. Dr. El Mahdy Maree Questions Assis. Prof. Dr. Elmahdy Maree THANK YOU Computer Science Dep. MET 2024-2025 CS 311 Computer Architecture 2024/2025 Lecture 2 Assis. Prof. Dr. Elmahdy Maree CH 1: Digital Building Blocks (Registers, Counters,.) A Top-Level View of Computer Function and Interconnection Lecture 2: Comp. Org. and Arch.  Structure of IAS Computer A Top-Level View of Computer Interconnection IAS stands for Princeton Institute for Advanced Studies. (Von Neumann)  Computer Components: Top-Level View IAS stands for Princeton Institute for Advanced Studies. (Von Neumann) CH 1: Digital Building Blocks (Registers, Counters,.) Digital Building Blocks 1. Registers 2. BUS System 3. COUNTERS 4. RAMS Lecture 2: Comp. Arch. and Org. CH 1: Digital Building Blocks (Registers, Counters,.) COUNTERS A. SYNCHRONOUS COUNTERS B. ASYNCHRONOUS (RIPPLE) COUNTERS Lecture 2: Comp. Arch. and Org. CH 1: Digital Building Blocks (Registers, Counters,.) SYNCHRONOUS COUNTERS Lecture 2: Comp. Arch. and Org.  CH 1: Digital Building Blocks (Registers, Counters,.) Design of Sequential Circuit Example 1: Design a 3 bit Counter (Using “T” FF) which counts in binary form as follows; 000, 001, 010, … 111, 000, 001, … Solution 2- State diagram: Lecture 2: Sequential Circuit  CH 1: Digital Building Blocks (Registers, Counters,.) 4- State Table: Lecture 2: Sequential Circuit  CH 1: Digital Building Blocks (Registers, Counters,.) 5- K-Map for FFs inputs and circuit Outputs + + + Lecture 2: Sequential Circuit  CH 1: Digital Building Blocks (Registers, Counters,.) 5- K-Map for FFs inputs and circuit Outputs Lecture 2: Sequential Circuit  CH 1: Digital Building Blocks (Registers, Counters,.) 6- Circuit diagram: Symbol : Lecture 2: Sequential Circuit  SYNCHRONOUS COUNTERS SYNCHRONOUS COUNTERS Ring Counters Many digital circuits participate during a computer run to fetch and execute instructions Symbol : Controlling a sequence of operations RING COUNTERS  RING COUNTERS IMPLEMENTATION SAP-1 ring counter Hardware Implementation RING COUNTERS CH 1: Digital Building Blocks (Registers, Counters,.) ASYNCHRONOUS (RIPPLE) COUNTERS Lecture 2: Comp. Arch. and Org.  RIPPLE COUNTER (Asy.) ASYNCHRONOUS (RIPPLE) COUNTERS -ve edge up counter (Asyn) Ripple counter design  ASYNCHRONOUS COUNTERS ASYNCHRONOUS (RIPPLE) COUNTERS Controlled ripple counter(up counter –ve edge) Symbol : SAP-1 program counter COUNTERS  Computer Components: Top-Level View IAS stands for Princeton Institute for Advanced Studies. (Von Neumann)  CH 1: Memory System Memory System ROM RAM Lecture 2 Comp. Arch. and Org. CH 4: Memory System ROM Design Lecture 8 Comp. Arch. and Org.  CH 1: Memory System ROM Design Design 8 x 4 ROM. Lecture 2 Comp. Arch. and Org.  CH 1: Memory System Types of ROMs Mask Programmed ROM Programmed during manufacturing Programmable Read-Only Memory (PROM) Blow out fuses to produce ‘0’ Erasable Programmable ROM (EPROM) Erase all data by Ultra Violet exposure Electrically Erasable PROM (EEPROM) Erase the required data using an electrical signal Lecture 2 Comp. Arch. and Org.  CH 5 Memory System Cache Memory Lecture 2: Comp. Arch. and Org.  CH 5: Memory System The Memory Hierarchy 24 Lecture 2:Comp. Arch. and Org. Questions Assis. Prof. Dr. Elmahdy Maree THANK YOU Computer Science Dep. MET 2024-2025 CS 311 Computer Architecture 2024/2025 Lecture 3 Assis. Prof. Dr. Elmahdy Maree CH 1: Digital Building Blocks (Registers, Counters,.) A Top-Level View of Computer Function and Interconnection Lecture 3: Comp. Org. and Arch.  Structure of IAS Computer A Top-Level View of Computer Interconnection IAS stands for Princeton Institute for Advanced Studies. (Von Neumann)  Computer Components: Top-Level View IAS stands for Princeton Institute for Advanced Studies. (Von Neumann) CH 1: Digital Building Blocks (Registers, Counters,.) Digital Building Blocks ALU Dsign Lecture 3: Comp. Arch. and Org. CH 1: Digital Building Blocks (Registers, Counters,.) COUNTERS Lecture 3: Comp. Arch. and Org. CH 1: Digital Building Blocks (Registers, Counters,.) Lecture 3: Comp. Arch. and Org.  CH 2: ALU Design Adders 1. Binary Adder Half Adder Full Adder 2. Binary Subtraction 3.. BCD Adder Lecture 3 Comp. Arch. and Org.  CH 2: ALU Design 8 Lecture 3 Comp. Arch. and Org.  CH 2: ALU Design Full Adder Lecture 3 Comp. Arch. and Org.  CH 2: ALU Design 8 Lecture 3 Comp. Arch. and Org.  CH 2: ALU Design 8 Lecture 3 Comp. Arch. and Org.  CH 2: ALU Design Carry Propagate Adder (CPA) Adding Two 4-Bits Numbers Lecture 3 Comp. Arch. and Org.  CH 2: ALU Design Lecture 3 Comp. Arch. and Org. Carry Propagate Adder (CPA) Adding Two 8-Bits Numbers  CH 2: ALU Design Carry Propagate Adder (CPA) Adding Two 8-Bits Numbers Lecture 3 Comp. Arch. and Org.  CH 2: ALU Design Lecture 3 Comp. Arch. and Org.  CH 2: ALU Design Lecture 3 Comp. Arch. and Org.  CH 2: ALU Design Binary Adder / Subtractor Lecture 3 Comp. Arch. and Org.  CH 2: ALU Design Binary Adder / Subtractor x3 x2 x1 x0 y3 y2 y1 y0 M A3 A2 A1 A0 B3 B2 B1 B0 Cy Binary Adder Ci S3 S2 S1 S0 F3 F2 F1 F0 M: Control Signal Mode: Add / Sub M=0 ➔ F = x + y M=1 ➔ F = x – y Lecture 3 Comp. Arch. and Org. THANK YOU Computer Science Dep. MET 2024-2025 CS 311 Computer Architecture 2024/2025 Lecture 4 Assis. Prof. Dr. Elmahdy Maree CH 1: Digital Building Blocks (Registers, Counters,.) A Top-Level View of Computer Function and Interconnection Lecture 3: Comp. Org. and Arch.  Computer Components: Top-Level View IAS stands for Princeton Institute for Advanced Studies. (Von Neumann)  CH 2: Digital Building Blocks Digital Building Blocks ALU Dsign Lecture 4: Comp. Arch. and Org.  CH 2: ALU Design Multiplication 1. Unsigned Multiplication Fast Multiplication Multiplication with Shifter 2. Signed Multiplication Lecture 4: Comp. Architecture.  CH 2: ALU Design Multiplication Unsigned Multiplication UNSIGNED INTEGERS the following figure illustrates the multiplication of unsigned binary integers, as might be carried out using paper and pencil. Several important observations can be made: Lecture 4: Comp. Architecture.  CH 2: ALU Design Multiplication Unsigned Binary Multiplication (Fast Multiplier) Unsigned Binary Multiplication with Array of Full Adder Lecture 4: Comp. Architecture.  CH 2: ALU Design Multiplication Unsigned Multiplication with Shifter Example: Multiply 11*13 using unsigned multiplication with shifter. Q0 Q0 Q0 Q0 Lecture 4: Comp. Architecture.  CH 2: ALU Design Multiplication Unsigned Multiplication with Shifter Flowchart for Unsigned Binary Multiplication with Shifter Lecture 4: Comp. Architecture.  CH 2: ALU Design Multiplication Unsigned Multiplication with Shifter Hardware Implementation of Unsigned Binary Multiplication with Shifter Lecture 4: Comp. Architecture.  CH 2: ALU Design Multiplication Signed Binary Multiplication TWOS COMPLEMENT MULTIPLICATION Booth’s Algorithm Booth’s Algorithm for Twos Complement Multiplication Lecture 4: Comp. Architecture.  CH 2: ALU Design Multiplication Signed Binary Multiplication 7 Example: Multiply 7*3 using Booth’s Algorithm. -7 Arithmetic Shift Arithmetic Shift Arithmetic Shift Arithmetic Shift Lecture 4: Comp. Architecture. THANK YOU Computer Science Dep. MET 2024-2025 CS 311 Computer Architecture 2024/2025 Lecture 5 Assis. Prof. Dr. Elmahdy Maree  CH 2: Digital Building Blocks Digital Building Blocks ALU Dsign Lecture 4: Comp. Arch. and Org.  CH 2: ALU Design Division Unsigned Division Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Cont’d 𝐴 𝑅 =𝑄+ 𝐵 𝐵 11012 Example1: calculate 102 – – – – Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Cont’d 𝐴 𝑅 =𝑄+ 𝐵 𝐵 11012 Example1: calculate 102 – 0 0 1 0 – 0 0 1 0 – 0 0 1 0 – 0 0 1 0 Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Cont’d 𝐴 𝑅 =𝑄+ 𝐵 𝐵 1 11012 Example1: calculate 102 – 0 0 1 0 1 – 0 0 1 0 0 – 0 0 1 0 1 – 0 0 1 0 Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Cont’d 𝐴 𝑅 =𝑄+ 𝐵 𝐵 0 0 0 1 11012 Example1: calculate 102 – 0 0 1 0 1 – 0 0 1 0 0 – 0 0 1 0 1 – 0 0 1 0 Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Cont’d 𝐴 𝑅 =𝑄+ 𝐵 𝐵 0 1 0 11012 0 0 Example1: calculate 102 – 0 0 1 0 1 1 1 1 1 – 0 0 1 0 0 – 0 0 1 0 1 – 0 0 1 0 Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Cont’d 𝐴 𝑅 =𝑄+ 𝐵 𝐵 0 1 0 11012 0 0 Example1: calculate 102 – 0 0 1 0 1 1 1 1 0 0 1 1 – 0 0 1 0 0 – 0 0 1 0 1 – 0 0 1 0 Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Cont’d 𝐴 𝑅 =𝑄+ 𝐵 𝐵 0 11012 0 0 1 0 1 Example1: calculate 102 – 0 0 1 0 1 1 1 1 0 0 1 1 – 0 0 1 0 1 0 0 0 1 0 – 0 0 1 0 1 – 0 0 1 0 Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Cont’d 𝐴 𝑅 =𝑄+ 𝐵 𝐵 0 11012 0 0 1 0 1 Example1: calculate 102 – 0 0 1 0 1 1 1 1 0 0 1 1 – 0 0 1 0 0 0 0 1 0 0 1 0 – 1 0 0 0 1 – 0 0 1 0 Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Cont’d 𝐴 𝑅 =𝑄+ 𝐵 𝐵 0 11012 0 0 1 0 1 1 Example1: calculate 102 – 0 0 1 0 1 1 1 1 0 0 1 1 – 0 0 1 0 0 0 0 1 0 0 1 0 – 1 0 0 0 0 0 0 0 1 – 0 0 1 0 Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Cont’d 𝐴 𝑅 =𝑄+ 𝐵 𝐵 0 11012 0 0 1 0 1 1 Example1: calculate 102 – 0 0 1 0 1 1 1 1 0 0 1 1 – 0 0 1 0 0 0 0 1 0 0 1 0 – 1 0 0 0 0 0 0 0 0 0 0 1 – 0 0 1 0 Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Cont’d 𝐴 𝑅 0 0 0 1 0 1 1 0 =𝑄+ – 0 0 1 0 𝐵 𝐵 11012 Example1: calculate 102 1 1 1 1 0 0 1 1 – 0 0 1 0 0 0 0 1 0 0 1 0 – 0 0 1 0 0 0 0 0 0 0 0 1 – 0 0 1 0 1 1 1 1 Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Cont’d 𝐴 𝑅 0 0 0 1 0 1 1 0 =𝑄+ – 0 0 1 0 𝐵 𝐵 11012 Example1: calculate 102 1 1 1 1 Q 0 0 1 1 – 0 0 1 0 0 0 0 1 0 0 1 0 – 0 0 1 0 Note: if last result is negative(i.e. the most significant bit is 1) then the 0 0 0 0 remainder will be the minuend (i.e. 0 0 0 1 R value of A before subtraction) else – 0 0 1 0 (i.e. the most significant bit is 0) it will be the last result 1 1 1 1 Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Cont’d 𝐴 𝑅 =𝑄+ 𝐵 𝐵 Legend N R B R B Cout Cin Cout Cin + D N R' D Difference 1 0 N Negative R' Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) with shifter Example: (7/3) Restoring Twos Complement Division Lecture 5: Comp. Architecture.  CH 2: ALU Design Floating Point Numbers 1. Fixed point numbers 2. Floating point numbers Floating point addition and subtraction Lecture 5: Comp. Architecture.  CH 2: ALU Design Floating point representation IEEE 754 32-bit floating-point representation (single precision) 1 bit 8 bits 23 bits ± Mantissa× 2Exponent Sign Mantissa Mantissa should be written using 24 bits in this form: 1.1011…….1 Most Significant Bit of the mantissa is always 1, so no need to store it Store just the fraction bits in 23-bit field Biased exponent: bias = 127 (011111112) Biased exponent = bias + exponent Lecture 5: Comp. Architecture.  CH 2: ALU Design Floating point representation Write -58.2510 in 32-bit floating point (IEEE754 32) 58.2510 = 111010.012 111010.012 = 1.11010012 × 25 Sign bit: 1 (negative) 8 exponent bits: (127 + 5) = 132 = 100001002 23 fraction bits: 110 1001 0000 0000 0000 0000 1 bit 8 bits 23 bits 1 100 0010 0 110 1001 0000 0000 0000 0000 Sign Exponent Fraction Lecture 5: Comp. Architecture. THANK YOU