3D Numerical Simulation of a Z Gate Layout MOSFET for Radiation Tolerance PDF

micromachines Article 3D Numerical Simulation of a Z Gate Layout MOSFET for Radiation Tolerance Ying Wang 1, *, Chan Shan 2 , Wei Piao 1 , Xing-ji Li 3 , Jian-qun Yang 3 , Fei Cao 1 and Cheng-hao Yu 1 1 Key Laboratory of RF Circuits and Systems, Ministry of Education, Hangzhou Dianzi U...

micromachines Article 3D Numerical Simulation of a Z Gate Layout MOSFET for Radiation Tolerance Ying Wang 1, *, Chan Shan 2 , Wei Piao 1 , Xing-ji Li 3 , Jian-qun Yang 3 , Fei Cao 1 and Cheng-hao Yu 1 1 Key Laboratory of RF Circuits and Systems, Ministry of Education, Hangzhou Dianzi University, Hangzhou 310018, China; [email protected] (W.P.); [email protected] (F.C.); [email protected] (C.-h.Y.) 2 College of Information Engineering, Jimei University, Xiamen 361021, China; [email protected] 3 National Key Laboratory of Materials Behavior and Evaluation Technology in Space Environment, Harbin Institute of Technology, Harbin 150080, China; [email protected] (X.-j.L.); [email protected] (J.-q.Y.) * Correspondence: [email protected]


Received: 11 November 2018; Accepted: 11 December 2018; Published: 14 December 2018
 Abstract: In this paper, for the first time, an n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) layout with a Z gate and an improved total ionizing dose (TID) tolerance is proposed. The novel layout can be radiation-hardened with a fixed charge density at the shallow trench isolation (STI) of 3.5 × 1012 cm−2. Moreover, it has the advantages of a small footprint, no limitation in W/L design, and a small gate capacitance compared with the enclosed gate layout. Beside the Z gate layout, a non-radiation-hardened single gate layout and a radiation-hardened enclosed gate layout are simulated using the Sentaurus 3D technology computer-aided design (TCAD) software. First, the transfer characteristics curves (Id -V g ) curves of the three layouts are compared to verify the radiation tolerance characteristic of the Z gate layout; then, the threshold voltage and the leakage current of the three layouts are extracted to compare their TID responses. Lastly, the threshold voltage shift and the leakage current increment at different radiation doses for the three layouts are presented and analyzed. Keywords: bulk NMOS devices; radiation hardened by design (RHBD); total ionizing dose (TID); Sentaurus TCAD; layout 1. Introduction The total ionizing dose (TID) effect is one of the mechanisms that causes radiation-induced anomalies in semiconductor devices. The TID mechanism induces the generation of trapped charges in the dielectrics and interface states along the Si/SiO2 interfaces, causing degradation of a transistor’s performance [1–4]. Due to the downscaling, the net-charge trapping in oxides with a thickness of less than 10 nm is modest [5–9]. Since the thickness of the gate oxide of the simulated transistors is 2 nm, in this work, the net-charge trapping in the oxides is negligible. Therefore, the effects on thick oxides, such as the shallow trench isolation (STI), dominate the TID response of metal-oxide-semiconductor field-effect transistors (MOSFETs). Moreover, the charge trapped in the spacer oxide or at its interface modifies the parasitic series’ resistance, reducing the drive current. In a conventional non-radiation-hardened single gate layout, the STI’s parasitic conduction path (the red arrow in Figure 1a) induced by the TID effect, which is visible only in an n-MOSFET, occurs along the sidewall oxide between the source and the drain, and leads to an increase in the drain current as the radiation dose increases. A widely studied layout with radiation hardness, called the Micromachines 2018, 9, 659; doi:10.3390/mi9120659 www.mdpi.com/journal/micromachines  Micromachines 2018, 9, 659 2 of 8 Micromachines 2018, 9, x FOR PEER REVIEW 2 of 8 enclosed gate layout [12–14], which requires tradeoffs in application [14,15], is presented in Figure 1b. For instance, Layout Transistor a very (ELT), small for width which over length ratio the minimum (W/L) is achievable W/L notisrealistic 2.26 ,for an Enclosed which Layout is a significant Transistor concern (ELT), for in analog which. circuits the minimum Moreover,achievable a larger gateW/L is 2.26 ,will capacitance which is aasignificant cause longer time concern delay,in analog which is circuits. Moreover, not favorable for digitala circuits. larger gate capacitance A large footprint will is cause another a longer time delay, disadvantage of thewhich is not enclosed favorable for digital circuits. A large footprint is another disadvantage gate layout. In circuit design, the area penalty induced by design has been the main drawback. of the enclosed gate layout. In circuit In orderdesign, the area penalty to eliminate induced the parasitic path byand design has been overcome thethe main drawback disadvantages of. an enclosed gate layout,Infor order to eliminate the first time, an the parasiticlayout n-MOSFET path and withovercome a Z gate isthe disadvantages proposed. Moreover, of antheenclosed proposedgate Z layout, gate for the layout is first time, anto applicable n-MOSFET layout withstructures, more complicated a Z gate is proposed. Moreover, the proposed such as fin-field-effect transistorsZ gate layout (FinFETs), is applicable to more tunnel-field-effect complicated transistors (TFETs),structures, such as[18–22]. and nanowires fin-field-effect In this transistors paper, devices (FinFETs), with tunnel-field-effect transistors (TFETs), and nanowires [18–22]. In this the proposed Z gate layout achieve total-dose hardness by eliminating these edges, but at the paper, devices with the proposed Z gate layout expense achieve total-dose of fabrication feasibility hardness due to the byasymmetric eliminating these activeedges, but at the area design, as expense shown in ofFigure fabrication 1c. feasibility First, due to the asymmetric the effectiveness of the proposed activelayout area design, as shown to eliminate the in Figurecurrent leakage 1c. First,is the effectivenessbyof demonstrated Idthe -Vg proposed curves. Then, layout thetototal eliminate shift ofthethe leakage current threshold is demonstrated voltage by Id -Vof and the variation g curves. Then,current, the leakage the total shift of before andtheafter threshold voltage is the radiation and the variation applied, of the leakage are calculated for the current, single gatebefore and the layout, after the radiation enclosed gate is applied, layout, and theare Z calculated gate layout, for the single gate respectively. layout,the Further, thethree enclosed gate layout, simulated layoutsand arethe Z gate layout, compared with respectively. respect to the Further, threshold thevoltage three simulated shift andlayouts are compared the leakage with respect current increase as atofunction the threshold of thevoltage fixed shift and charge the leakage density. Comparing current theincrease as a function ofofthe static characteristics thefixed chargetransistor different density. Comparing layouts, it isthe static found characteristics of the different transistor layouts, it is found that the that the Z gate layout exhibits the best TID response compared with the conventional layouts andZ gate layout exhibits the best TID response compared with the conventional layouts and ELTs. ELTs. Schematic structures Figure1.1. Schematic Figure structuresofof(a)(a) thethe conventional layout, conventional (b) the layout, (b)Hthe gateHlayout, and (c) the gate layout, andproposed (c) the layout. STI, proposed shallow layout. STI, trench shallowisolation. trench isolation. 2.2.Device DeviceStructure Structureand andSimulation Simulation TheZZgate The gatelayout layoutachieves achievesthe theradiation radiationhardness hardnessby byintroducing introducingtwo twoshort shortextra extragates gatesthat that separatethe separate the active active area area and and the theisolation isolationoxides. oxides.It It should shouldbebe noted notedthatthat the the precise, effective precise, W/LW/L effective ratio model of the proposed layout is not available at present; so, the channel ratio model of the proposed layout is not available at present; so, the channel width of the Z gate width of the Z gate layout in thisinwork layout is defined this work as shown is defined in Figure as shown 1c. A 1c. in Figure report proposed A report proposedan effective W/L W/L an effective model of an model ofenclosed an enclosedgate gate layout, and and layout, concluded concluded that that the only way way the only to obtain a lowa aspect to obtain ratioratio low aspect is to is increase the L to increase value. In the rectangular shape of an enclosed gate layout, the minimum W/L the L value. In the rectangular shape of an enclosed gate layout, the minimum W/L achievable is 2.26,is achievable is 2.26, and almost and reached is almost with L with reached = 7 um L =, 7 um which ,implies which aimplies considerable waste of area a considerable waste andofaarea largeandcapacitance a large issue. Although a precise W/L model of the Z gate layout is not available capacitance issue. Although a precise W/L model of the Z gate layout is not available at present, at present, the drain current the level of the Z gate layout, when compared with the drain current of a drain current level of the Z gate layout, when compared with the drain current of a single gate single gate layout with the same W, L, and layout withthetheoverdrive same W, voltage L, and (V thegt overdrive − V th ), (V , V gt = V gsvoltage is gtnearly , Vgt =theVgs same. – Vth),Itisassumes nearly the thatsame. a Z gateIt not need to increase the L assumes that a Z gate layout does not need to increase the L value that high to achieve theasame layout does value that high to achieve the same effective W/L with single gate layout, effective W/L and, with thus, hasgate a single a smaller layout, footprint and, thus,andhasgate capacitance. a smaller footprint and gate capacitance. InInthe thesimulation, simulation,the themain mainparameters parameterswere werekeptkeptthe thesamesamefor forallall three three layouts. layouts. The Thelateral lateral spacers were formed by a layer of SiO and a thick spacers were formed by a layer of SiO2 2and a thick layer of Si3N layer of Si N , and the STI was inserted 3 4,4and the STI was inserted using the using the SiO2.2Because SiO. Becausethe theenclosed enclosedgate gatelayout layoutwas wasnot notable abletotoachieve achieveaasmallsmallW/LW/LatatLL= =0.120.12μm,µm,the thevalues values of R1 and R2 were 0.15 μm and 0.27 μm, respectively, and the effective W/L was calculated by the formula given in , and it was equal to 13.6. The main parameters of the transistors in the simulation are listed in Table 1. Micromachines 2018, 9, 659 3 of 8 of R1 and R2 were 0.15 µm and 0.27 µm, respectively, and the effective W/L was calculated by the formula given in , and it was equal to 13.6. The main parameters of the transistors in the simulation are listed in Table 1. The TID effect on the MOSFET was modeled by adopting the fixed-charge insulator model provided by the sentaurus technology computer-aided design (TCAD) software, which can be used to set a fixed charge density between the STI and the active region. All simulations were performed using a hydrodynamic model with high-field saturation and mobility degradation models that included doping dependence and carrier–carrier scattering. We simulated the effects of the total radiation dose by increasing the fixed charge density on the sidewall oxide. It should be noted that this work is focused only on the effects of fixed charges; so, the interface states were neglected for the reasons below. When a complementary metal-oxide-semiconductor (CMOS) device is exposed to radiation, hole trapping results in fixed charges and interface states in the thick oxides. According to a report on the radiation-induced fixed charge density and interface state density in MOS capacitors , the radiation-induced flat band voltage is predominantly shifted by the fixed charges. The effect of the interface states is minor. Therefore, in this simulation, the interface states were neglected, and only the fixed charge density was modified to reflect the total ionizing dose effect. Moreover, the effects of interface traps were left out of the simulations due to a lack of empirical information about several parameters of interface traps, such as trap energy and density and the capture cross-section, which are necessary for accurate simulations. In addition, we can see from the literature that the tendencies of ∆V th and ∆SS extracted from the simulation results are in good agreement with those from the experimental data of 5 Mrad. Through the three-dimensional (3D) simulation results, they confirm that, for sub-100 nm gate-all-around metal-oxide-semiconductor field-effect transistors (GAA MOSFETs), the fixed charges in the gate spacer predominantly determine ∆V th and ∆SS, i.e., the TID effect. Note that interface traps were not taken in the simulation in this paper. Although that may result in some disagreement in the current levels as obtained with the experimental counterparts, this case does not have much impact on our findings, because the focus of this paper is not on the exact values of currents but on the general trends and relative results of Z gate, enclosed gate, and single gate layouts due to the TID effect. Table 1. The parameters that were used for the device’s simulation. Parameter Value Length of channel 0.12 µm Width of channel 0.21 µm Thickness of n-type poly gate 100 nm Thickness of gate oxide 2 nm Doping of source/drain region 1.0 × 1019 cm−3 Depth of source/drain region 100 nm Doping of p-type substrate 4.0 × 1017 cm−3 3. Results and Discussion 3.1. The Id -Vg Simulation Results In order to verify that the Z gate layout is able to work well in a non-radiation environment, we simulated the Id -V g curves of the Z gate layout, the enclosed gate layout, and the single gate layout at the fixed charge density of 3 × 1010 cm−2 to model the non-radiation scenario. The following simulation results focus on the analysis of the radiation tolerance characteristics of the proposed layout. The degradation of devices is mainly characterized by the threshold-voltage shift and the off-state leakage current. As we know, IDSS is the maximum current that flows through a FET transistor, which is when the gate voltage (VG) supplied to the FET is 0 V. Additionally, it is only valid when the FET transistor is a junction field-effect transistor (JFET) or depletion MOSFET. However, as the proposed Z gate layout transistor is an enhanced MOSFET, we think that the parameters of IDSS and Micromachines 2018, 9, 659 4 of 8 the IDSS /Ioff ratio are unnecessary to investigate. The threshold-voltage is determined by the linear extrapolation Micromachines 2018, method 9, x FORinPEER the linear REVIEW region; thus, the simulation was performed with a very small 4Vof DS8, i.e., 20 mV, 50 mV, and 100 mV [24,27,28]. In this paper, V DS was taken as 20 mV. Moreover, the TID mainly effect willattributed to the fact be more serious when that more V DS trapped reaches V DDcharges. This at can the be STI/body interface will mainly attributed sufficiently to the fact that reduce more the potential trapped chargesbarrier and resultinterface at the STI/body in a largerwillleakage current sufficiently at a high reduce drain voltage. the potential barrierInand addition, result thea larger in use ofleakage a 20 mV drainatbias current a high gives drainthevoltage. best results for thethe In addition, Z use gateoflayout a 20 mV in drain comparison bias givesto the the alternatives best results for (results the Znot gateshown). layout Thus, in this paper, in comparison to thethe three layout alternatives types not (results are simulated shown). Thus,at theindrain this bias ofthe paper, 20 three mV, whichlayoutsweeps types are thesimulated gate biasat from 0 V tobias the drain 1.5 V.of 20 mV, which sweeps the gate bias from 0 V toThe 1.5 simulation V. results of the Id-Vg curves of the single gate layout are shown in Figure 2a, where it can Thebesimulation seen that the leakage results of thecurrent significantly Id -V g curves increases of the single as the are gate layout fixed showncharge density in Figure 2a,increases, where it andbethat can seenthethaton-current the leakageincreases slightly as increases current significantly the fixedaschargethe fixeddensity charge increases. The simulation density increases, and that results the of the Idincreases on-current -Vg curvesslightly of the enclosed as the fixedgate layoutdensity charge are shown in Figure increases. The2b, where the simulation Id-Vg curves results of the Ialmost -V d g overlap curves of with the each enclosed other, gate demonstrating layout are shown a small in impact Figure 2b, of the where TID the I effect -V d g on curvesthe enclosed almost gate overlap layout. with each other, demonstrating a small impact of the TID effect on the enclosed gate layout. The simulation The simulation resultsresults of ofthe theIIdd-V -Vgg curves of the Z gate layout are shown shown in in Figure Figure 2c, 2c, wherein wherein itit can be seen seen that thatthetheleakage leakagecurrent currentincreases increases slightly slightly as as thethe fixed charge fixed chargedensity increases. density The increases. radiation The radiationtolerance characteristic tolerance characteristicof theofZthe gateZ layout gate layoutwas verified by comparison was verified by comparisonwith that withofthatthe single of gate layout. the single The curves gate layout. The curves of the Z gate of the layout Z gate layout arearesimilar similartotothose thoseofofthe theenclosed enclosed gate gate layout; namely,the namely, the leakage leakage current current increasedincreased very very little little as the fixedas charge the fixed density charge density increased, increased, demonstrating demonstrating that the Z gate layout that thewas Z radiation gate layout was radiation tolerant at the fixed tolerant chargeatdensities the fixed at charge of 3.5 × 10 the STI densities at12the −2 , cmSTI of 3.5 the same× 10as12 the cm−2enclosed , the same as layout. gate the enclosed gate layout. (a) (b) (c) Figure2.2. The Figure The simulation simulation results resultsof ofthe theIIdd-V -Vgg curve of (a) the single gate gate layout, layout, (b) (b) the the enclosed enclosed gate gate layout,and layout, and(c)(c)the theZZgate gatelayout. layout. 3.2. 3.2. Comparison Comparison of of Key Key Transistor TransistorPerformance PerformanceParameters Parameters To Tocompare comparethe TID the response TID responseof the of transistors fairly,fairly, the transistors the threshold voltagevoltage the threshold and leakage and current leakage parameters were extracted at the fixed charge density of 3 × 10 10 cm − 2 and 3.5 × 10 12 cm −2 to model current parameters were extracted at the fixed charge density of 3 × 10 cm and 3.5 × 10 cm−2 to 10 −2 12 the pre-the model andpre- post-radiation scenarios, and post-radiation respectively. scenarios, The results respectively. Theofresults the threshold voltage and of the threshold leakage voltage and current leakageare listedare current in Tables 2 and listed in 3, 2respectively. Table and 3, respectively. In In Table Table2,2,the thethreshold thresholdvoltage voltageof ofthe thenon-radiation-hardened non-radiation-hardened single single gate gate layout layout atat pre- pre- and and post-radiation post-radiation is 363 mV and 138 mV, respectively, and the total shift is 225.56 mV; for the other is 363 mV and 138 mV, respectively, and the total shift is 225.56 mV; for the other two two radiation-hardened radiation-hardened layouts, layouts, the the total total shift shift is is below below 30 30 mV. mV. Thus, Thus, regarding regarding the the shift shift value value inin descending descending order, the order of three layout types is the single gate layout, the Z gate layout, and order, the order of three layout types is the single gate layout, the Z gate layout, and the the enclosed enclosedgate gatelayout. layout. Table 2. Vth in the pre- and post-radiation scenarios. Layout Vth-pre (mV) Vth-post (mV) ΔVth (mV) single gate 363 138 226 enclosed gate 374 374