Scaling and Advanced MOSFETs PDF

Scaling Theory What is Scaling? - Moving VLSI designs to new fabrication processes - Shrinking the size of the circuitry 1961 2001 2006 First Planar Integrated Circuit Pentium 4 Processor Itanium 2 Dual Processor Tw...

Scaling Theory What is Scaling? - Moving VLSI designs to new fabrication processes - Shrinking the size of the circuitry 1961 2001 2006 First Planar Integrated Circuit Pentium 4 Processor Itanium 2 Dual Processor Two Transistors 42 Million Transistors 1.7 Billion Transistors  Scaling Theory Why do we Scale? 1) Improve Performance More complex systems 300mm wafer 2) Increase Transistor Density Reduce cost per transistor & size of system 3) Reduce Power Smaller transistors require less supply voltage 10/23/2024 ECC 302, ECE Department, NIT Durgapur 2  Scaling Theory Scaling Predictions - In 1965, Gordon Moore of Intel predicted the exponential growth of the number of transistors on an IC. - Transistor count will doubled every 2-3 years - Predicting >65,000 transistors in 1975 Moore’s Prediction (1965) 10/23/2024 ECC 302, ECE Department, NIT Durgapur 3  Scaling Theory Timeline of Major Events 2006 Intel Ships 1st Billion Transistor uP 1971 1968 Intel Introduces the 4004, 1st single chip uP (2300 transistors) Noyce and Moore Form Intel 1958 First Integrated Circuit (Noyce/Fairchild & Kilby/Texas Instruments) 1947 First Transistor (Bell Labs) 10/23/2024 ECC 302, ECE Department, NIT Durgapur 4  Scaling Theory How much can we shrink? - Chip Area (A) A  1 1 S  1S   1S  X Y 1 1 A  S Chip Area for a Circuit (A) scales following : 1 S2 Note: In addition, the die sizes have increased steadily, allowing more transistors per die  Scaling Theory I. Full Scaling (Constant-Field) The principle of constant-field scaling lies in scaling the device voltages and the device dimensions (both horizontal and vertical) by the same factor, s (> 1), such that the electric field remains unchanged. - Reduce physical size of structures by 30% in the subsequent process W = Width of Gate L = Length of Gate tox = thickness of Oxide xj = depth of doping - Reduce power supplies and thresholds by 30% - we define: S ≡ Scaling Factor > 1 - Historically, S has come in between 1.2 and 1.5 for the past 30 years 10/23/2024 ECC 302, ECE Department, NIT Durgapur 6 Full Scaling (Constant-Field) Scaling Theory Scaling Effect on Device Characteristics : Power - Static Power in the MOSFET can be described as: P  I DS VDS + - both quantities scale by 1/S ID VDS I V P - P'  DS  DS  2 S S S Power scales down by S2, this is great!!!  Full Scaling (Constant-Field) Scaling Theory Scaling Effect on Device Characteristics : Power Density + - Power Density is defined as the power consumed per area ID VDS - this is an important quantity because it shows how much heat - is generated in a small area, which can cause reliability problems P PDensity  Area - Power scales by 1/S2 - Area scales by 1/S2 (because W and L both scale by S and Area=W∙L) - this means that the scaling cancels out and the Power Density remains constant This is OK, but can lead to problems when IC’s get larger in size and the net power consumption increase  Scaling Theory II. Constant Voltage Scaling – only dimensions scale, voltages remain constant - Constant-Voltage Scaling refers to scaling the physical quantities (W,L,tox,xj,NA) but leaving the voltages un-scaled (VT0, VGS, VDS) - while this has some system advantages, it can lead to some unwanted increases in MOSFET characteristics 10/23/2024 ECC 302, ECE Department, NIT Durgapur 9  Scaling Theory Constant Voltage Scaling Scaling Effect on Device Characteristics : Power + - Instantaneous Power in the MOSFET can be described as: ID VDS P  I DS VDS - - but in Constant-Voltage Scaling, IDS increases by S and VDS remains constant P'  S  I DS VDS  S  P Power increases by S as we get smaller, this is not what we wanted!!! Constant Voltage Scaling Scaling Theory Scaling Effect on Device Characteristics : Power Density + - Power Density is defined as the power consumed per area ID VDS - we’ve seen that Power increases by S in Constant-Voltage Scaling - - but area is still scaling by 1/S2 SP ' PDensity   S3  P  Area     2  S - This is a very bad thing because a lot of heat is being generated in a small area  Scaling Choices So Which One Do We Choose? - Full Scaling is great, but sometimes impractical. - Constant Voltage can actually be worse from a performance standpoint Full Constant-V Quantity Scaling Scaling Cox' S S IDS' 1/S S Power' 1/S2 S Power Density' 1 S3 - We actually see a hybrid approach. Dimensions tend to shrink each new generation. Then the voltages steadily creep in subsequent designs until they are in balance. Then the dimensions will shrink again.  Adv. Mater. 2022, 34, 2106886 10/23/2024 ECC 302, ECE Department, NIT Durgapur 13  What is short channel effect 10/23/2024 ECE Dept, NIT Durgapur 14  VT Roll Off 10/23/2024 ECE Dept, NIT Durgapur 15  VT Roll Off: The Short Channel Effect – Yau’s model 10/23/2024 ECE Dept, NIT Durgapur 16  Drain Induced Barrier Lowering 10/23/2024 ECE Dept, NIT Durgapur 17 10/23/2024 ECE Dept, NIT Durgapur 18  Punchthrough Effect 10/23/2024 ECE Dept, NIT Durgapur 19 10/23/2024 ECE Dept, NIT Durgapur 20 10/23/2024 ECE Dept, NIT Durgapur 21  Hot Carrier Effects Why do we care about hot electron effects? Electron-hole pairs are generated due to energetic carriers in drain depletion region Can be injected into oxide, causing damage / traps – Device degradation – Device reliability Causes substrate leakage current 10/23/2024 ECE Dept, NIT Durgapur 22  The lightly doped drain (LDD) Goal: Minimize Em Method: We know that the peak field in a PN junction is reduced when the doping is reduced, since the same voltage is dropped over a larger depletion width Fabrication: Use a spacer and two self-aligned implants. 10/23/2024 ECE Dept, NIT Durgapur 23  Limits of Scaling Four kinds of limits: Thermodynamics: doping concentration in source and drain Physics: tunneling through gate oxide Statistics: statistical fluctuation of body doping Economics: factory cost 10/23/2024 ECE Dept, NIT Durgapur 24 10/23/2024 ECE Dept, NIT Durgapur 25 Tunneling through gate oxide Below 1.5-2.0 nm, SiO2 or Si-O-N can no longer be used 10/23/2024 ECE Dept, NIT Durgapur 26  New Materials and Structures for Advanced MOSFETs Problem 1: Poor Electrostatics ⇒ increased Ioff Solution: Double Gate - Retain gate control over channel - Minimize OFF-state drain-source leakage Problem 2: Poor Channel Transport ⇒ decreased Ion Solution: High Mobility Channel - High mobility/injection velocity - High drive current and low intrinsic delay Problem 3: S/D Parasitic resistance ⇒ decreased Ion Solution: Metal Schottky S/D - Reduced extrinsic resistance Problem 4: Gate leakage increased Solution: High-K dielectrics - Reduced gate leakage Problem 5:Gate depletion ⇒ increased EOT Solution: Metal gate -High drive current 10/23/2024 27  Gate Leakage:The End of the Road for SiO2? Conventional gate dielectrics: SiO2 A C   0 t ox  : dielectric constant Device scaling Thinner gate dielectrics High leakage current High power consumption  Alternative gate oxide required 10/23/2024 28 Solution: Instead of decreasing the gate 1 W Id   Cox (VGS  VT )2 oxide thickness, increase the dielectric 2 L constant (k) of the gate oxide.  A where C ox  ox ;  ox  k 0 k t ox k is the dielectric constant Low Gate High Leakage Gate Leakage K=4 e- 6.0 nm High-k K=16 1.5 nm SiO2 e- e- Drain  tox J DT  e Source Source e- Drain Channel Channel Si Substrate Si Substrate  0 k SiO A  0 k High k A 2  C ox  t ox t high k Physical thickness: Actual thickness of gate oxide Example: Effective thickness: Equivalent SiO2 thickness HfO2: k=16 k teq: 1.5 nm t phys  teq tphys=6.0 nm 10/23/2024 3.9 ECE Dept, NIT Durgapur 29  High Mobility Channel:Strained Silicon 1 W Mobility in silicon can be enhanced by Id   Cox (VGS  VT )2 2 L straining it. This increases carrier  A mobility in both electrons and holes, where C ox  ox ;  ox  k 0 k t ox due to changes in the energy structure of the conduction / valence sub-bands k is the dielectric constant 10/23/2024 ECE Dept, NIT Durgapur 30 10/23/2024 ECE Dept, NIT Durgapur 31 10/23/2024 ECE Dept, NIT Durgapur 32 10/23/2024 ECE Dept, NIT Durgapur 33  Double‐Gate MOSFET Structures Vertical Planar Fin L. Geppert, IEEE Spectrum, October 2002 10/29/2024 ECC 302, ECE Department, NIT Durgapur 35 10/29/2024 ECC 302, ECE Department, NIT Durgapur 36  Multigate MOSFETs I. Ferain, C. A. Colinge, J.‐P. Colinge, Nature 479, 310–316 (2011) 10/29/2024 ECC 302, ECE Department, NIT Durgapur 37