MOSFET 1 PDF

© Chor EF MOSFET 1 Metal Oxide Semiconductor Field Effect Transistor (MOSFET) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) 1. Introduction 2. Modes of operation: Linear, Saturation and Cut-off 3....

© Chor EF MOSFET 1 Metal Oxide Semiconductor Field Effect Transistor (MOSFET) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) 1. Introduction 2. Modes of operation: Linear, Saturation and Cut-off 3. iD-vDS Relationship of the MOSFET 4. Comparison between MOSFET and BJT 5. Large-Signal Models and dc Analysis 6. Small-Signal Model and ac Analysis 7. Channel Length Modulation 8. Body Effect and Capacitances 9. CMOS Inverter References  Sedra and Smith, Microelectronic Circuits, Theory and Applications, Fifth Edition (International Version), Oxford (2004), pp. 325 – 349, pp. 426-429, pp. 901-921. © Chor EF MOSFET-2 MOSFET – Introduction (Structure)  Schematic on the left shows the basic structure of an n-channel MOSFET, also called an NMOS transistor.  MOSFET is a transistor, performing the same functions as iD BJT: switching and amplification.  An n-channel MOSFET is made using a p-type single-crystal silicon substrate.  Heavily doped n+-type regions, created in the substrate, form the Channel region source and drain regions.  The metal electrode on top of the Basic structure of an n-channel MOSFET. thin oxide (dielectric) layer, between the source and drain regions, is called the gate. © Chor EF MOSFET-3 MOSFET – Introduction (Carrier Flow & Current)  Source, drain and gate of a MOSFET correspond to the emitter, collector and base of a BJT, respectively.  Source terminal is the source of the carriers that will flow through the channel to the drain terminal. iD  In an n-channel MOSFET, electrons (negatively charged carriers) flow from the source to the drain.  Conventional current (iD) therefore enters the drain terminal and flows to the source terminal. Channel region  Note that MOSFET has a fourth terminal - the substrate or body. It Basic structure of an n-channel MOSFET. is typically shorted to the source, (Comparison with BJT in Appendix A) making MOSFET effectively a 3- terminal device. © Chor EF MOSFET-4 MOSFET – Introduction (n-MOSFET vs p-MOSFET) Circuit symbol of Schematic cross-section of MOSFET and Simplified circuit symbol MOSFET operating biases. of MOSFET when body is shorted to source D - vDS + D + - vGS + Gate (G) Source Drain + (S) iD (D) G B vDS Oxide G vDS + n+ n+ + - vGS p-type substrate vGS - - - S S Substrate/Body (B) n-channel MOSFET D + vSD - D - + vSG - Gate (G) Source Drain (S) - iD (D) G B vSD Oxide G vSD - p+ p+ - + vSG n-type substrate vSG + + + S S Substrate/Body (B) p-channel MOSFET © Chor EF MOSFET-5 MOSFET – Introduction (n-MOSFET Vs p-MOSFET)  There are two types of MOSFET: n-channel and p-channel MOSFETs (see their structures and circuit models in previous slide, MOSFET-4)  A p-channel MOSFET, also called a PMOS transistor, is made using an n- type single-crystal silicon substrate, and heavily doped p+-regions form the source and drain regions. Note the differences from n-channel MOSFET.  The n-channel and p-channel MOSFETs are functionally the same. Their difference lies in the biasing polarities of drain-to-source voltage, vDS, and gate-to-source voltage, vGS; and the direction of drain current, iD. They are opposite between n-channel and p-channel MOSFETs for the same mode of operation.  The arrow head in the circuit symbols, which identify the source terminal, indicate the direction of current flow in the MOSFET.  Our discussion will focus on n-channel MOSFET, which applies to p-channel MOSFET except for the differences highlighted above: current direction and biasing voltage polarity. © Chor EF MOSFET 6 Metal Oxide Semiconductor Field Effect Transistor (MOSFET) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) 1. Introduction 2. Modes of operation: Linear, Saturation and Cut-off 3. iD-vDS Relationship of the MOSFET 4. Comparison between MOSFET and BJT 5. Large-Signal Models and dc Analysis 6. Small-Signal Model and ac Analysis 7. Channel Length Modulation 8. Body Effect and Capacitances 9. CMOS Inverter References  Sedra and Smith, Microelectronic Circuits, Theory and Applications, Fifth Edition (International Version), Oxford (2004), pp. 325 – 349, pp. 426-429, pp. 901-921. © Chor EF MOSFET-7 MOSFET – Modes of Operation (n-channel MOSFET) - vDS + Assuming body is shorted to source and both are grounded. - vGS + Gate (G) D Source iG = 0 Drain iD + RD iD RG (S) Oxide (D) G vDS n+ n+ + VDD VGG vGS - p-type substrate - S Substrate/Body (B) Channel region  The main current flow in a MOSFET is between the source and drain, and it is called the drain current, iD.  No current flows through the gate, iG = 0, as it is electrically isolated from the semiconductor substrate by the oxide.  Two back-to-back pn-junctions exist in series between source and drain. One is between the n+-drain region and the p-type substrate, and the other is between the n+-source region and the p-type substrate.  With no vGS applied, the two back-to-back pn-junctions prevent current flow between the source and drain (iD = 0) when a voltage vDS > 0 is applied. © Chor EF MOSFET-8 MOSFET – Modes of Operation (n-channel MOSFET) - vDS + Assuming body is shorted to source and both are grounded. - vGS + Gate (G) D Source >0 iG = 0 Drain iD + RD iD RG (S) Oxide (D) G vDS n+ n+ + VDD VGG vGS - p-type substrate - S Substrate/Body (B) Channel region Depletion Region What happens when vGS > 0 is applied?  Take note that in a p-type semiconductor, there are many holes (positively charge carriers) and they are mainly contributed by p-type impurities that have become ionized. The ionized p-type impurities are fixed negative charges that neutralize the positive charges of holes, thus making the p-type semiconductor overall electrically neutral (see Appendix B).  With vGS > 0 applied, positive voltage at the gate repels holes in the p-type substrate from the region below the gate (the channel region), leaving behind fixed ionised p-type impurities near the surface of the substrate. This produces a region depleted of holes, known as the depletion region (see Appendix C). © Chor EF MOSFET-9 MOSFET – Modes of Operation - vDS + Assuming body is shorted to source and both are grounded. - vGS + Gate (G) D Source >0 iG = 0 Drain iD + RD iD RG (S) Oxide (D) G - - - - - vDS n+ n+ + VDD VGG vGS - p-type substrate - S Electrons Substrate/Body (B) Channel region Depletion Region What happens when vGS > 0 is applied?  The depletion region have only fixed ionised p-type impurities, and it prevents current flow between the source and drain, iD = 0., even with vGS > 0.  At the same time, with vGS > 0 applied, electrons will be attracted from the n+- source and n+-drain into the p-doped channel region.  With increasing vGS > 0, more electrons will be attracted into the channel region, and pile up near the surface of the substrate under the gate. © Chor EF MOSFET-10 MOSFET – Modes of Operation - vDS + Assuming body is shorted to source and both are grounded. - vGS + Gate (G) D Source >0 iG = 0 Drain iD + RD iD RG (S) Oxide (D) G ------------- vDS n+ n+ + VDD VGG vGS - p-type substrate - S Channel of Electrons Substrate/Body (B) formed when vGS ≥ VTH Depletion Region What happens when vGS > 0 is applied?  With high enough vGS, sufficient electrons can be attracted into the channel region and pile up near the surface of p-substrate under the gate to make the surface effectively n-type, connecting the n+-source and n+-drain regions.  The surface of p-substrate is said to be inverted (or a channel is formed), a current iD can flow between the source and drain when vDS > 0 is applied.  The vGS at which the surface of the p-type substrate becomes inverted is known as the threshold voltage, VTH (a parameter of MOSFET with the dimension of voltage). For n-channel MOSFET, VTH > 0. © Chor EF MOSFET-11 MOSFET – Modes of Operation - vDS + Assuming body is shorted to source and both are grounded. - vGS + Gate (G) D Source >0 iG = 0 Drain iD + RD iD RG (S) Oxide (D) G ------------- vDS n+ n+ + VDD VGG vGS - p-type substrate - S Channel of Electrons Substrate/Body (B) formed when vGS ≥ VTH Depletion Region Summary - What happens when vGS > 0 is applied ?  With vGS < VTH, effectively no channel is formed between the source and drain, hence no current flows between them, and iD ≈ 0, even with vDS > 0. MOSFET is said to operate in the cut-off region.  With vGS ≥ VTH, a channel is formed and iD can flow between the source and drain when vDS > 0 is applied. Does iD increases always with increasing vDS? Note: n-channel MOSFET (or NMOS transistor) is so called as the channel that connects the n+-source and n+-drain regions is made up of negatively charged electrons. © Chor EF MOSFET-12 MOSFET – Modes of Operation - vDS + Assuming body is shorted to >0 source and both are grounded. - vGS + Gate (G) D Source ≥ VTH iG = 0 Drain iD + RD iD RG (S) Oxide (D) G ------------ vDS n+ n+ + VDD VGG vGS - p-type substrate - S Substrate/Body (B) Channel depth is not uniform with vDS > 0 With vGS ≥ VTH , what happens when vDS > 0 is applied?  With vGS increasing beyond VTH, more electrons will be induced in the channel. The channel conductivity increases and so does iD for a given vDS.  With a specific vGS ≥ VTH , for small vDS > 0, iD increases with increasing vDS. The MOSFET is said to operate in the linear region.  Take note that the channel depth at the drain end is ‘narrower’ (with fewer electrons) than the source end because the voltage between the gate and the drain (vGS - vDS) is less than that between the gate and the source (vGS). © Chor EF MOSFET-13 MOSFET – Modes of Operation - vDS + Assuming body is shorted to = (vGS - VTH) source and both are grounded. - vGS + Gate (G) D Source ≥ VTH iG = 0 Drain iD + RD iD RG (S) Oxide (D) G --------- vDS n+ n+ + VDD VGG vGS - p-type substrate - S Substrate/Body (B) Channel pinches off at drain end when vDS = (vGS - VTH) With vGS ≥ VTH , what happens when vDS > 0 is applied?  When vDS = (vGS - VTH), the voltage between the gate and the drain end of the channel = vGS - vDS = vGS - (vGS - VTH) = VTH.  Recall that a channel forms under the gate only when vGS > VTH.  Therefore, when vDS = (vGS – VTH), the channel depth at the drain end has reduced to zero. The channel is said to be pinched off at the drain end. © Chor EF MOSFET-14 MOSFET – Modes of Operation - vDS + Assuming body is shorted to > (vGS – VTH) source and both are grounded. - vGS + Gate (G) D Source ≥ VTH iG = 0 Drain iD + RD iD RG (S) Oxide (D) G ------- vDS n+ n+ + VDD VGG vGS - p-type substrate - S Substrate/Body (B) Channel pinch-off point moves towards source end when vDS > (vGS - VTH) With vGS ≥ VTH , what happens when vDS > 0 is applied?  When vDS > (vGS – VTH), the pinch-off point of channel moves towards the source terminal. A high electric field exists in the depletion region near the drain end of the device (between pinch-off point and drain) Electrons drift from the source, through the channel to the pinch-off point, where they are swept by the electric field near the drain into the drain terminal.  Assume the MOSFET has a long channel. This means the shortening of channel as the pinch-off point moves towards source is insignificant compared to the length of channel (see Appendix D). © Chor EF MOSFET-15 MOSFET – Modes of Operation - vDS + Assuming body is shorted to > (vGS – VTH) source and both are grounded. - vGS + Gate (G) D Source ≥ VTH iG = 0 Drain iD + RD iD RG (S) Oxide (D) G ------- vDS n+ n+ + VDD VGG vGS - p-type substrate - S Substrate/Body (B) Channel pinch-off point moves towards source end when vDS > (vGS - VTH) With vGS ≥ VTH , what happens when vDS > 0 is applied?  The channel length and channel charge density, for a given vGS , is therefore not changed significantly for vDS > (vGS – VTH). The drain current iD (due to the drift of electrons through the channel) is then approximately constant.  The drain current iD is then said to be saturated, and the MOSFET is said to operate in the saturation region.  The drain voltage at which current saturation occurs is called the saturation drain voltage, VDSsat = (VGS – VTH). Note that VDSsat is a dc voltage. © Chor EF MOSFET-16 MOSFET - Modes of Operation  The relationships between the drain current, iD, and the drain-to-source voltage, vDS, for different gate-to-source voltages, vGS, of an n-channel MOSFET are shown in the plot below.  The regions corresponding to the cut-off, linear and saturation modes of operation are as indicated in the plot below. Linear region - iD depends on both vDS and vGS, i.e., iD = f (vDS ,vGS) Saturation region - iD is independent on vDS and is a function of only vGS, i.e., iD = f (vGS) For any vGS, the linear and saturation regions are separated by 𝑣𝑣𝐷𝐷𝐷𝐷 = 𝑉𝑉𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 = 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇. 𝑉𝑉𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 = 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 D 𝑣𝑣𝐷𝐷𝐷𝐷 < 𝑉𝑉𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 𝑣𝑣𝐷𝐷𝐷𝐷 > 𝑉𝑉𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 iD + RD RG G vDS + VDD VGG vGS - - S Cut-off region: vGS < VTH, iD ≈ 0 Note : Do not confuse the saturation region of operation of the MOSFET with that of the BJT. See Appendix E. © Chor EF MOSFET-17 MOSFET - Modes of Operation The operation of MOSFET and the phenomenon of saturation of the drain current can be likened, albeit imperfectly, to a water analogy, as shown below. (a) The water depth in the canal (channel) can be varied by the gear and track (vGS). When the source and drain are level (vDS = 0) there is no flow, despite the presence of a water vGS > VTH & vDS = 0 channel (vGS > VTH). (b ) When the drain is lower than the source (vDSsat > vDS > 0), and a water channel exists between them due to the “bias” by the gear and track (vGS > VTH), vGS > VTH & vDSsat > vDS > 0 water flows along the channel. This corresponds to the linear region of operation of the MOSFET. © Chor EF MOSFET-18 MOSFET - Modes of Operation (c) The water flow is limited by the channel capacity. When the drain end of canal has been lowered to its lowest point, the limit is reached, and the rate of flow cannot be increased further. This vGS > VTH & vDS = vDSsat corresponds to vDS = vDSsat. (d) Lowering the drain further (increasing vDS beyond vDSsat) only increases the height of the waterfall at its edge, but does not increase the rate of flow of water in the channel. This corresponds to the saturation region of vGS > VTH & vDS > vDSsat operation of the MOSFET. © Chor EF MOSFET-19 MOSFET - Modes of Operation - vDS + Assuming body is shorted to source and both are grounded. - vGS + Gate (G) D Source iG = 0 Drain iD + RD iD RG (S) Oxide (D) G vDS n+ n+ + VDD VGG vGS - p-type substrate - S Substrate/Body (B) Channel region Modes of operation of the n-channel MOSFET Mode of Gate-to-Source Drain-to-Source Drain Current Applications Operation Bias (vGS > 0) Bias (vDS > 0) (iD – into Drain) Cut-off vGS < VTH N.A. iD = 0 CMOS Logic – OFF state Linear vGS ≥ VTH vDS ≤ vGS – VTH iD = f (vDS ,vGS) CMOS Logic – ON state Saturation vGS ≥ VTH vDS ≥ vGS - VTH iD = f (vGS) Amplifier * A similar table for p-channel MOSFET is shown in the Appendix F. © Chor EF MOSFET 20 Metal Oxide Semiconductor Field Effect Transistor (MOSFET) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) 1. Introduction 2. Modes of operation: Linear, Saturation and Cut-off 3. iD-vDS Relationship of the MOSFET 4. Comparison between MOSFET and BJT 5. Large-Signal Models and dc Analysis 6. Small-Signal Model and ac Analysis 7. Channel-Length Modulation 8. Body Effect and Capacitances 9. CMOS Inverter References  Sedra and Smith, Microelectronic Circuits, Theory and Applications, Fifth Edition (International Version), Oxford (2004), pp. 325 – 349, pp. 426-429, pp. 901-921. © Chor EF MOSFET-21 MOSFET - iD-vDS Relationship Consider an n-channel MOSFET and for 𝑣𝑣𝐺𝐺𝑆𝑆 ≥ 𝑉𝑉𝑇𝑇𝑇𝑇 -  In linear region, 𝑣𝑣𝐷𝐷𝐷𝐷 ≤ 𝑣𝑣𝐷𝐷𝐷𝐷𝑠𝑠𝑠𝑠𝑠𝑠 = 𝑣𝑣𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 and 𝑖𝑖𝐷𝐷 = 𝑓𝑓 𝑣𝑣𝐷𝐷𝐷𝐷 , 𝑣𝑣𝐺𝐺𝑆𝑆 - 𝑊𝑊 2 1 𝑖𝑖𝐷𝐷 = 𝜇𝜇𝑛𝑛 𝐶𝐶 𝑣𝑣𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 𝑣𝑣𝐷𝐷𝐷𝐷 − 𝑣𝑣𝐷𝐷𝐷𝐷 *, (4.1) 𝐿𝐿 𝑜𝑜𝑜𝑜 2  In saturation region, 𝑣𝑣𝐷𝐷𝐷𝐷 ≥ 𝑣𝑣𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 = 𝑣𝑣𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 and 𝑖𝑖𝐷𝐷 = 𝑓𝑓 𝑣𝑣𝐺𝐺𝐺𝐺 - 1 𝑊𝑊 2 𝑖𝑖𝐷𝐷 = 𝑖𝑖𝐷𝐷𝑠𝑠𝑠𝑠𝑠𝑠 = 𝜇𝜇𝑛𝑛 𝐶𝐶 𝑣𝑣𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 (4.2) 2 𝐿𝐿 𝑜𝑜𝑜𝑜  For any 𝑣𝑣𝐺𝐺𝐺𝐺 , the linear and saturation regions are separated by - 𝑣𝑣𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 = 𝑣𝑣𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 (4.3) 𝑉𝑉𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 = 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 D 𝑣𝑣𝐷𝐷𝐷𝐷 < 𝑉𝑉𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 𝑣𝑣𝐷𝐷𝐷𝐷 > 𝑉𝑉𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 iD + RD RG G vDS + VDD VGG vGS - - S Cut-off region, iD ≈ 0 * Equation (4.1) is not valid for 𝑣𝑣𝐷𝐷𝐷𝐷 > 𝑣𝑣𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 = 𝑣𝑣𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 © Chor EF MOSFET-22 MOSFET - iD-vDS Relationship  𝜇𝜇𝑛𝑛 is the mobility of the electrons in the channel between the source and drain, 𝑊𝑊 is the width of the channel, 𝐿𝐿 is the length of the channel and 𝐶𝐶𝑜𝑜𝑜𝑜 is the gate oxide capacitance per unit area – 𝜀𝜀𝑜𝑜𝑜𝑜 𝜀𝜀𝑟𝑟,𝑜𝑜𝑜𝑜 𝜀𝜀𝑜𝑜 𝐶𝐶𝑜𝑜𝑜𝑜 = = , (4.4) 𝑡𝑡𝑜𝑜𝑜𝑜 𝑡𝑡𝑜𝑜𝑜𝑜 where 𝑡𝑡𝑜𝑜𝑜𝑜 is the thickness of the oxide, 𝜀𝜀𝑜𝑜𝑜𝑜 is the permittivity of the oxide, 𝜀𝜀𝑟𝑟,𝑜𝑜𝑜𝑜 is the dielectric constant (or relative permittivity) of oxide and is equal to 3.9 for silicon dioxide, and 𝜀𝜀𝑜𝑜 = 8.854×10-14 F cm-1 is the permittivity of free space.  Defining the conductance parameter, 𝐾𝐾𝑛𝑛 , as 1 𝑊𝑊 𝐾𝐾𝑛𝑛 = 𝜇𝜇𝑛𝑛 𝐶𝐶 (4.6) 2 𝐿𝐿 𝑜𝑜𝑜𝑜  Equations (4.1) and (4.2) can be re-written respectively as 2 1 𝑖𝑖𝐷𝐷 = 2𝐾𝐾𝑛𝑛 𝑣𝑣𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 𝑣𝑣𝐷𝐷𝐷𝐷 − 𝑣𝑣𝐷𝐷𝐷𝐷 , (4.7) 2 2 and 𝑖𝑖𝐷𝐷 = 𝑖𝑖𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 = 𝐾𝐾𝑛𝑛 𝑣𝑣𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 (4.8) © Chor EF MOSFET-23 MOSFET - iD-vDS Relationship (p-MOSFET)  For a p-channel MOSFET, 𝑣𝑣𝐷𝐷𝐷𝐷 , 𝑣𝑣𝐺𝐺𝐺𝐺 and 𝑉𝑉𝑇𝑇𝑇𝑇 are all negative.  For 𝑣𝑣𝑆𝑆𝐺𝐺 = 𝑣𝑣𝐺𝐺𝐺𝐺 ≥ 𝑉𝑉𝑇𝑇𝑇𝑇 , positively charged holes form the channel, allowing holes to flow from the source to the drain, and the drain current, 𝑖𝑖𝐷𝐷 , flows out of the drain terminal (see Appendix G). D  To maintain the same notation and sign as an n-channel iD - MOSFET, we shall express the 𝑖𝑖𝐷𝐷 − 𝑣𝑣𝐷𝐷𝐷𝐷 equations for the p-channel MOSFET in terms of absolute values - G vSD In linear region, 𝑣𝑣𝐷𝐷𝐷𝐷 ≤ 𝑣𝑣𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 - - 𝑖𝑖𝐷𝐷 = 2𝐾𝐾𝑝𝑝 𝑣𝑣𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 𝑣𝑣𝐷𝐷𝐷𝐷 − 1 𝑣𝑣𝐷𝐷𝐷𝐷 2 , (4.9) vSG + 2 + S In saturation region, 𝑣𝑣𝐷𝐷𝐷𝐷 ≥ 𝑣𝑣𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 - + vSD - 2 𝑖𝑖𝐷𝐷 = 𝐾𝐾𝑝𝑝 𝑣𝑣𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 (4.10) + vSG - Gate (G) Source  Conductance parameter: Drain (S) iD Oxide (D) 1 𝑊𝑊 𝐾𝐾𝑝𝑝 = 𝜇𝜇𝑝𝑝 𝐶𝐶𝑜𝑜𝑜𝑜 (4.11) p+ p+ 2 𝐿𝐿 n-type substrate  𝜇𝜇𝑝𝑝 is the mobility of the holes in the channel between the source and drain. Substrate/Body (B) © Chor EF MOSFET 24 Metal Oxide Semiconductor Field Effect Transistor (MOSFET) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) 1. Introduction 2. Modes of operation: Linear, Saturation and Cut-off 3. iD-vDS Relationship of the MOSFET 4. Comparison between MOSFET and BJT 5. Large-Signal Models and dc Analysis 6. Small-Signal Model and ac Analysis 7. Channel-Length Modulation 8. Body Effect and Capacitances 9. CMOS Inverter References  Sedra and Smith, Microelectronic Circuits, Theory and Applications, Fifth Edition (International Version), Oxford (2004), pp. 325 – 349, pp. 426-429, pp. 901-921. © Chor EF MOSFET-25 MOSFET - Comparison between MOSFET and BJT A MOSFET is a four terminal device while a BJT is a three terminal device. Both of them can be used as logic switches or as amplifiers. The comparison table below sets out some of the differences. Feature Bipolar Junction Transistor MOSFET Terminals Emitter Source Base Gate Collector Drain Substrate/Body Mode of operation in Forward active Saturation amplifiers Modes of operation in Cut-off for logic ‘OFF’ Cut-off for logic ‘OFF’ logic switches Saturation for logic ‘ON’ Linear for logic ‘ON’ Main Applications High frequency, high speed, Logic, memory, mixed high power circuits signal circuits, low power and VLSI circuits © Chor EF MOSFET 26 Metal Oxide Semiconductor Field Effect Transistor (MOSFET) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) 1. Introduction 2. Modes of operation: Linear, Saturation and Cut-off 3. iD-vDS Relationship of the MOSFET 4. Comparison between MOSFET and BJT 5. Large-Signal Models and dc Analysis 6. Small-Signal Model and ac Analysis 7. Channel-Length Modulation 8. Body Effect and Capacitances 9. CMOS Inverter References  Sedra and Smith, Microelectronic Circuits, Theory and Applications, Fifth Edition (International Version), Oxford (2004), pp. 325 – 349, pp. 426-429, pp. 901-921. © Chor EF MOSFET-27 MOSFET – Large-Signal Model (Saturation Region)  For an n-channel MOSFET in the saturation region – 𝑣𝑣𝐺𝐺𝑆𝑆 > 𝑉𝑉𝑇𝑇𝑇𝑇 and 𝑣𝑣𝐷𝐷𝐷𝐷 ≥ 𝑣𝑣𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 = 𝑣𝑣𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 *  From equation (4.8), we have, under dc condition - 2 𝐼𝐼𝐷𝐷 = 𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 = 𝐾𝐾𝑛𝑛 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 a dependent current source  As there is no gate current – 𝐼𝐼𝐺𝐺 = 0 an open circuit D IG = 0 ID G D ID + + IG = 0 + VGS VDS Kn (VGS - VTH)2 G VDS - - + - is equivalent to VGS IS - IS S S * (vGS – VTH) is also known as the Gate-Overdrive, and it is also the minimum vDS to keep the MOSFET in the saturation region. © Chor EF MOSFET-28 MOSFET – Large-Signal Model (Linear Region)  For an n-channel MOSFET in the linear region – 𝑣𝑣𝐺𝐺𝑆𝑆 > 𝑉𝑉𝑇𝑇𝑇𝑇 and 𝑣𝑣𝐷𝐷𝐷𝐷 < 𝑣𝑣𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 = 𝑣𝑣𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇.  From equation (4.7), we have, under dc condition - 2 1 𝐼𝐼𝐷𝐷 = 2𝐾𝐾𝑛𝑛 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 𝑉𝑉𝐷𝐷𝐷𝐷 − 𝑉𝑉𝐷𝐷𝐷𝐷 2 1 2  For small 𝑉𝑉𝐷𝐷𝐷𝐷 , we neglect 𝑉𝑉 , 2 𝐷𝐷𝐷𝐷 𝐼𝐼𝐷𝐷 ≈ 2𝐾𝐾𝑛𝑛 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 𝑉𝑉𝐷𝐷𝐷𝐷 a resistance between source and drain  Drain-to-source resistance for small 𝑉𝑉𝐷𝐷𝐷𝐷 is 𝑉𝑉𝐷𝐷𝐷𝐷 𝑅𝑅𝐷𝐷𝑆𝑆 = | 𝐼𝐼𝐷𝐷 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 𝑉𝑉𝐷𝐷𝐷𝐷 ≈ 1/ 2𝐾𝐾𝑛𝑛 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 D ID G D ID + + IG = 0 + For small 𝑽𝑽𝑫𝑫𝑫𝑫 IG = 0 VGS VDS RDS = 1/[2Kn(VGS - VTH)] G VDS + - - - is equivalent to VGS IS - IS S S © Chor EF MOSFET-29 MOSFET – Large-Signal Models (p-MOSFET)  In the saturation region: 𝑣𝑣𝐺𝐺𝐺𝐺 > 𝑉𝑉𝑇𝑇𝑇𝑇 and 𝑣𝑣𝐷𝐷𝐷𝐷 ≥ 𝑣𝑣𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 and under dc condition - S S + IS VSG IS VTH for P-MOSFET G - is negative. + IG = 0 is equivalent to VSG ID Kp (|VGS| - |VTH|)2 G - D D IG = 0 ID  In the linear region: 𝑣𝑣𝐺𝐺𝐺𝐺 > 𝑉𝑉𝑇𝑇𝑇𝑇 and 𝑣𝑣𝐷𝐷𝐷𝐷 ≤ 𝑣𝑣𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 and under dc condition (for small 𝑣𝑣𝐷𝐷𝐷𝐷 ) - S S + IS IS VSG G - + is equivalent to RDS = VSG IG = 0 1/[2Kp(|VGS| - |VTH|)] ID G - D IG = 0 ID D © Chor EF MOSFET-30 MOSFET – Calculation of Bias Point (dc Analysis) Example 1 (Thevenin equivalent method) Find the current ID and the voltage VD. Assume that µnCox = 2.0 ×10-5 A/V2, W/L = 5, and VTH = 1 V. VDD  First, we obtain the Thevenin equivalent 10 V 10 V circuit of the gate-biasing circuit shown in the dashed box (gray): RD R1 5 kΩ 5 kΩ ID D IG RTHV = G VTHV + R1//R2 = =5V - 2.5 kΩ Note that the voltage S divider method can also R2 5 kΩ be used to find the IS voltage at the node G as the gate current IG = 0. 5kΩ / (5kΩ+5kΩ ) × 10V Gate-biasing circuit © Chor EF MOSFET-31 MOSFET – Calculation of Bias Point Example 1 (Thevenin equivalent method) 10 V  Next, we assume the MOSFET is in saturation (needs to check later) and Note that the voltage at the RD replace it with the corresponding gate VG is 5 V, as IG = 0. 5 kΩ large-signal model. IG = 0 ID D  We see that 𝑉𝑉𝐺𝐺𝐺𝐺 = 𝑉𝑉𝑇𝑇𝑇𝑇𝑇𝑇 = 5 V (> 𝑉𝑉𝑇𝑇𝑇𝑇 ) VTHV G +  Substitute VGS and other given =5V RTHV = + R1//R2 = VGS parameters into the equation for 𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 : - 2.5 kΩ - Kn(VGS-VTH)2 1 𝑊𝑊 2 𝐼𝐼𝐷𝐷 = 𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 = 2 𝜇𝜇𝑛𝑛 𝐶𝐶𝑜𝑜𝑜𝑜 𝐿𝐿 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 IS = ID 2 S = 0.5 × 2.0 × 10−5 × 5 × (5 − 1) = 0.8 mA  Hence, 𝑉𝑉𝐷𝐷 = 10 V − 𝐼𝐼𝐷𝐷 𝑅𝑅𝐷𝐷 = 6 V  Check if MOSFET is indeed in Large Signal Model for N-MOSFET in Saturation saturation: o 𝑉𝑉𝐺𝐺𝐺𝐺 = 5 V > 𝑉𝑉𝑇𝑇𝑇𝑇 = 1 V o 𝑉𝑉𝐷𝐷𝑆𝑆 = 6 V > 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 = 4 V.  Yes. © Chor EF MOSFET-32 MOSFET – Calculation of Bias Point Example 2 (Voltage Divider method) A 5 kΩ resistance is connected between the N-MOSFET source and ground of the circuit of Example 1. Determine the values of ID and VD. VDD = 10 V  By means of voltage divider, 𝑉𝑉𝐺𝐺 = 5 V. RD  𝑉𝑉𝐺𝐺𝐺𝐺 = 𝑉𝑉𝐺𝐺 − 𝑉𝑉𝑆𝑆. What is 𝑉𝑉𝑆𝑆 ? R1 5 kΩ 5 kΩ  𝑉𝑉𝑆𝑆 = 𝐼𝐼𝑆𝑆 𝑅𝑅𝑆𝑆 = 𝐼𝐼𝐷𝐷 𝑅𝑅𝑆𝑆 , which depends on the solution ID for 𝐼𝐼𝐷𝐷. D IG  We assume the MOSFET is in saturation G (needs to check later) and replace it with the corresponding large signal model. R2 IS = ID S 5 kΩ  Examine the equation for 𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 : RS 1 𝑊𝑊 2 5 kΩ 𝐼𝐼𝐷𝐷 = 𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 = 2 𝜇𝜇𝑛𝑛 𝐶𝐶𝑜𝑜𝑜𝑜 𝐿𝐿 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 −5 = 0.5 × 2.0 × 10 A/V 2 × 5 2 × (𝑉𝑉𝐺𝐺 − 𝑉𝑉𝑆𝑆 − 𝑉𝑉𝑇𝑇𝑇𝑇 ) © Chor EF MOSFET-33 MOSFET – Calculation of Bias Point Example 2 (Voltage Divider method) 1 𝑊𝑊 2 10 V 10 V  𝐼𝐼𝐷𝐷 = 𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 = 𝜇𝜇𝑛𝑛 𝐶𝐶𝑜𝑜𝑜𝑜 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 2 𝐿𝐿 Note that the −2 voltage at the = 0.5 × 2.0 × 10 mA/V 2 × 5 R1 gate VG is 5 V, as RD 2 IG = 0. 5 kΩ × (𝑉𝑉𝐺𝐺 − 𝑉𝑉𝑆𝑆 − 𝑉𝑉𝑇𝑇𝑇𝑇 ) 5 kΩ 2 ID  𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 = 0.05 5 − 𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 5 − 1 IG = 0 𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 in mA D RS in kΩ G +  Solving the above quadratic equation, VGS R2 𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 = 2.09 mA or 0.31 mA. 5 kΩ - Kn(VGS-VTH)2 IS = ID  Check: 𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 = 2.09 mA cannot be a S solution as this leads to 𝑉𝑉𝑆𝑆 > 10 V. RS 5 kΩ  Therefore, IDsat = 0.31 mA. In this case, 𝑉𝑉𝐷𝐷 = 8.45 V, 𝑉𝑉𝑆𝑆 = 1.55 V, Large-Signal Model for N-MOSFET in Saturation 𝑉𝑉𝐷𝐷𝑆𝑆 = 6.9 V, 𝑉𝑉𝐺𝐺𝑆𝑆 = 3.45 V.  Check that MOSFET is indeed in saturation: 𝑉𝑉𝐺𝐺𝐺𝐺 = 3.45 V > 𝑉𝑉𝑇𝑇𝑇𝑇 = 1 V & 𝑉𝑉𝐷𝐷𝐷𝐷 = 6.9 V > 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 = 2.45 V. © Chor EF MOSFET 34 Metal Oxide Semiconductor Field Effect Transistor (MOSFET) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) 1. Introduction 2. Modes of operation: Linear, Saturation and Cut-off 3. iD-vDS Relationship of the MOSFET 4. Comparison between MOSFET and BJT 5. Large-Signal Model and dc Analysis 6. Small-Signal Models and ac Analysis 7. Channel-Length Modulation 8. Body Effect and Capacitances 9. CMOS Inverter References  Sedra and Smith, Microelectronic Circuits, Theory and Applications, Fifth Edition (International Version), Oxford (2004), pp. 325 – 349, pp. 426-429, pp. 901-921. © Chor EF MOSFET-35 MOSFET – Small-Signal Model  Interested in the small-signal model of MOSFET in saturation operation.  In developing the small-signal model of MOSFET, we seek a set of linear relationships among the small-signal components of the drain current, gate-to- source voltage and drain-to-source voltage - id, vgs and vds (at a bias point).  If the body (substrate) is not tied to the source, then a voltage applied to the body (w.r.t. to source) will affect the current in the MOSFET. This will be dealt with in Section 8. D NMOS D is equivalent to G B + id vds S ig = 0 G + ??? B PMOS S vgs B is equivalent to - S - iG = 0 as the gate is separated from the drain, source and body by an insulator. D © Chor EF MOSFET-36 MOSFET – Small-Signal Model (Transconductance gm)  From equation (4.8), drain current in saturation – iD 𝑖𝑖𝐷𝐷 = 𝑖𝑖𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 = 𝐾𝐾𝑛𝑛 𝑣𝑣𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 2 Small change Gradient at Q =  At the bias point, dc drain current – in drain current. 𝜕𝜕𝑖𝑖𝐷𝐷 | = 𝑔𝑔𝑚𝑚 𝐼𝐼𝐷𝐷 = 𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 = 𝐾𝐾𝑛𝑛 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 2 𝜕𝜕𝑣𝑣𝐺𝐺𝐺𝐺 𝑉𝑉𝐺𝐺𝑆𝑆 I D + id id  A linear relationships between a small change in ID Bias Point Q the drain current, 𝑖𝑖𝑑𝑑 , and a small change in gate- to-source voltage, 𝑣𝑣𝑔𝑔𝑔𝑔 , can be found by linearizing Small change in gate-to the 𝑖𝑖𝐷𝐷 -𝑣𝑣𝐺𝐺𝐺𝐺 characteristic. source voltage. vgs  A small change in 𝑖𝑖𝐷𝐷 w.r.t a small change in 𝑣𝑣𝐺𝐺𝐺𝐺 , can vGS VTH VGS be approximated by the derivative of 𝑖𝑖𝐷𝐷 w.r.t 𝑣𝑣𝐺𝐺𝐺𝐺 – 𝑖𝑖𝑑𝑑 𝜕𝜕𝑖𝑖 | ≈ 𝜕𝜕𝑣𝑣 𝐷𝐷 |𝑉𝑉𝐺𝐺𝐺𝐺 = 2𝐾𝐾𝑛𝑛 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 = 𝑔𝑔𝑚𝑚 (4.12) 𝑣𝑣𝑔𝑔𝑔𝑔 𝑉𝑉𝐺𝐺𝐺𝐺 𝐺𝐺𝐺𝐺  Transconductance (for n-channel MOSFET): 𝑖𝑖 𝑔𝑔𝑚𝑚 = 𝑣𝑣 𝑑𝑑 = 2𝐾𝐾𝑛𝑛 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 = 2 𝐾𝐾𝑛𝑛 𝐼𝐼𝐷𝐷 = 2𝐼𝐼𝐷𝐷 / 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 (4.13) 𝑔𝑔𝑔𝑔 © Chor EF MOSFET-37 MOSFET – Small-Signal Model (Transconductance gm)  Transconductance (for n-channel MOSFET): 𝑖𝑖 𝑔𝑔𝑚𝑚 = 𝑑𝑑 = 2𝐾𝐾𝑛𝑛 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 = 2 𝐾𝐾𝑛𝑛 𝐼𝐼𝐷𝐷 = 2𝐼𝐼𝐷𝐷 / 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 (4.13) 𝑣𝑣 𝑔𝑔𝑔𝑔 Transconductance, 𝑔𝑔𝑚𝑚 , models a small change in the drain current, 𝑖𝑖𝑑𝑑 , caused by a small change in gate-to-source voltage, 𝑣𝑣𝑔𝑔𝑔𝑔 - 𝑖𝑖𝑑𝑑 = 𝑔𝑔𝑚𝑚 𝑣𝑣𝑔𝑔𝑔𝑔 (4.14) Small change Small change in gate- in drain current. to-source voltage 2 2  For p-channel MOSFET: 𝑖𝑖𝐷𝐷 = 𝐾𝐾𝑝𝑝 𝑣𝑣𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 = 𝐾𝐾𝑝𝑝 𝑣𝑣𝑆𝑆𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 𝑖𝑖 𝜕𝜕𝑖𝑖 𝑔𝑔𝑚𝑚 = 𝑣𝑣 𝑑𝑑 = 𝜕𝜕𝑣𝑣 𝐷𝐷 |𝑉𝑉𝑆𝑆𝐺𝐺 = 2𝐾𝐾𝑝𝑝 𝑉𝑉𝑆𝑆𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 = 2𝐾𝐾𝑝𝑝 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 (4.15) 𝑠𝑠𝑔𝑔 𝑆𝑆𝐺𝐺 Transconductance, 𝑔𝑔𝑚𝑚 , models a small change in the drain current, 𝑖𝑖𝑑𝑑 , caused by a small change in source-to-gate voltage, 𝑣𝑣𝑠𝑠𝑔𝑔 - 𝑖𝑖𝑑𝑑 = 𝑔𝑔𝑚𝑚 𝑣𝑣𝑠𝑠𝑔𝑔 (4.16) Small change Small change in source- in drain current. to-gate voltage © Chor EF MOSFET-38 MOSFET – Small-Signal Model  Small-signal model of n-channel MOSFET is developed using equation (4.13).  Note that iG = IG + ig = 0 since no current flows into the gate of the MOSFET, i.e. IG = 0 and ig = 0. No current flows into the gate, hence 𝑖𝑖𝐺𝐺 = 𝐼𝐼𝐺𝐺 + 𝑖𝑖𝑔𝑔 = 0, 𝐼𝐼𝐺𝐺 = 0, and 𝑖𝑖𝑔𝑔 = 0 – an open circuit. D ig = 0 id G D iD + + iG = 0 + vgs vds gmvgs G vDS - - + - is equivalent to vGS iS - is S S Eqn. (4.12): 𝑖𝑖𝑑𝑑 = 𝑔𝑔𝑚𝑚 𝑣𝑣𝑔𝑔𝑔𝑔 - value of id is dependent on vgs – modeled by a voltage- dependent current source. © Chor EF MOSFET-39 MOSFET – Large- & Small-Signal Saturation Mode Models Replace Large-Signal Model of n-MOSFET MOSFET IG = 0 ID by large - G D signal + + model for VGS VDS dc analysis - - D IS Kn [VGS - VTH]2 iD S iG + G vDS + - Small-Signal Model of n-MOSFET vGS iS id - ig = 0 G D S + + Replace vgs vds MOSFET - by small - - signal gmvgs is model for S ac analysis © Chor EF MOSFET-40 MOSFET – Amplifier Circuit Operation and Analysis  A simple MOSFET amplifier circuit is shown below.  The dc voltage sources, VDD and VGG are used to set the dc bias point, and an ac (small signal) source, vs, is applied to the input circuit (involving the gate and source of MOSFET).  Two types of operation: dc and ac operations.  The dc bias point can be determined using the saturation mode large-signal model, and in the absence of the ac (small signal) source, vs. N-MOSFET Parameters VDD = 10 V VDD = 10 V DC Analysis VTH = 1 V In the absence of small signal, we µnCox = 2.0×10-5 A/V2 RD RD consider only the DC component, W/L = 5 iD 5 kΩ i.e., we look at a case where vs = 0. 5 kΩ Kn = 5×10-5 A/V2 D IG = 0 ID RG iG RG D G Kn(VGS-VTH)2 G + vs S VGG + VGS =5V - - VGG + iD ID =5V - S Large-Signal Model for N-MOSFET in Saturation © Chor EF MOSFET-41 MOSFET – Amplifier Circuit (dc analysis)  Assume MOSFET operates in saturation region (need to check later).  We see that 𝑉𝑉𝐺𝐺𝐺𝐺 = 𝑉𝑉𝐺𝐺𝐺𝐺 = 5 V (as 𝐼𝐼𝐺𝐺 = 0), which can be substituted into the equation for 𝐼𝐼𝐷𝐷 = 𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 - 1 𝑊𝑊 2 𝐼𝐼𝐷𝐷 = 𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 = 𝜇𝜇𝑛𝑛 𝐶𝐶𝑜𝑜𝑜𝑜 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 = 0.8 mA 2 𝐿𝐿  From output circuit load line equation: 𝑉𝑉𝐷𝐷𝑆𝑆 = 𝑉𝑉𝐷𝐷𝐷𝐷 − 𝐼𝐼𝐷𝐷 𝑅𝑅𝐷𝐷 = 6 V.  Check: 𝑉𝑉𝐺𝐺𝑆𝑆 > 𝑉𝑉𝑇𝑇𝑇𝑇 & 𝑉𝑉𝐷𝐷𝐷𝐷 > 𝑉𝑉𝐺𝐺𝑆𝑆 − 𝑉𝑉𝑇𝑇𝑇𝑇 = 4 V, MOSFET operates in saturation. N-MOSFET Parameters VDD = 10 V VDD = 10 V DC Analysis VTH = 1 V In the absence of small signal, we µnCox = 2.0×10-5 A/V2 RD RD consider only the DC component, W/L = 5 iD 5 kΩ i.e., we look at a case where vs = 0. 5 kΩ Kn = 5×10-5 A/V2 D IG = 0 ID RG iG RG D G Kn(VGS-VTH)2 G + vs S VGG + VGS =5V - - VGG + iD ID =5V - S Large-Signal Model for N-MOSFET in Saturation © Chor EF MOSFET-42 MOSFET – Amplifier Circuit (dc vs ac operation)  The dc bias point on the 𝑖𝑖𝐷𝐷 -𝑣𝑣𝐺𝐺𝐺𝐺 and 𝑖𝑖𝐷𝐷 -𝑣𝑣𝐷𝐷𝑆𝑆 curves are shown below.  In the presence of an ac (small signal) source, vs, -  𝑖𝑖𝐷𝐷 = 𝐼𝐼𝐷𝐷 + 𝑖𝑖𝑑𝑑 , 𝑣𝑣𝐺𝐺𝐺𝐺 = 𝑉𝑉𝐺𝐺𝐺𝐺 + 𝑣𝑣𝑔𝑔𝑔𝑔 , and 𝑣𝑣𝐷𝐷𝑆𝑆 = 𝑉𝑉𝐷𝐷𝑆𝑆 + 𝑣𝑣𝑑𝑑𝑠𝑠 𝑖𝑖𝐷𝐷 , 𝑣𝑣𝐺𝐺𝐺𝐺 and 𝑣𝑣𝐷𝐷𝐷𝐷 all have a small signal component and they vary with time. iD iD 𝐼𝐼𝐷𝐷 = 𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 Saturation 2 = 𝐾𝐾𝑛𝑛 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 Linear I D + id vG = VGS + vgs id ID id Bias Point ID Bias Point vG = VGS = 5 V = 0.8 mA Load line vgs vGS vDS VTH VGS = 5 V VDS= 6 V VDS + vds Small-signal voltage vgs varies with Load line equation: 𝑣𝑣𝐷𝐷𝐷𝐷 = 𝑉𝑉𝐷𝐷𝐷𝐷 − 𝑖𝑖𝐷𝐷 𝑅𝑅𝐷𝐷 time. It contains information to be Rearranging, we have 𝑖𝑖𝐷𝐷 = 𝑉𝑉𝐷𝐷𝐷𝐷 − 𝑣𝑣𝐷𝐷𝑆𝑆 /𝑅𝑅𝐷𝐷 amplified. = (10V – vDS)/5 kΩ = 2 mA – (vDS/5kΩ) © Chor EF MOSFET-43 MOSFET – Amplifier Circuit (ac analysis) In the presence of small- signal, we consider both the 10 V Small-Signal Equivalent Circuit DC component and the time- varying ac component. RD What is the change in voltage at this point? 5 kΩ 10 V is a constant voltage supply which does not vary with time. Answer: 0 V. This is an ac short. I D + id IG + ig= 0 D G Kn(VGS-VTH)2 + id + Replace MOSFET by small-signal model for RD vs VGS + vgs id ac analysis 5 kΩ - D + I D + id ig= 0 vd - S vs G Large-signal Model for + N-MOSFET in Saturation vgs - gmvgs ac S.C. S  Small-signal (ac) analysis using the id small-signal equivalent circuit - 𝑣𝑣𝑑𝑑 = 0 − 𝑖𝑖𝑑𝑑 𝑅𝑅𝐷𝐷 = −𝑔𝑔𝑚𝑚 𝑣𝑣𝑔𝑔𝑔𝑔 𝑅𝑅𝐷𝐷 Eqn. (4.13): 𝑔𝑔𝑚𝑚 = 2𝐾𝐾𝑛𝑛 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 = 2 2 × 10−5 A/V 5 − 1 = 4 × 10−4 A/V 𝑣𝑣 Hence, 𝑣𝑣 𝑑𝑑 = −𝑔𝑔𝑚𝑚 𝑅𝑅𝐷𝐷 = − 4 × 10−4 A/V × 5kΩ = −2 𝑔𝑔𝑔𝑔 © Chor EF MOSFET-44 MOSFET – Interpretation of Small-Signal Analysis Results  The small-signal equivalent circuit shown in the previous slide can be re-drawn as - id D ig= 0 G vd We found that vd = -(gmRD)vgs + + RD For vd = -2vgs it means that vs vgs 5 kΩ when the change in gate- source voltage is +25 mV, then - S gmvgs S - the change in the drain-source voltage is -50 mV. vgs and vd vd 25 mV vgs 0V Time t -50 mV © Chor EF MOSFET-45 MOSFET – Small-Signal Model (p-MOSFET) N-MOSFET The change in drain current for P-MOSFET the N-MOSFET is positive when there is an increase in the Drain D D ID+id + current flowing into the drain - I D + id id = gmvgs The Change in drain G VDS + vds G - VSD + vsd current for the P-MOSFET is positive when there is + VSG + vsg an increase in the Drain VGS + vgs Replace the MOSFET + current flowing out of the drain by this Hybrid-π Model - S - for Small-Signal S + Analysis id = gmvsg Hybrid-π Model for N-MOSFET or P-MOSFET G id D + vgs gmvgs This Hybrid-π Model is in its - simplest form here. We will use this simplest form by default. id S © Chor EF MOSFET-46 MOSFET – Small-Signal Model (p-MOSFET) P-MOSFET G id D D - I D + id vsg gmvsg G - + VSG + vsg + S S G id D G id D + + vgs gmvgs vgs -gmvgs - - There is no difference between the S small-signal models of N-MOSFET S and PMOSFET © Chor EF MOSFET 47 Metal Oxide Semiconductor Field Effect Transistor (MOSFET) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) 1. Introduction 2. Modes of operation: Linear, Saturation and Cut-off 3. iD-vDS Relationship of the MOSFET 4. Comparison between MOSFET and BJT 5. Large-Signal Models and dc Analysis 6. Small-Signal Model and ac Analysis 7. Channel-Length Modulation 8. Body Effect and Capacitances 9. CMOS Inverter References  Sedra and Smith, Microelectronic Circuits, Theory and Applications, Fifth Edition (International Version), Oxford (2004), pp. 325 – 349, pp. 426-429, pp. 901-921. © Chor EF MOSFET-48 MOSFET – Non-Ideal iD-vDS Relationship  For a real (non-ideal) MOSFET, the iD-vDS characteristics in the saturation region is not independent on vDS (c.f. ideal characteristics in slide MOSFET- 21). In fact, there is a slight dependence owing to the Channel-Length Modulation effect*.  The iD-vDS characteristics in the saturation region would then have a slight upward slope, as shown in the figure below.  When the iD-vDS characteristics in the saturation region are extrapolated to the negative vDS-axis, they intersect approximately at the same voltage, - VA, also known as the Early voltage, as an analogy to that in the BJT.  VA = 1/λ, where λ is called the Channel Length Modulation factor.  VA is typically large, e.g., ~100 V; while iD vGS3 λ is small. vGS2 vGS1 - VA vDS *Channel-length modulation has similar effect as the Early Effect in BJT (slide BJT-14). © Chor EF MOSFET-49 MOSFET – Non-Ideal iD-vDS Relationship  With Channel-Length Modulation effect, the iD-vDS characteristics in the saturation region is modified from eqn. (4.2) on slide MOSFET-21 to – 1 𝑊𝑊 2 𝑖𝑖𝐷𝐷 = 𝑖𝑖𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 = 𝜇𝜇𝑛𝑛 𝐶𝐶 𝑣𝑣𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 1 + 𝜆𝜆𝑣𝑣𝐷𝐷𝐷𝐷 = 𝑓𝑓 𝑣𝑣𝐺𝐺𝐺𝐺 , 𝑣𝑣𝐷𝐷𝐷𝐷 (4.17) 2 𝐿𝐿 𝑜𝑜𝑜𝑜 1 𝑊𝑊 2 = 𝜇𝜇𝑛𝑛 𝐶𝐶𝑜𝑜𝑜𝑜 𝑣𝑣𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 1 + 𝑣𝑣𝐷𝐷𝐷𝐷 /𝑉𝑉𝐴𝐴 = 𝑓𝑓 𝑣𝑣𝐺𝐺𝐺𝐺 , 𝑣𝑣𝐷𝐷𝐷𝐷 2 𝐿𝐿 The additional factor 𝜆𝜆𝑣𝑣𝐷𝐷𝐷𝐷 or 𝑣𝑣𝐷𝐷𝐷𝐷 /𝑉𝑉𝐴𝐴 above accounts for the dependence of iD on vDS, or the Channel-Length Modulation effect.  iD is now a function of both vGS and vDS: 𝑖𝑖𝐷𝐷 = 𝑓𝑓 𝑣𝑣𝐺𝐺𝑆𝑆 , 𝑣𝑣𝐷𝐷𝑆𝑆 *.  Small-signal drain current current, 𝑖𝑖𝑑𝑑 , will then be contributed by not only the small-signal gate-to-source voltage, 𝑣𝑣𝑔𝑔𝑔𝑔 , but also the drain-to-source voltage, 𝑣𝑣𝑑𝑑𝑠𝑠 - 𝜕𝜕𝑖𝑖 𝜕𝜕𝑖𝑖 ∆𝑖𝑖𝑑𝑑 = 𝑖𝑖𝑑𝑑 ≈ 𝐷𝐷 |𝑉𝑉𝐺𝐺𝐺𝐺 × 𝑣𝑣𝑔𝑔𝑔𝑔 + 𝐷𝐷 |𝑉𝑉𝐷𝐷𝐷𝐷 × 𝑣𝑣𝑑𝑑𝑑𝑑 (4.18) 𝜕𝜕𝑣𝑣𝐺𝐺𝐺𝐺 𝜕𝜕𝑣𝑣 𝐷𝐷𝐷𝐷 Contribution of 𝑣𝑣𝑔𝑔𝑔𝑔 Contribution of 𝑣𝑣𝑑𝑑𝑑𝑑  Mathematical proof of equation (4.18) is given in Appendix H. * Note the difference between equation (4.2) for an ideal n-MOSFET and equation (4.17). © Chor EF MOSFET-50 MOSFET – Output Resistance ro 1 𝑊𝑊 2  Equation (4.17) - 𝑖𝑖𝐷𝐷 = 𝜇𝜇𝑛𝑛 𝐶𝐶 𝑣𝑣𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 1 + 𝜆𝜆𝑣𝑣𝐷𝐷𝐷𝐷 2 𝐿𝐿 𝑜𝑜𝑜𝑜 1 𝑊𝑊 2 = 𝜇𝜇𝑛𝑛 𝐶𝐶𝑜𝑜𝑜𝑜 𝑣𝑣𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 1 + 𝑣𝑣𝐷𝐷𝐷𝐷 /𝑉𝑉𝐴𝐴 = 𝑓𝑓 𝑣𝑣𝐺𝐺𝐺𝐺 , 𝑣𝑣𝐷𝐷𝐷𝐷 2 𝐿𝐿  For given VGS and VDS (point Q), when vDS changes, iD will change. Change in iD owing to a small change in vDS is given approximately by the slope (or derivative) of the corresponding iD-vDS curve – 𝑖𝑖𝑑𝑑 𝜕𝜕𝑖𝑖 1 𝑊𝑊 1 = 𝜕𝜕𝑣𝑣 𝐷𝐷 |𝑉𝑉𝐷𝐷𝐷𝐷 , 𝑉𝑉𝐺𝐺𝐺𝐺 = 𝜇𝜇𝑛𝑛 𝐶𝐶 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 2 𝜆𝜆 ≈ 𝐼𝐼𝐷𝐷 𝜆𝜆 = 𝑣𝑣𝑑𝑑𝑑𝑑 𝐷𝐷𝐷𝐷 2 𝐿𝐿 𝑜𝑜𝑜𝑜 𝑟𝑟𝑜𝑜 1 𝑊𝑊 1 = 𝜇𝜇𝑛𝑛 𝐶𝐶 𝑉𝑉𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 2 /𝑉𝑉𝐴𝐴 ≈ 𝐼𝐼𝐷𝐷 /𝑉𝑉𝐴𝐴 = (4.19)