Pipelining and Pipeline Hazards PDF

# Definition of Pipelining * Pipelining is the process of arranging hardware elements of the CPU such that its overall performance is increased. * It allows for the simultaneous execution of more than one instruction in a pipelined processor. * In Pipelining, multiple instructions are overlapped i...

# Definition of Pipelining * Pipelining is the process of arranging hardware elements of the CPU such that its overall performance is increased. * It allows for the simultaneous execution of more than one instruction in a pipelined processor. * In Pipelining, multiple instructions are overlapped in execution. ## Non-Pipeline vs. Pipeline * In a non-pipeline system, a process cannot start until the previous process is complete. This leads to performance issues. * In a pipeline, if one process is running on a particular stage, another process can run on a different stage, leading to an overlapping state. ### Pipelining Stages * In pipelining, there are multiple stages, such as instruction fetch(IF), instruction decode(ID), operand fetch (OF), execution (EX), memory access (MEM), and write back (WB). * Instructions pass through these stages sequentially, but the stages themselves can overlap. ### Example of Pipelining Stages | Clock Cycle | IF | ID | OF | EX | MEM | WB | |---|---|---|---|---|---|---| | 1 | I₁ | | | | | | | 2 | I₂ | I₁ | | | | | | 3 | I₃ | I₂ | I₁ | | | | | 4 | I₄ | I₃ | I₂ | I₁ | | | | 5 | I₅ | I₄ | I₃ | I₂ | I₁ | | | 6 | I₆ | I₅ | I₄ | I₃ | I₂ | I₁ | | 7 | I₇ | I₆ | I₅ | I₄ | I₃ | I₂ | | 8 | I₈ | I₇ | I₆ | I₅ | I₄ | I₃ | | 9 | | I₈ | I₇ | I₆ | I₅ | I₄ | | 10 | | | I₈ | I₇ | I₆ | I₅ | | 11 | | | | I₈ | I₇ | I₆ | | 12 | | | | | I₈ | I₇ | ## Pipelining Performance Metrics * **K**: Number of stages in the pipeline * **n**: Number of instructions * **Instructions per clock cycle (IPC)**: The number of instructions completed per clock cycle. * **Speedup**: The ratio of the time taken to execute a program in a non-pipelined system to the time taken in a pipelined system. * **Efficiency**: The percentage of time that the pipeline is actively used. * **Clock cycles needed**: The total number of clock cycles required to execute the program. ## Hazards In Pipelining * **Hazards** are problems that arise in pipelining due to the interdependence of instructions. **Types of Hazards:** 1. **Data Hazards**: Occur when an instruction depends on the result of a previous instruction that has not yet been computed. This can be classified as: * **RAW (Read After Write):** An instruction tries to read a register before it is written by an earlier instruction. * **WAR (Write After Read):** An instruction tries to write a register before it is read by an earlier instruction. * **WAW (Write After Write):** An instruction tries to write a register before it is written by an earlier instruction. 2. **Structural Hazards**: Occur when multiple instructions need to access the same resource at the same time. 3. **Control Hazards**: Occur when the execution flow of the program changes based on a branch condition or a jump instruction. ## Example Of Data Hazards **Consider the following instructions:** * **I₁:** R2 ← R2 + R3 * **I₂:** R5 ← R2 + R4 * **I₃:** IF/D OF EX MEM WB -final value R * **I₄:** IF/D OF EX MEM WB - R2→Read **RAW (Read After Write) Occurs**: I₂ tries to read R2 before I₁ has completed writing to R2, resulting in I₂ using an incorrect value. ## Dealing with Hazards **Solutions:** 1. **Stalling**: Introduce a delay in the pipeline until a hazard is resolved. 2. **Forwarding/bypassing**: Use specialized hardware to bypass the waiting stages and send the result directly to the instruction requiring it. 3. **Resource Duplication**: Use multiple resources (memory, functional units, etc.) to overcome structural hazards. 4. **Reordering**: Change the order of instructions to minimize hazards. **Conclusion:** Pipelining offers significant performance benefits in computer systems, but careful consideration must be given to hazards. By understanding the different types of hazards and implementing appropriate solutions, efficient and high-throughput execution can be achieved.