Pipelining Instruction Processing Lecture Notes (PDF)

Pipelining : Pipelining Instruction Processing (cont’d) 471029: Introduction to Computer Architecture 20th Lecture Disclaimer: Slides are mainly based on COD 5th textbook and also developed in part by Profs. Dohyung Kim @ KNU and Computer architecture course @ KAIST and SKKU...

Pipelining : Pipelining Instruction Processing (cont’d) 471029: Introduction to Computer Architecture 20th Lecture Disclaimer: Slides are mainly based on COD 5th textbook and also developed in part by Profs. Dohyung Kim @ KNU and Computer architecture course @ KAIST and SKKU 1 Control Signals in a Pipeline  For a given instruction  same control signals as single-cycle, but  control signals required at different cycles, depending on stage Option 1: decode once using the same logic as single-cycle and buffer signals until consumed WB Instruction Control M WB EX M WB IF/ID ID/EX EX/MEM MEM/WB Option 2: carry relevant “instruction word/field” down the pipeline and decode locally within each or in a previous stage Which one is better? 2 Pipelined Control Signals PCSrc ID/EX 0 M u WB x EX/MEM 1 Control M WB MEM/WB EX M WB IF/ID Add Add 4 Add result RegWrite Branch Shift left 2 MemWrite ALUSrc Read MemtoReg Instruction PC Address register 1 Read data 1 Read register 2 Zero Instruction Registers Read ALU ALU memory Write 0 Read data 2 result Address 1 register M data u Data M Write x memory u data x 1 0 Write data Instruction 16 32 6 [15– 0] Sign ALU MemRead extend control Instruction [20– 16] 0 ALUOp M Instruction u [15– 11] x 1 RegDst 3 Remember: An Ideal Pipeline  Goal: Increase throughput with little increase in cost (hardware cost, in case of instruction processing)  Repetition of identical operations  The same operation is repeated on a large number of different inputs (e.g., all laundry loads go through the same steps)  Repetition of independent operations  No dependencies between repeated operations  Uniformly partitionable suboperations  Processing an be evenly divided into uniform-latency suboperations (that do not share resources) 4 Instruction Pipeline: Not An Ideal Pipeline  Identical operations … NOT! e.g., R-type, I-type & J-type different instructions  not all need the same stages  Forcing different instructions to go through the same pipe stages  external fragmentation (some pipe stages idle for some instructions)  Uniform suboperations … NOT! e.g., Memory read VS. addition? different pipeline stages  not the same latency  Need to force each stage to be controlled by the same clock  Internal fragmentation (some pipe stages are too fast but all takes the same clock cycle time) e.g., Reg. read & write in 1 clock?  Independent operations … NOT! Waiting data to be produced? instructions are not independent of each other  Need to detect and resolve inter-instruction dependencies to ensure the pipeline provides correct results  pipeline stalls (pipeline is not always moving) 5 Issues in Pipeline Design  Balancing work in pipeline stages  How many stages and what is done in each stage  Keeping the pipeline correct, moving, and full in the presence of events that disrupt pipeline flow  Handling dependences Data  Control  Handling resource contention  Handling long-latency (multi-cycle) operations  Handling exceptions, interrupts  Advanced: Improving pipeline throughput  Minimizing stalls 6 Causes of Pipeline Stalls  Stall: A condition when the pipeline stops moving  Resource contention  Dependences (between instructions)  Data  Control  Long-latency (multi-cycle) operations 7 Dependences and Their Types  Also called “dependence” or less desirably “hazard”  Dependences dictate ordering requirements between instructions  Two types  Data dependence (or data hazard): need to wait for previous instruction to complete its data read/write  Control dependence (or control hazard): deciding on control action depends on previous instruction  Resource contention is sometimes called resource dependence  Also called structural hazard: conflict for use of resource  However, this is not fundamental to (dictated by) program semantics, so we will treat it separately 8 Handling Resource Contention  Happens when instructions in two pipeline stages need the same resource  Suppose: single-ported memory for both instruction and data 9 Handling Resource Contention (cont’d)  Solution 1: Detect the resource contention and stall one of the contending stages  Which stage do you stall?  prioritization  Example: What if you had a single read and write port for the memory?  Solution 2: Eliminate the cause of contention  Duplicate the resource or increase its throughput  E.g., use separate instruction and data memories (caches)  E.g., use multiple ports for memory structures 10 Data Dependences  Types of data dependences  Flow dependence (true data dependence – read after write)  Output dependence (write after write)  Anti dependence (write after read)  Which ones cause stalls in a pipelined machine?  For all of them, we need to ensure semantics of the program is correct  Flow dependences always need to be obeyed because they constitute true dependence on a value  Anti and output dependences exist due to limited number of architectural registers  They are dependence on a name, not a value  We will later see what we can do about them 11 Data Dependence Types Flow dependence r3  r1 op r2 Read-after-Write r5  r3 op r4 (RAW) Anti dependence r3  r1 op r2 Write-after-Read r1  r4 op r5 (WAR) Output-dependence r3  r1 op r2 Write-after-Write r5  r1 op r4 (WAW) r3  r6 op r7 12 Pipelined Operation Example lw $10, sub $11,20($1) $2, $3 lw $10, sub $11,20($1) $2, $3 lw $10, 20($1) Instruction fetch Instruction decode Execution sub $11, $2, $3 lw $10, sub $11,20($1) $2, $3 sub $11,20($1) lw $10, $2, $3 00 M M M uuu Execution Memory Memory Write back Write back xxx 1 11 IF/ID IF/ID IF/ID ID/EX ID/EX ID/EX EX/MEM EX/MEM EX/MEM MEM/WB MEM/WB MEM/WB Add Add Add Add Add Add 44 Add result Add result result Shift Shift Shift left 22 left left 2 Read Read Read Instruction Instruction Instruction PC PC Address Address register 11 register register 1 Read Address Read Read Read data 11 data data 1 Read Read Zero Instruction register 22 register Zero Zero Instruction Instruction Registers Read Registers Read Read ALU ALU ALU ALU ALU memory memory Write 0 00 Address Read Read Read Write Write data 22 data data 2 result result result Address Address 1 11 register register register MM data data data M M M M uuu Data Data Data Data uuu Write Write Write xxx memory data memory memory xxx data data 1 11 0 00 Write Write data data data 16 16 32 32 Sign Sign extend extend extend Clock Clock Clock56 21 43 Clock Clock 13 13