Makefile - GNU C Programming PDF

CST8234 – C Programming C-Make File  What is make? "GNU Make is a tool which controls the generation of executables and other non-source files of a program from the program's source files.” * In other words, make is a tool which help you compile multiple source files and...

CST8234 – C Programming C-Make File  What is make? "GNU Make is a tool which controls the generation of executables and other non-source files of a program from the program's source files.” * In other words, make is a tool which help you compile multiple source files and produces executable files as a result. * https://www.gnu.org/software/make/ 2 Benefits Of make It makes deployment of programmes easier, it hides the details from the end user. It compile files as needed, it only recompiles source files that changed since last compilation, reducing the compile time. Make can be used to compile other programming languages, not just C. Make can be used for more than just compiling files, it can install or uninstall packages for example. Using make make requires a special file called makefile. This makefile tells the tool, called make, what to do when compiling programs. makefile can also include other commands, for example cleaning the environment after complication. Make file content makefile has a number of rules that follow this format: target … : prerequisites … recipe … … The first rule in makefile is considered the default goal, the goal make strive to achieve at the end. Make file content target: usually the name of generated files, it also can be a name for an action to be called later. prerequisites: name of file(s) that is an input to produce the target. Sometimes we may not need any prerequisites for a target, like the case for cleanup. recipe: commands that make execute to produce the target. Keep in mind, recipes must be tab indented in makefile. Example of make file This is how a simple makefile looks like *: edit : main.o kbd.o command.o display.o \ insert.o search.o files.o utils.o cc -o edit main.o kbd.o command.o display.o \ insert.o search.o files.o utils.o main.o : main.c defs.h cc -c main.c kbd.o : kbd.c defs.h command.h cc -c kbd.c command.o : command.c defs.h command.h cc -c command.c * https://www.gnu.org/software/make/manual/make.html#Simple-Makefile Example of make file — con’t… display.o : display.c defs.h buffer.h cc -c display.c insert.o : insert.c defs.h buffer.h cc -c insert.c search.o : search.c defs.h buffer.h cc -c search.c files.o : files.c defs.h buffer.h command.h cc -c files.c utils.o : utils.c defs.h cc -c utils.c clean : rm edit main.o kbd.o command.o display.o \ insert.o search.o files.o utils.o * https://www.gnu.org/software/make/manual/make.html#Simple-Makefile Calling/using make While inside the folder that contains the makefile file, simply use the command make from command line. You can also call targets by writing the target name after make command. This is helpful if we want to run other tasks (more on that later). Using variables in makefile You can declare variables in makefile, which simplifies the file, reduces errors, and leaves it more readable in some cases You declare a variable by using the "=" sign. For example, we can declare a variable called objects to list all “.o” files needed to build edit rule in the previous makefile as follow: objects = main.o kbd.o command.o display.o \ insert.o search.o files.o utils.o edit : $(objects) cc -o edit $(objects) Implicit recipes in make In makefile, we can omit the recipe and let make use the implicit recipe that complies “.o” files from corresponding “.c” files. For example, make will compile main.o file from main.c using the recipe "gcc -c main.c -o main.o", this is possible because both “.o” and “.c” files has the same name. We still need to include the prerequisites for each target though, so that the compilation works correctly. Rewriting the above example objects = main.o kbd.o command.o display.o \ insert.o search.o files.o utils.o edit : $(objects) cc -o edit $(objects) main.o : defs.h kbd.o : defs.h command.h command.o : defs.h command.h display.o : defs.h buffer.h insert.o : defs.h buffer.h search.o : defs.h buffer.h files.o : defs.h buffer.h command.h utils.o : defs.h clean : rm edit $(objects) Simplifying makefile even farther With implicit recipes, we can rewrite our makefiles to group entries by their prerequisites not targets: objects = main.o kbd.o command.o display.o \ insert.o search.o files.o utils.o edit : $(objects) cc -o edit $(objects) $(objects) : defs.h kbd.o command.o files.o : command.h display.o insert.o search.o files.o : buffer.h Running other tasks with make make can run other actions than compiling files, for example it can clean the current directory from the object files. To achieve that, we add another target at the end of the file: clean: rm edit $(objects) Though, to be sure that make will not get confused between these tasks and actual file names, we can use the following formats.PHONY : clean clean : -rm edit $(objects) References For more details about make, Please check the official documentation at https://www.gnu.org/software/make/manual/make.html