Logic Circuits II – Lecture 7: Design of Synchronous Counters PDF

Logic Circuits II – Lecture 7 Design of Synchronous Counters  Design of Synchronous Counters 2 To design a synchronous counter, six steps are required: Step 1: State Diagram The first step in the design of a...

Logic Circuits II – Lecture 7 Design of Synchronous Counters  Design of Synchronous Counters 2 To design a synchronous counter, six steps are required: Step 1: State Diagram The first step in the design of a state machine (counter) is to create a state diagram. A state diagram shows the progression of states through which the counter advances when it is clocked. As an example, the figure below is a state diagram for a basic 3-bit Gray code counter. This particular circuit has no inputs other than the clock and no outputs other than the outputs taken off each flip- flop in the counter. Lecture 7- Logic cct II  3 Step 2: Next-State Table Once the sequential circuit is defined by a state diagram, the second step is to derive a next-state table, which lists each state of the counter (present state) along with the corresponding next state. The next state is the state that the counter goes to from its present state upon application of a clock pulse. The next-state table is derived from the state diagram The table shows the next state diagram for the 3-bit Gray code counter. Q0 is the least significant bit. Lecture 7- Logic cct II  4 Step 3: Flip-Flop Transition Table The table is a transition table for the J-K flip-flop. All possible output transitions are listed by showing the Q output of the flip-flop going from present states to next states. QN is the present state of the flip-flop (before a clock pulse) and QN + 1 is the next state (after a clock pulse). For each output transition, the J and K inputs that will cause the transition to occur are listed. An X indicates a “don’t care” (the input can be either a 1 or a 0). Lecture 7- Logic cct II  5 Step 4: Karnaugh Maps Karnaugh maps can be used to determine the logic required for the J and K inputs of each flip-flop in the counter. There is a Karnaugh map for the J input and a Karnaugh map for the K input of each flip-flop. In this design procedure, each cell in a Karnaugh map represents one of the present states in the counter sequence of the 3- bit Gray code counter. From the J and K states in the J and K flip flop transition table, a 1, 0, or X is entered into each present-state cell on the maps depending on the transition of the Q output for a particular flip-flop. To illustrate this procedure, two sample entries are shown for the J0 and the K0 inputs to the least significant flip-flop (Q0) as shown in the next slide. Lecture 7- Logic cct II  6 Lecture 7- Logic cct II  7 Karnaugh maps for the J and K inputs Lecture 7- Logic cct II  8 Step 5: Logic Expressions for Flip-Flop Inputs From the Karnaugh maps obtained in step 4, you obtain the following expressions for the J and K inputs of each flip-flop: Lecture 7- Logic cct II  9 Step 6: Counter Implementation The final step is to implement the combinational logic from the expressions for the J and K inputs and connect the flip-flops to form the complete the (3-bit Gray code counter) as shown in the figure below: Lecture 7- Logic cct II  10 A summary of the steps used in the design of the 3-bit Gray code counter follows. 1. Specify the counter sequence and draw a state diagram. 2. Derive a next-state table from the state diagram. 3. Develop a transition table showing the flip-flop inputs required for each transition. The transition table is always the same for a given type of flip-flop. 4. Transfer the J and K states from the transition table to Karnaugh maps. There is a Karnaugh map for each input of each flip-flop. 5. Group the Karnaugh map cells to generate and derive the logic expression for each flip-flop input. 6. Implement the expressions with combinational logic, and combine with the flip- flops to create the counter. Note: In general, these steps can be applied to any state machine. Lecture 7- Logic cct II