EE2028 Lecture 3 & 4 ARMv7E-M Instructions PDF

Eg 7: Memory Addressing Comparison The various addressing modes of LDR instruction are ▪ Offset addressing: LDR R2,[R1]; R4,[R3],#4; R5,[R1,#4]; R6,[R4,#4]! @ loads memory contents ▪ PC-relative addressing: LDR R1, NUM1 @ loads the memory contents referenced by the label ▪ Pseudo-in...

Eg 7: Memory Addressing Comparison The various addressing modes of LDR instruction are ▪ Offset addressing: LDR R2,[R1]; R4,[R3],#4; R5,[R1,#4]; R6,[R4,#4]! @ loads memory contents ▪ PC-relative addressing: LDR R1, NUM1 @ loads the memory contents referenced by the label ▪ Pseudo-instruction: LDR R3, =NUM1 @ loads the memory address associated with the label Updated registers: Main Memory Registers 0x00000100 LDR R1, NUM1 PC 0x00000104 LDR R2, [R1] : 0x00000108 LDR R3, =NUM1 R1 0x100 0x0000010C LDR R4, [R3], #4 R2 LDR R1, NUM1 0x00000110 LDR R5, [R1, #4] R3 0x00008004 0x00000114 LDR R6, [R4, #4]! R4 0x104 0x00000118 STR R7, [R3] R5 LDR R2, [R1] : : R6 LDR R2, [R1] NUM1: 0x00008000 0x100 R7 0x7 0x00008004 0x7 : [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 2. Memory Addressing 28 Eg 8: Memory Addressing Application a. Using the assembly instructions you have just learned, find the sum of (A+5) + (B+10) + C & store the result in memory location ANS. Memory locations A & B hold the value of 2 numbers provided by peripheral devices in another subsystem, while C is a time- varying signal & its most updated value will only be available to you just before you assemble your code. [Unless specified otherwise, you may assume all variables are.word-declared by default.] b. What if the numbers 5 & 10 above are stored in the memory instead? At memory address of A +4 & +8 respectively. How would you modify the program to retrieve them & store the new sum? [Hint: pre- or post-index, or both?] Memory A: 0x..40 A’s value 0x..44 5 [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 2. Memory Addressing 0x..48 10 29  Eg 8a: We want ANS ← (A+5) + (B+10) + C, one possible solution… Eg 8a Memory Addressing Application.EQU C, xxx @.equ is always located near the top of the code, so we can conveniently key in the last-minute entry ‘xxx’ LDR R1, A @ PC-Relative load R1 with the value of A LDR R2, B @ another PC-Relative load as above LDR R3, =C @ we want the assembler to substitute C’s value & we want it literally in R3, hence use Pseudo-Instruction ADD R1, #5 @ R1 updated ADD R2, #10 @ R2 updated ADD R4, R1, R2 @ sum the updated R1 & R2, & store the result in R4 ADD R0, R3, R4 @ sum the previous result R4 with R3 & store the result to the default “output” register, R0 @ STR R0, ANS @ at this point we might be prone to issue a PC-Relative STR; but unfortunately, ARMv7E-M does not support it, unlike the more advanced versions. Instead, we’ll have to substitute it with the following two instructions: LDR R5, =ANS @ load R5 with the address of ANS (since we literally want the address, use Pseudo-Instruction, with the equal sign) STR R0, [R5] @ then load the final result in R0 to the memory location pointed.LCOMM ANS 4 by R5, which holds the address of ANS. [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 2. Memory Addressing 30  Eg 8b. We want ANS ← (A+5#) + (B+10#) + C; #in memory. One possibility… Eg 8b Memory Addressing Application.EQU C, xxx @.equ is always located near the top of the code, so we can conveniently key in the last-minute entry ‘xxx’ LDR R1, =A @ Pseudo-Instruction load R1 with the address of A & use it as a pointer LDR R2, B @ PC-Relative load R2 with B’s value LDR R3, =C @ we want the assembler to substitute C’s value & we want it literally in R3, hence use Pseudo-Instruction LDR R4, [R1], #4 @ Post-Index load R4 with A’s value, pointer R1 incremented by 4 LDR R5, [R1] @ Load R5 with value in address of A+4 (e.g. 5) ADD R4, R5 @ R4 = A + value in address of A+4 (e.g. 5) LDR R6, [R1, #4]! @ Pre-index load R6 with value pointed by R1(A+4) +4, (e.g. 10) ADD R6, R2 @ R6 = B + value in address A+8 (e.g. 10) ADD R4, R6 @ R4 = R4 + R6 ADD R0, R3, R4 @ sum the previous result R4 with R3 & store the result to the default “output” register, R0 LDR R5, =ANS @ load R5 with the address of ANS (since we literally want the address, use Pseudo-Instruction, with the equal sign) STR R0, [R5] @ then load the final result in R0 to the memory location pointed.LCOMM ANS 4 by R5, which holds the address of ANS [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 2. Memory Addressing 31 3. ARMv7E-M Ctrl & Arithmetic Instructions 3.1 Move Instructions MOV Assembly language format: Operand2 MOV{S} Rd, Op2 e.g. ADD R0, R1, #0xFF MOV{S} Rd, #imm16 ADD R0, R1, R2 ADD R0, R1, R2, LSL #0x4 Examples: MOV Rd, Rm LDR or STR vs MOV: performs LDR or STR is for transfers Rd  Rm to/from a register from/to memory (hence the [ ]) respectively, while MOV is to transfer to a register MOVS Rd, #value (Rd) an immediate constant value performs or from another register Rd  value N & Z are updated accordingly; C may be updated based on the result of Op2 (e.g. LSL #0x4); V is not affected [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 3. ARMv7E-M Instructions 32 3.1 Move Instructions MOV vs LDR/STR : When to use what? Common Scenarios: Preferred: Bad Ideas: Wrong Ideas: 1. I need a known constant (e.g. 314) to be in a MOV R1, #314 or LDR R1, CONST LDR R1, #314 register (e.g. R1) LDR R1, =314 or CONST:.word 314.equ Pi, 314 LDR R1, =Pi 2. There is a constant in the memory (e.g. CONST) LDR R1, CONST LDR R0, CONST MOV R1, CONST that I can use & I need it to be in R1 CONST:.word 314 MOV R1, R0 CONST:.word 314 CONST:.word 314 3. There is a result in another register (e.g. R0) that MOV R2, R0 STR R0, ANS LDR R2, R0 I can use & I need it to be in R2 LDR R2, ANS 4. There is a result in the memory (e.g. ANS) that LDR R2, ANS LDR R0, ANS MOV R2, ANS or I can use & I need it to be in R2 MOV R1, R0 STR ANS, R2 5. I need to set up a pointer (e.g. with R3) LDR R3, =NUM1 LDR R0, =NUM1 MOV R3, =NUM1 or MOV R3, R0 STR =NUM1, R3 [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 3. ARMv7E-M Instructions 33 3.2 Arithmetic Instructions: ADD, SUB ADD & SUB (Add & Subtract) e.g. Operand2 Assembly language format: ADD R0, R1, #0xFF ADD{S}/SUB{S} {Rd,} Rn, Op2 ADD R0, R1, R2 ADD R0, R1, R2, LSL #0x4 or ADD{S}/SUB{S} {Rd,} Rn, #imm12 If Rd is omitted, destination register is Rn Examples: ADDS R0, R2, R4 while SUB R3, #6 performs performs R0  R2 + R4 R3  R3 − 6 & NZCV are updated accordingly based on the sum in R0 [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 3. ARMv7E-M Instructions 34 3.3 Arithmetic Instructions: MUL, MLA MUL & MLA (Multiply & Multiply with Accumulate, 32-bit result) Assembly language format: MUL{S} {Rd,} Rn, Rm If Rd is omitted, destination register is Rn MLA{S} Rd, Rn, Rm, Ra Example: MUL R0, R1, R2 while MLA R0, R4, R5, R6 performs performs R0  R1  R2 R0  (R4  R5) + R6 ▪ MUL: only the low-order 32 bits of the 64-bit product are written to the destination R0. If the operands are signed, the product will be signed also. The two’s- complement value in R0 is correct if the product fits into 32 bits ▪ MLA: only the low-order 32 bits of the 64-bit result are written to the destination R0 ▪ These 32 bits do not depend on whether signed or unsigned calculations are performed, i.e. the input operands’ signedness is ignored [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 3. ARMv7E-M Instructions 35 3.3 MUL, MLA Related: -L, MLS, S/UDIV To get 64-bit products, use the long versions that come with the L suffix, in either unsigned (U) or signed (S) variants, e.g. UMULL, UMLAL, SMULL, & SMLAL They all treat both their input operands as unsigned/signed integers, regardless of the input operands’ actual binary representations (i.e. signedness) The counterpart of MLA: Multiply with Subtract (MLS) instruction e.g. MLS R0, R4, R5, R6 performs R0  R6 - (R4  R5) Division can either be SDIV or UDIV (Signed/Unsigned Divide) Assembly language format: SDIV {Rd,} Rn, Rm or UDIV {Rd,} Rn, Rm @ Rd  Rn / Rm ▪ divides a 32-bit signed/unsigned integer register value (dividend, Rn) by a 32-bit signed/unsigned integer register value (divisor, Rm), & writes the result to the destination register, Rd or Rn if Rd is omitted ▪ The condition code flags are not affected, hence no S suffix option Did you know we can also do multiplication/division without using these instructions? [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 3. ARMv7E-M Instructions 36 3.4 Compare Instructions CMP & CMN (Compare & Compare Negative) Assembly language format: If S suffix option is not available to the instruction before a conditional branch, CMP Rn, Op2 it is very useful to CMP/CMN ! CMN Rn, Op2 CMP performs: while CMN performs: Rn - Op2 Rn + Op2 & NZCV are updated accordingly based on the result CMP & CMN are similar to SUBS & ADDS respectively, but CMP & CMN do you know discard there istheir a bigarithmetic results difference? [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 3. ARMv7E-M Instructions 37 3.5 Branch Instructions: B, BL, BLX, BX Assembly language format: B{cond} label B: if-else/switch-case; for/while/do-while loop; goto BL{cond} label BL or BLX: from a Caller to a Callee function e.g. to jump to a Subroutine/Function from Main BLX{cond} Rm BX: from a Callee back to the Caller function BX{cond} Rm e.g. to go back to Main, from a Subroutine/Function where: ▪ L: branch with link, i.e. writes the address of the next instruction (in PC) to LR ▪ X: branch indirect, via register Rm that indicates the address to branch to ▪ label: a PC-relative expression indicating the address to branch to ▪ cond: an optional condition code suffix for conditional execution ▪ B{cond} is the only conditional instruction that can be either inside or outside an IT block. All other branch instructions must be unconditional outside an IT block (& must be conditional inside the IT block). (More on IT block later …) [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 3. ARMv7E-M Instructions 38 3.5 Branch Instructions: B B Branch (immediate) Assembly language format: B{cond} label performs: branch to location indicated by label, when condition(s) specified by condition code suffix {cond} is(are) met PC  label Example: CMP R0, R1 BEQ IFEQUAL @ Some instructions for R0, R1 not equal : B SKIPEQUAL IFEQUAL: @ Some instructions for R0, R1 equal : SKIPEQUAL: @ Continue onto the rest of the program B branches to instructions at label IFEQUAL or SKIPEQUAL when R0 & R1 are equal, or R0 & R1 are not equal, respectively [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 3. ARMv7E-M Instructions 39 3.5 Branch Instructions: BL, BLX BL Branch with Link (immediate) Assembly language format: BL{cond} label performs: branch to location indicated by label & write the address of the next instruction to LR, usually when calling a subroutine/function LR  PC; PC  label LR is referred to as R14, PC is referred to as R15 BLX Branch Indirect with Link (Register) in some literature Assembly language format: BLX{cond} Rm performs: branch to location indicated by Rm & write the address of the next instruction to LR, usually when calling a subroutine/function LR  PC; PC  Rm [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 3. ARMv7E-M Instructions 40 3.5 Branch Instructions: BX BX Branch Indirect (Register) Assembly language format: BX{cond} Rm performs: branch to location indicated by Rm PC  Rm Example: BX LR Branch Instructions Summary Example: /Function [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 3. ARMv7E-M Instructions 41 3.5 Branch Instructions: Summary When to use what? Usually, in situations similar to: ✓ If-Else/Switch-Case branch; For/While loop: B{cond} ✓ To jump to a Subroutine/Function from Main: BL or BLX ✓ To go back to Main, from a Function: BX Main Prog 0x……40 Instruction 0x……44 BL or BLX 0x……48 Subsequent Instruction Function 0x…..840 Instructions 0x…..844 … 0x…..848 BX LR (usually) [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 3. ARMv7E-M Instructions 42 4. Conditional Execution Flow of a program can be altered by a two-step process: Step 1: Perform either comparison/test or arithmetic/logic/ move instructions (with suffix S specified) to cause the condition flags (N,Z,C,V) in APSR* to be updated accordingly Step 2: Use Condition Code Suffixes in branch instruction/ IF-THEN (IT) instruction block to perform conditional execution of subsequent instructions *Application Program Status Register 1 2 12 [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 4. Conditional Execution 43 4.1 Condition Code Suffixes or [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 4. Conditional Execution 44 4.2 Conditional Execution: Branch_1 …Recall for B, Branch (immediate) Assembly language format: B{cond} label performs: branch to location indicated by label, when condition... Actually performs: branch to location indicated by label if and only if the condition flags satisfy {cond} PC  label (if and only if the flags satisfy {cond}) ! Example: BEQ LOCATION branches to label LOCATION if Z=1 A loop can thus be implemented if LOCATION refers to the first line of the instruction block that is to be repeated, & for as long as Z=1 when the instruction block ends, or [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 4. Conditional Execution 45 4.2 Conditional Execution: Branch_2 Alternatively, it can also be used to branch to another memory location: Z=? [PC] PC ==1004 1004 Z=1 PC  1100 [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 4. Conditional Execution 46 4.3 Conditional Execution: IT Block_1 IF-THEN (IT) block allows efficient branching whenever If-Then-Else conditions are needed: The conditions can be the same or the logical inverse ! Not more than 4 instructions! [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 4. Conditional Execution 47 4.3 Conditional Execution: IT Block_2 [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 4. Conditional Execution 48 4.3 Conditional Execution: IT Block_3 IT Example 2: Compare and Update Value @ @ @ @ [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 4. Conditional Execution 49 4.4 Conditional Execution: Program E.g. An asm program for adding a list of N numbers (at location labelled N) stored in consecutive memory locations, starting from a location labelled NUM1: LDR R4, =SUM STR R0, [R4] PC-relative STR is not permitted in ARMv7E-M; : : it takes 2 instructions to complete the task. [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 50 5. ARMv7E-M Logic Instructions 5.1 Logic Instructions: AND, ORR, EOR AND, ORR & EOR (bit-wise logic AND, OR & Exclusive-OR) Assembly language format: Recall: Operand2 ADD R0, R1, #0xFF op{S} {Rd,} Rn, Op2 ADD R0, R1, R2 ADD R0, R1, R2, LSL #0x4 where op is one of the above Example: ANDS Rd, Rn, Rm performs the bit-wise logic AND of the operands in registers Rn & Rm, writes the result into register Rd. N & Z are updated accordingly, C may be updated based on the result of Op2 (e.g. LSL #0x4, see Shift), V is not updated in all logic instructions [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 5. ARMv7E-M Logic Instructions 51 5.2 Logic Instructions: MVN (NOT) MVN (Move NOT: bit-wise logic NOT) Assembly language format: MVN{S} Rd, Op2 performs a bit-wise logic NOT operation on the value of Op2, & places the result into Rd. Rd  (~Op2) Example: MVNS Rd, Rn performs the bit-wise logic NOT on Rn, writes the result into register Rd. N & Z are updated accordingly, C may be updated based on the result of Op2 (e.g. LSL #0x4), V is not updated in all logic instructions [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 5. ARMv7E-M Logic Instructions 52 5.3 Shift & Rotate Instructions_1 LSL Logical Shift Left LSR Logical Shift Right The range of n (shift length) ASR Arithmetic Shift Right for the various instructions: ROR Rotate Right LSL: 0 to 31 RRX Rotate Right with Extend LSR, ASR: 1 to 32 ROR: 1 to 31 Assembly language format: op{S} Rd, Rm, Rs where op is one of the top 4, Rs & op{S} Rd, Rm, #n n (shift length) limited to =>2 (i.e. Op2) If R1 = 0xA0000014 (1010…. ….01 0100)2 R1>>2 = 0xE8000005 (1110 10.. ….00 0101)2 which results in 0xE8000005 being written to R0 The most significant bit (sign bit) of R1 is being copied in every shift, i.e. for n times Carry flag is finally cleared, due to the 0 in the original nth position (n=2 in this ASR) of R1 before the shift [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 5. ARMv7E-M Logic Instructions 55 5.4 Test Instructions TST & TEQ (Test & Test Equivalence) Assembly language format: TST Rn, Op2 TEQ Rn, Op2 TST performs: bit-wise logic AND of the two operands TEQ performs: bit-wise logic Exclusive OR of the two operands Both update N & Z accordingly; C may be updated based on the result of Op2 (e.g. LSL #0x4); V is not affected TST & TEQ are similar to ANDS & EORS respectively, but they discard results [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 5. ARMv7E-M Logic Instructions 56 5.4 Test Instructions: Examples Checking a specific bit TST R3, #1 @ bit-wise logic AND sets Z = 1 if the least significant bit of R3 is 0 sets Z = 0 if the least significant bit of R3 is 1 (useful for checking status bits in I/O devices) Checking for a specific bit pattern TEQ R2, #5 @ bit-wise logic Exclusive OR sets Z = 1 if R2 equals 5 sets Z = 0 otherwise (useful for testing the flags in peripheral control registers) [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 5. ARMv7E-M Logic Instructions 57 5.5 Masking Instructions BIC & ORN (Bit Clear & OR NOT) ▪ BIC performs an bit-wise AND on the bits in Rn with the complements of the corresponding bits in the value of Op2. ▪ ORN performs an bit-wise OR on the bits in Rn with the complements of the corresponding bits in the value of Op2. Assembly language format: op{S} {Rd,} Rn, Op2 where op is one of the above BIC performs: while ORN performs: Rn  Rn & (~Op2) Rn  Rn | (~Op2) If Rd is omitted. [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 5. ARMv7E-M Logic Instructions 58 5.5 Masking Instructions: E.g. BIC & ORN are very useful for clearing or setting one or more bits in hardware configuration words Example: BIC R0, R1 @ R0  R0 & (~Op2) If R0 = 0x02FA62CA, & R1 = 0x0000FFFF, ~R1 = 0xFFFF0000, which results in 0x02FA0000 being written to R0 What would ORN R0, R1 produce? (~Op2) is known as the bitmask BIC is useful for masking OFF, i.e. clearing bit(s) ORN is for masking ON, i.e. setting bit(s) [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 5. ARMv7E-M Logic Instructions 59 6. Stack & Subroutines/Functions Stack: an efficient memory usage model where data is saved/ recalled in a Last-In-First-Out manner & address specified by SP Stack Types: ARM supports 4 different stack implementations, categorised by two axes, namely Empty vs Full & Ascending vs Descending: ▪ Empty stack: SP points to the next free location on the stack, i.e. the location where the next item to be pushed onto the stack will be stored. ▪ In a Full stack, the stack pointer points to the most recent item in the stack, i.e. the location of the last item pushed onto the stack. ▪ An Ascending stack grows upwards: it starts from a low memory address &, as items are pushed onto it, progresses to higher memory addresses. ▪ A Descending stack grows downwards: it starts from a high memory address, & as items are pushed onto it, progresses to lower memory addresses. [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 6. Stack & Subroutines/Functions 60 6. Stack: Cortex-M4 Cortex-M4 Stack: can be software-controlled or carried out automatically when enter/exit an exception/interrupt handler; Full-Descending stack Common use: to save Register contents before some data processing & then restore those contents from the stack after the processing task is done Stack type? [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 6. Stack & Subroutines/Functions 61 6.1 Stack: Instructions Assembly language format: PUSH reglist (Push registers onto stack) They are not OPTIONALs ! POP reglist (Pop registers off stack) where reglist is a non-empty list of register(s), enclosed in braces. It can contain a register range, e.g. {R0-R7} or more than one register or register range, which must be comma separated, e.g. {R0, R1-R3, R5-R7} SP (R13) is auto-decremented/incremented respectively E.g.: PUSH {R0} POP {R0} performs performs R13  R13 - 4 R0  Memory [R13] followed by followed by Memory [R13]  R0 R13  R13 + 4 [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 6. Stack & Subroutines/Functions 62 6.2 Stack: Practical Considerations Avoid unnecessary PUSH & POP – they are relatively expensive operations in terms of CPU cycles For the stack to work as expected, always perform PUSH & POP in pairs, and preferably with the same reglist R7 &/or R11 are often used as the default Frame Pointers (which point to the current stack frame of a function) – avoid using them to prevent overwriting these return addresses accidentally The highest numbered register will be PUSHed first & POPed last, & vice versa, irrespective of the order of registers in the reglist [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 6. Stack & Subroutines/Functions 63 6.3 Stack: Operation Details E.g. initial SP set to point at: 0x20008000 (always empty) ▪ SP (R13) always points to the last data pushed into stack memory ▪ When PUSH, SP decrements by 4 or multiples of 4 (if several registers are saved) before new data is inserted Full-Descending Stack type? Initial SP: 0x20008000 SP after PUSH, e.g. 0x20007FFC ▪ When POP, SP increments by 4 or multiples of 4 (if several registers are recalled) after data is copied (What happen to stack’s contents after POP?) [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 6. Stack & Subroutines/Functions 64 6.4 Subroutines/Functions_Method 1 Subroutines (software-controlled stack operation): Manually PUSH registers that will be modified in the subroutine, then POP them at the end of the subroutine to restore their original contents Multiple-registers PUSH & POP are similar to multiple-word STR & LDR respectively (refer to STM & LDM for details, not in syllabus) /Function [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 6. Stack & Subroutines/Functions 65 6.4 Subroutines/Functions_Method 2 Subroutines (software-controlled stack operation): Manually PUSH registers that will be modified & LR in the subroutine, then POP registers at the end to restore their original contents & LR into PC, thus combining POP & BX LR into one instruction. /Function [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 6. Stack & Subroutines/Functions 66 Armv7E-M Instructions Summary_1 [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS 67 Armv7E-M Instructions Summary_2 [T]EE2028 Lectures 2, 3 & 4: ARM Assembly Language © Dr Henry Tan, ECE NUS THE END 68