Intel 80286 Architecture PDF

INTEL 80286 16 bit MP (with 8 MHz, 10 MHz & 12.5 MHz clock frequencies). Used for multiuser/multitasking applications 6 times faster than standard 5MHz 8086 MP. Data bus 16 bits(D0-D15). Address bus 24 bits(A0-A23). Physical memory (224 =16 MB) Virtual Memory=1GB 2...

INTEL 80286 16 bit MP (with 8 MHz, 10 MHz & 12.5 MHz clock frequencies). Used for multiuser/multitasking applications 6 times faster than standard 5MHz 8086 MP. Data bus 16 bits(D0-D15). Address bus 24 bits(A0-A23). Physical memory (224 =16 MB) Virtual Memory=1GB 2 Operating modes: Real and PVAM(Protected Virtual Address Mode). Architecture of 80286  Architecture of 80286 (cont..) It contains four separate processing units: (i) The bus unit (BU) (ii) The instruction unit (IU) (iii) The execution unit (EU) (iv) The address unit (AU) I. The bus unit (BU): It provides all memory and I/O read and write operations. The prefetcher in the BU prefetches instructions of up to 6 bytes and places them in a queue. II. The instruction unit (IU): It decodes up to 3 prefetched instructions and places them in a queue for execution by the EU.  Architecture of 80286 (cont..) III. The execution unit (EU): It executes instructions from the IU sequentially. It contains an 8086 flag register, general-purpose registers, pointer registers, index registers and one 16-bit additional register called machine status word (MSW) register. IV.The address unit (AU): It calculates physical address that will be sent out to memory or I/O by the BU. If 80286 is operating in real address mode, the AU computes 20-bit addresses using a segment base and an offset just like 8086. In this mode, pins A20-A23 are zeros and A0-A19 (20 bits) are only used so the maximum physical address it can access is (220 )1MB.  Architecture of 80286 (cont..) IV.The address unit (cont..) If 80286 is operating in protected virtual address mode, the AU functions as a complete MMU. In this mode, 80286 uses all 24 address lines to access up to (224 ) 16 MB of physical memory. In this mode, it also provides up to 1 GB of virtual memory.  Description of Pins Major Groups: Address Bus(A0-A23/24 bits) Data BusBus(D0-D15/16 bits) Memory Interface DMA Interface Interrupt Interface Processor extension Power Supply Clock Interface Processor extensions (coprocessors): Four pins are provided to interface the 80286 with a coprocessor. – PEREQ (Processor Extension Request) – PEACK’ (Processor Extension Acknowledge) – BUSY’ (’ indicates low active) – ERROR’  PEREQ PEACK Intel BUSY’ Coprocessor ’ 80286 80287 ERROR ’ Cont… The processor extension request (PEREQ) Input pin will be asserted by a coprocessor to tell the 80286 to perform an operation. When the 80286 gets around, it asserts the processor extension acknowledge (PEACK’) signal to the coprocessor as an acknowledgement. During the operation, 80286 executes a WAIT instruction, it will remain in a WAIT loop until it finds the BUSY’ signal from the coprocessor high. If a coprocessor finds some error during processing, it will assert the ERROR’ Input of the 80286.  REAL MODE-80286 Configured on system reset. 80286 computes 20-bit physical address by shifting the 16-bit segment address four times to the left add four zeros to the right and then adds the 16-bit offset, just like the 8086.(as shown in the next slide). Like 8086 uses 20 bit Address bus(A0-A19)(00000H-FFFFFH). Physical Memory=1MB In this mode 80286 reserves 2 areas of Memory: Ø system initialization(FFFF0H-FFFFFH) Ø IVT(0000H:0000H to 0000H:03FFH) 15 0 SEGMENT 0000 ADDRESS 15 0 OFFSET ADDER 20 BIT PHY MEM ADDRESS  Ex: [CS]=4000H [IP]=0022H Then the 20 bit physical Address in real mode is calculated as 40000H+0022H=40022H  List of Registers used in 80286 8 no of 16 bit GPR- AX,BX,CX,DX,SP,BP,SI,DI 4 no of 16 bit Segment Registers- CS,DS,SS,ES 16 bit IP Special Registers in PVAM Mode 16 bit MSW(Machine status Word) LDTR (Local Descriptor Table Address) GDTR (Global Descriptor Table Address) 4 no of special registers called Segment Descriptor Cache/ Invisible/Shadow Registers But before switching to protected mode(PVAM), initialize and set up descriptor tables. initialize registers like GDTR,LDTR etc. load the main part of OS from disc to memory and enable interrupt. And then switches to protected mode by setting the PE bit in MSW register.  PVAM Mode-80286 For switching to protected mode protection enable bit [PE bit(D0 Bit)] in the machine status word (MSW) register in the 80286 is set to 1. Program:  Program Explanation Ex: [CX] [MSW] [CX]=0000H [CX] Ored 01H 0000000000000000 OR 00000001 0000000000000001 [MSW] [CX] Physical Memory Structure of 80286 (Address Bus=24 bits) FFFFFFH Address=24 bits Each Location can store 8bit data. 10 000000H= 9 8 0000 0000 0000 0000 0000 0000 bits 2 1 0 000000H Virtual / Logical Address in Program 31 0 SELECTOR OFSET SEGMENT REGISTER CS + / DS / SS / ES 15 0 DS INDEX GDT RP OR LDT TI SEGMENT x8 BASE 24 \BIT BASE ADRESS OF + THE MEMORY SEGMENT PHYSICAL MEMORY GDTR SEGMENT OR DESCRIPTOR TABLE BASE LDTR CACHE PHYSICAL MEMORY  Memory Management in 80286 in PVAM mode Conversion of Virtual/Logical Address(32 bits) to Physical Address(24 bits). Virtual /Logical Address: 32 bits (16 bit selector +16 bit offset.) The content of segment register are called selector in PVAM mode. 16 bit selector: 2bits RPL(RPL is request privilege level) + I bit TI+ 13 bits Index The 13-bit index is used to find particular descriptor entry from the selected descriptor table. This selected descriptor contains the 24 bit physical address of the required segment to which the 16 bit offset is added to get the final 24 bit physical address.  TI is Table Indicator. TI=0; Global Descriptor Table (GDT)used. TI=1; Local Descriptor Table(LDT) used.  How? 2 Registers used GDTR and LDTR Cache. GDTR stores base address of GDT Table and LDTR Cache of LDT Table. Tables Address calculated as: Base Address(GDTR/LDTR Cache)+ (13 bits of Index from selector)X 8. X8 as each descriptor is 8 bytes wide. GDT/LDT contains descriptor where each descriptor describes about 1 memory segment.  LDT stores descriptors for the segments dedicated for a particular user. GDT stores descriptors for the segments which are shared by all the users. From one of these descriptors the 24 bit base address of the physical memory segment is obtained added to the offset address to reach the physical memory segment. Virtual Address space= 213 X 2(Tables:LDT&GDT) X 216 =230=1GB Where 213 =Maximum no of Descriptors in 1 Table 216 =Maximum Length of each Memory segment.  Q. Determine the Physical Address of a Memory Segment if Virtual Address reads 0008:0024H and Base Address in the Descriptor is 420000H.Also tell it will access GDT or LDT. Sol: (a)Physical Address: 420000H(Base)+0024H(Offset)=420024H (b)TI=0(D2 bit of selector): so GDT to be accessed. Concept: Cache/ Invisible Registers Physical Memory Two stage CS/DS/SS/ES access to (16 bit memory Intel Registers) 80286 (selector) ’ ’ Required DESCP Table ’ Memory CS/DS/SS/ES Descp Segment Cache Registers Information (LDT/G (6 Bytes) DT) Directly Segment Descriptor Cache Register or Invisible or Shadow Register Segment Register 8-bit 24-bit CS 16-bit Access Physical base DS Limit Right Byte Address SS CS Cache ES DS Cache 15 0 SS Cache (Selector) ES Cache Program 47 0 6 byte Visible Program Invisible Loaded by the (Loaded form the Descriptor Table) Programmer  INVISIBLE/SEGMENT DESCRIPTOR CACHE/SHADOW REGISTERS Concept of caching introduced in 286 to minimize the time required for fetching the frequently required descriptor information from LDT/GDT present in physical Memory. The 80286 contains a number of special registers called shadow registers. The shadow registers are internal and cannot be accessed by instructions. Therefore, these registers are also called Program Invisible Registers/Cache Registers. A 6 byte Cache Register is assigned to each of the 4 segment registers CS, DS, SS and ES. Also LDTR register has its cache Register. Shadow Registers / Program Invisible Registers The descriptor is of 8 bytes from which 2 bytes are intel reserved so 6 bytes of information loaded to Cache Registers. These are provided to speed up memory references. When the selector is not changed, i.e., it still points to the same segment and all the details are present in the processor itself. Only when the segment selector is loaded with a new value then it accesses the descriptor in the memory and all the information's are automatically loaded from descriptor to the cache part of segment register.  Once loaded all information regarding memory segment obtained from cache register instead of referring to LDT/GDT in the physical memory for descriptor again and again. Cache registers not available for programming. They get reloaded when segment register is loaded with a selector value.  Virtual Address in Program 31 15 0 SELECTOR OFSET SEGMENT REGISTER CS + / DS / SS / ES HIDDEN SEGMENT REGISTER VISIBLE 15 0 47 0 ACCES DS INDEX RIGHT 24 BIT BASE LIMIT GDT RP OR LDT TI SEGMENT x8 BASE DESCRIPTOR (LOADED INTO HIDDEN + PART OFSEGMENT PHYSICAL MEMORY REGISTER) GDTR OR DESCRIPTOR TABLE BASE LDTR CACHE PHYSICAL MEMORY  Descriptor Tables and Concept of GDTR/LDTR Registers The single-bit TI in selector tells the 80286 to select one of the two tables: – GDT (Global Descriptor Table); if TI=0. – LDT (Local Descriptor Table);if TI=1. All tasks in 286 can share some common memory segments pointed by GDT(Global Descriptor Table) whereas each individual task has its own local memory segments pointed by LDT(Local Descriptor Table).(shown in subsequent slide). Location of GDT is pointed by GDTR register. GDTR contains the 24bit base address & 16 bit limit of GDT, whereas LDTR stores a 16 bit selector.  TASK 1 LOCAL TASK 1 ADDRESS VIRTUAL ADDRESS SPACE SPACE LDT1 TASK 2 GLOBAL VIRTUAL ADDRESS SPACE ADDRESS SPACE GDT TASK 3 TASK 2 LOCAL LOCAL ADDRESS ADDRESS SPACE SPACE LDT3 LDT2 TASK 3 VIRTUAL ADDRESS SPACE  The global descriptor table’s (GDT) base address is stored in GDTR. But, LDTR holds 16 bit selector.  LDTR is loaded with a 16 bit value that is used as a selector to point to one of the entries in GDT, which is automatically copied to the LDTR Cache or the hidden part of LDTR and that points to the current LDT for that task.  CONCEPT OF GDTR AND LDTR REGISTERS CPU  MEMORY  15 0 LDT DESCRIPTOR GDT LIMIT 23 GDT + GDT BASE 24-BIT PHYSICAL ADDRESS 15 0 x8 LDT1 LDTR SELECTOR CURRENT LDT LDTR 47 CACHE 15 0 LDT BASE LDT LDT0 ACCESS 24-BIT LIMIT RIGHTS PHYSICAL BYTE ADDRESS INCREASING MEMORY PROGRAM INVISIBLE ADDRESS (AUTOMATICALLY LOADED FROM LDT DESCR WITHIN GDT   Q. Ifthe limit and base address in GDTR are 0FFFH and 001000H , respectively , What will be the starting address and ending address of the table and size of the table in bytes and How many descriptors can be stored in the table. Solution: Given: Base Address (24Bit) = 0010 00 H Limit (16-bit)= 0FFF H (i) Beginning address = 001000H (ii) Ending Address = 001FFFH (iii)Total no of Bytes in Table=Decimal eqv of limit+1 0FFF H==(0X16^3)+(15X16^2)+(15X16^1)+15 = 4095+1= 4096 bytes (iv)Total no of Descriptors = 4096/8 =512  When TI=0, it points to GDT. The 13 bit index is multiplied by 8 (as each descriptor is 8 bytes). This is added to the GDT base (available from GDTR) to point to the required descriptor, which contains all the information's about the required segment.  Virtual Address in Program IF TI=0 31 15 0 SELECTOR OFSET SEGMENT REGISTER CS + / DS / SS / ES HIDDEN SEGMENT REGISTER VISIBLE 15 0 47 0 ACESS DS INDEX RIGHTS 24 BIT BASE LIMIT GDT RP TI SEGMENT x8 BASE DESCRIPTOR (LOADED INTO HIDDEN + PART OFSEGMENT PHYSICAL MEMORY REGISTER) GDTR DESCRIPTOR TABLE BASE PHYSICAL MEMORY  When TI=1, it points to LDT. The LDTR acts as a selector to access a descriptor in the GDT and this GDT entry is automatically copied to the LDTR cache, which now points to the current LDT. Then the index of the segment selector is multiplied by 8 and is added to the LDT base (available in LDTR CACHE) to point to the required descriptor which contains all the information about the segment. 80286 then obtains the 24 bit physical address by adding the segment base address(from the descriptor) or from Invisible/shadow registers with the 16 bit offset address.  IF TI=1 SEGMENT DESCRIPTOR ACCES 24BIT OFFSET INDEX LIMIT + RIGHT BASE CACHE SEGMENT SELECTOR SS/DS/SS/ES LDT + x8 DESCRIPTOR MEMORY SEGMENT x8 DESCRIPTOR + PHYSICAL MEMORY SEGMENT LDT GDT GDTR 24 24BIT LDTR ACCES LIMIT BIT BAS4E SELECTOR LAYER BASE ADDRESS LDTR CACHE GDTR  THE 80286 GETS SELECTOR FROM A SEGMENT REGISTER GDT IS TO BE ACCESSED, TI=0 WHOSE LOCATION IN TI = 0/1 EXTERNAL MEMORY IS GIVEN BY GDTR TI=1 SELECTOR IN LDTR REGISTER ACCESSES A DESCRIPTOR IN THE GDT AND THIS GDT ENTRY IS COPIED TO THE LDTR CACHE, WHICH NOW POINTS TO THE CURRENT LDT (13-BIT INDEX FROM THE 16-BIT SEGMENT SELECTOR * 8) +24 BIT GDT BASE ADDRESS FROM GDTR/ 24 BIT CURRENT LDT BASE ADDRESS FROM LDTR CACHE. 80286 THEN ACESSSES THE SEGMENT DESCRIPTOR FROM THIS ADDRESS IN THE CORRESPONDING TABLE. THE 80286 DETERMINES THE SEGMENT BASE ADDRESS FROM THE DESCRIPTOR, WHICH IS ALSO COPIED TO THE SEGMENT DESCRIPTOR CACHE THE 80286 THEN OBTAINS THE 24 BIT PHYSICAL ADDRESS BY ADDING THE SEGMENT BASE ADDRESS WITH THE OFFSET THE 80286 THEN ACCESSES THE SELECTED 24 BIT PHYSICAL ADDRESS Fig:- Flowchart showing steps for generating 24 bit Physical Address  Descriptor Table and Descriptor (cont..) There are (2^13)8192 descriptors in GDT and (2^13)8192 descriptors in LDT... 8191 Descriptor Each descriptor is of 8 bytes... Descriptor. 11 Eachdescriptor describes the starting address, length, and Descriptor 10. access rights information of a particular memory segment. Descriptor 9 Descriptor 8 Descriptor 7 Descriptor 6 Descriptor 5 Descriptor 4 Descriptor 3 Descriptor 2 Descriptor 1 Descriptor 0  Code/Data Segment Descriptor Structure Total =8 bytes 6 byte used, 2 bytes are Intel Reserved. 0,+1=Signifies limit, 16 bit(0000-FFFFH) +2,+3,+4=Signifies the base Address , 24 bits(000000H-FFFFFFH) +5=Specifies Access Rights Byte +6,+7=Intel Reserved  Code or Data Segment Descriptor 7 0 7 0 +7 +6 INTEL RESERVED* +5 P DPL S TYPE A BASE23-16 +4 ACCESS INTEL RESERVED* RIGHTS BYTE P DPL BASE15-0 +2 +3 S TYPE A +1 LIMIT15-0 BASE23-16 0 BASE15-0 LIMIT15-0 15 8 7 0 * Must be to for compatibility with IAPX 386 Physical Memory Segment  Access Right Byte Definition Bit Name Function Position 7 Present (P) P=1 Segment is mapped into physical Memory P=0 No mapping to physical memory exists,. 6-5 Descriptor Privilege Level (DPL) 00/01/ Segment privilege level used in privilege test. 10/11 4 Segment S=1 Code or data (includes stacks) segment descriptor Descriptor (S) S=0 System Segment Descriptor or Gate Descriptor T 3 Executable (E) E=0 Data segment descriptor type is: Y 2 If Data Expansion Direction ED = 0 Expand up segment,. P 1 Segment (ED) ED = 1 Expand down segment,. (S = 1, E Writeable (W) W=0 Data segment may not be written into E = 0) W=1 Data segment may be written into T 3 Executable (E) E=1 Code segment Descriptor type is: If Code Y 2 Conforming (C) C=1 Code segment may only be executed with condition. Segment P. (S = 1, E 1 Readable (R) R=0 Code segment may not be read. E=1 R=1 Code segment may be read. 0 Accessed (A) A= 0 Segment has not been accessed. A= 1 Segment has been accessed. Q. If Access Rights byte reads FF H , then what information d o yo u get re ga rd i n g t h e m e m o r y s e g m e nt. I f t h e corresponding selector stores a value 0008H, can this memory segment be accessed? Sol: FFH= 11111111 P=1; Segment is mapped into physical Memory DPL=11; Memory privilege level 3 S=1; Code or data segment descriptor Type=111; Code segment Descriptor. May only be executed with condition. Code segment may be read A=1; Segment has been accessed. Sol: Selector= 0008H=0000 0000 0000 1000 RPL=00 H(given):Request privilege level 0(Highest) DPL=11; Memory privilege level 3(Lowest) Check condition: RPL>= DPL? YES; So access granted.