VHDL Introduction PDF

DE Module 5 VHDL - Introduction Contents Overview of different design styles Design and implementation of adder, subtractor, multiplexer and flip flop using VHDL Introduction  Hardware description languages (HDL) ◼ Language to describe hardware ◼ Two popular languages...

DE Module 5 VHDL - Introduction Contents Overview of different design styles Design and implementation of adder, subtractor, multiplexer and flip flop using VHDL Introduction  Hardware description languages (HDL) ◼ Language to describe hardware ◼ Two popular languages  VHDL: Very High Speed Integrated Circuits Hardware Description Language ◼ Developed by U.S.DOD from 1983 ◼ IEEE Standard 1076-1987/1993/200x ◼ Based on the ADA language  Verilog ◼ IEEE Standard 1364-1995/2001/2005 ◼ Based on the C language 12/1/2024 DDRA,Amaya pethe 3 Applications of HDL  Model and document digital systems ◼ Different levels of abstraction  Behavioral, structural, etc.  Verify design  Synthesize circuits ◼ Convert from higher abstraction levels to lower abstraction levels 12/1/2024 DDRA,Amaya pethe 4 Features of VHDL  It allows behaviour of the required system to be Described(Modelled)&Verified(simulated)before synthesis tools translate design into real hardware  Allows the description of concurrent systems  A VHDL project is Multipurpose  Supports Hierarchies: Flexible design methodology-Top-down, bottom-up, or both 12/1/2024 DDRA,Amaya pethe 5 Features of VHDL  Supports different types of Modelling Behavioural(Sequential statement model [like a program]) Dataflow (concurrent statement modelling) Structural (for connecting components)  Has elements to make large-scale design easier e.g., components, functions, procedures, packages, configuration  Test Benches can be written in the same language Circuits can be verified before synthesis 12/1/2024 DDRA,Amaya pethe 6 Structure of VHDL code Library Declaration Entity Architecture Configuration 12/1/2024 DDRA,Amaya pethe 7 Library Declaration  To make a package visible to the design, two declarations are needed one for the LIBRARY where the package is located(e.g.ieee,std,work)  The other a USE clause pointing to the specific package. The corresponding syntax is shown below LIBRARY library_name; USE library_name.package_name.all; At in least three packages from three different libraries are usually needed a design: ieee.std_logic_1164(from ieee library) standard(from standard library) work(work library) LIBRARY ieee; USE ieee.std_logic_1164.all; Declarations LIBRARY std; USE std.standard.all; LIBRARY work; USE work.all; 12/1/2024 DDRA,Amaya pethe 8 Entity  Entity describes the external view of the device made  It has at least one architecture associated with it  Entity declaration specifies the name of the entity being modeled and list of interface ports  Ports are signals for communicating with other devices(Terminals)  We specify input, output ports in entity  Any design we do is an Entity in VHDL 12/1/2024 DDRA,Amaya pethe 9 Entity Syntax ENTITY entity_name IS Port( Port_name : signal_mode signal_type; Port_name : signal_mode signal_type ); END entity _name; 12/1/2024 DDRA,Amaya pethe 10 Rules to write entity name The first letter of the entity should be alphabet. Special characters should not be allowed except underscore(_). Two underscore(_) continuously not allowed. The last cannot end with special character. 12/1/2024 DDRA,Amaya pethe 11 Signal Modes  Signal Mode : in- specified when a signal should be taken as input Out- specified when a signal should be taken as output inout- specified when a signal should be taken as both in and out buffer- specified when a signal should be temporarily stored For eg: counter state, Shift register state etc. 12/1/2024 DDRA,Amaya pethe 12 Signal Types  Commonly used Signal Types : bit bit_vector std_logic std_logic_vector 12/1/2024 DDRA,Amaya pethe 13 Entity declaration of a circuit  Example: my_ckt ◼ Inputs: A, B, S ◼ Outputs: X, Y A  VHDL description: X B my_ckt entity my_ckt is Y port ( S A: in bit; B: in bit; S: in bit; X: out bit; Y: out bit); end my_ckt ; 12/1/2024 DDRA,Amaya pethe 14 Write entity declaration for NOR gate entity nor_gate is Port (A,B: in STD_LOGIC; Y : Out STD_LOGIC; ) end nor_gate; 12/1/2024 DDRA,Amaya pethe 15 Architecture Body VHDL architecture can be done in three ways 1. As a set of concurrent statements: Dataflow way-Logic equations 2. As a set of sequential statements: Behavioural way –Truth table 3. As a set of interconnected components: Structural way-connections 12/1/2024 DDRA,Amaya pethe 16 Syntax of Architecture 12/1/2024 DDRA,Amaya pethe 17 VHDL Operators  Assignment Operators  Logical Operators  Relational Operators  Shift Operators  Adding Operators  Multiplying Operators  Miscellaneous Operators 12/1/2024 DDRA,Amaya pethe 18 Assignment Operators  Used to assign values to signals, variables and constants. Used to assign values to individual vector elements or with OTHERS. 12/1/2024 DDRA,Amaya pethe 19 Logical Operators  The seven Logical Operators(Type of operand- Bit, Type of result-Bit) ◼ AND ◼ OR ◼ NAND are not associative ◼ NOR are not associative ◼ XOR ◼ XNOR ◼ NOT ; highest precedence over the others 12/1/2024 DDRA,Amaya pethe 20 Relational Operator  = Equality  /= Inequality  <   >= Must be one-dimensional discrete array of the same type. 12/1/2024 DDRA,Amaya pethe 21 Shift Operators  Sll: Shift left logical-Position on right filled with zero  Srl: Shift right logical-logical-Position on left filled with zero  Sla: Shift left arithmetic-Position of rightmost is repeated  Sra: Shift right arithmetic-Position of leftmost is repeated  Rol Rotate left  Ror Rotate Right 12/1/2024 DDRA,Amaya pethe 22 Adding Operators  + addition  - subtraction  & Concatenation Example: A = 1010 B = 1000 C